[mirror_ubuntu-artful-kernel.git] / arch / sparc64 / kernel / sun4v_ivec.S

/* sun4v_ivec.S: Sun4v interrupt vector handling.
 *
 * Copyright (C) 2006 <davem@davemloft.net>
 */

#include <asm/cpudata.h>
#include <asm/intr_queue.h>

	.text
	.align	32

sun4v_cpu_mondo:
	/* Head offset in %g2, tail offset in %g4.
	 * If they are the same, no work.
	 */
	mov	INTRQ_CPU_MONDO_HEAD, %g2
	ldxa	[%g2] ASI_QUEUE, %g2
	mov	INTRQ_CPU_MONDO_TAIL, %g4
	ldxa	[%g4] ASI_QUEUE, %g4
	cmp	%g2, %g4
	be,pn	%xcc, sun4v_cpu_mondo_queue_empty
	 nop

	/* Get &trap_block[smp_processor_id()] into %g3.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g3
	sub	%g3, TRAP_PER_CPU_FAULT_INFO, %g3

	/* Get CPU mondo queue base phys address into %g7.  */
	ldx	[%g3 + TRAP_PER_CPU_CPU_MONDO_PA], %g7

	/* Now get the cross-call arguments and handler PC, same
	 * layout as sun4u:
	 *
	 * 1st 64-bit word: low half is 32-bit PC, put into %g3 and jmpl to it
	 *                  high half is context arg to MMU flushes, into %g5
	 * 2nd 64-bit word: 64-bit arg, load into %g1
	 * 3rd 64-bit word: 64-bit arg, load into %g7
	 */
	ldxa	[%g7 + %g2] ASI_PHYS_USE_EC, %g3
	add	%g2, 0x8, %g2
	srlx	%g3, 32, %g5
	ldxa	[%g7 + %g2] ASI_PHYS_USE_EC, %g1
	add	%g2, 0x8, %g2
	srl	%g3, 0, %g3
	ldxa	[%g7 + %g2] ASI_PHYS_USE_EC, %g7
	add	%g2, 0x40 - 0x8 - 0x8, %g2

	/* Update queue head pointer.  */
	sethi	%hi(8192 - 1), %g4
	or	%g4, %lo(8192 - 1), %g4
	and	%g2, %g4, %g2

	mov	INTRQ_CPU_MONDO_HEAD, %g4
	stxa	%g2, [%g4] ASI_QUEUE
	membar	#Sync

	jmpl	%g3, %g0
	 nop

sun4v_cpu_mondo_queue_empty:
	retry

sun4v_dev_mondo:
	/* Head offset in %g2, tail offset in %g4.  */
	mov	INTRQ_DEVICE_MONDO_HEAD, %g2
	ldxa	[%g2] ASI_QUEUE, %g2
	mov	INTRQ_DEVICE_MONDO_TAIL, %g4
	ldxa	[%g4] ASI_QUEUE, %g4
	cmp	%g2, %g4
	be,pn	%xcc, sun4v_dev_mondo_queue_empty
	 nop

	/* Get &trap_block[smp_processor_id()] into %g3.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g3
	sub	%g3, TRAP_PER_CPU_FAULT_INFO, %g3

	/* Get DEV mondo queue base phys address into %g5.  */
	ldx	[%g3 + TRAP_PER_CPU_DEV_MONDO_PA], %g5

	/* Load IVEC into %g3.  */
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	add	%g2, 0x40, %g2

	/* XXX There can be a full 64-byte block of data here.
	 * XXX This is how we can get at MSI vector data.
	 * XXX Current we do not capture this, but when we do we'll
	 * XXX need to add a 64-byte storage area in the struct ino_bucket
	 * XXX or the struct irq_desc.
	 */

	/* Update queue head pointer, this frees up some registers.  */
	sethi	%hi(8192 - 1), %g4
	or	%g4, %lo(8192 - 1), %g4
	and	%g2, %g4, %g2

	mov	INTRQ_DEVICE_MONDO_HEAD, %g4
	stxa	%g2, [%g4] ASI_QUEUE
	membar	#Sync

	/* Get &__irq_work[smp_processor_id()] into %g1.  */
	TRAP_LOAD_IRQ_WORK(%g1, %g4)

	/* Get &ivector_table[IVEC] into %g4.  */
	sethi	%hi(ivector_table), %g4
	sllx	%g3, 5, %g3
	or	%g4, %lo(ivector_table), %g4
	add	%g4, %g3, %g4

	/* Load IRQ %pil into %g5.  */
	ldub	[%g4 + 0x04], %g5

	/* Insert ivector_table[] entry into __irq_work[] queue.  */
	sllx	%g5, 2, %g3
	lduw	[%g1 + %g3], %g2	/* g2 = irq_work(cpu, pil) */
	stw	%g2, [%g4 + 0x00]	/* bucket->irq_chain = g2 */
	stw	%g4, [%g1 + %g3]	/* irq_work(cpu, pil) = bucket */

	/* Signal the interrupt by setting (1 << pil) in %softint.  */
	mov	1, %g2
	sllx	%g2, %g5, %g2
	wr	%g2, 0x0, %set_softint

sun4v_dev_mondo_queue_empty:
	retry

sun4v_res_mondo:
	/* Head offset in %g2, tail offset in %g4.  */
	mov	INTRQ_RESUM_MONDO_HEAD, %g2
	ldxa	[%g2] ASI_QUEUE, %g2
	mov	INTRQ_RESUM_MONDO_TAIL, %g4
	ldxa	[%g4] ASI_QUEUE, %g4
	cmp	%g2, %g4
	be,pn	%xcc, sun4v_res_mondo_queue_empty
	 nop

	/* Get &trap_block[smp_processor_id()] into %g3.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g3
	sub	%g3, TRAP_PER_CPU_FAULT_INFO, %g3

	/* Get RES mondo queue base phys address into %g5.  */
	ldx	[%g3 + TRAP_PER_CPU_RESUM_MONDO_PA], %g5

	/* Get RES kernel buffer base phys address into %g7.  */
	ldx	[%g3 + TRAP_PER_CPU_RESUM_KBUF_PA], %g7

	/* If the first word is non-zero, queue is full.  */
	ldxa	[%g7 + %g2] ASI_PHYS_USE_EC, %g1
	brnz,pn	%g1, sun4v_res_mondo_queue_full
	 nop

	/* Remember this entry's offset in %g1.  */
	mov	%g2, %g1

	/* Copy 64-byte queue entry into kernel buffer.  */
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2

	/* Update queue head pointer.  */
	sethi	%hi(8192 - 1), %g4
	or	%g4, %lo(8192 - 1), %g4
	and	%g2, %g4, %g2

	mov	INTRQ_RESUM_MONDO_HEAD, %g4
	stxa	%g2, [%g4] ASI_QUEUE
	membar	#Sync

	/* Disable interrupts and save register state so we can call
	 * C code.  The etrap handling will leave %g4 in %l4 for us
	 * when it's done.
	 */
	rdpr	%pil, %g2
	wrpr	%g0, 15, %pil
	mov	%g1, %g4
	ba,pt	%xcc, etrap_irq
	 rd	%pc, %g7

	/* Log the event.  */
	add	%sp, PTREGS_OFF, %o0
	call	sun4v_resum_error
	 mov	%l4, %o1

	/* Return from trap.  */
	ba,pt	%xcc, rtrap_irq
	 nop

sun4v_res_mondo_queue_empty:
	retry

sun4v_res_mondo_queue_full:
	/* The queue is full, consolidate our damage by setting
	 * the head equal to the tail.  We'll just trap again otherwise.
	 * Call C code to log the event.
	 */
	mov	INTRQ_RESUM_MONDO_HEAD, %g2
	stxa	%g4, [%g2] ASI_QUEUE
	membar	#Sync

	rdpr	%pil, %g2
	wrpr	%g0, 15, %pil
	ba,pt	%xcc, etrap_irq
	 rd	%pc, %g7

	call	sun4v_resum_overflow
	 add	%sp, PTREGS_OFF, %o0

	ba,pt	%xcc, rtrap_irq
	 nop

sun4v_nonres_mondo:
	/* Head offset in %g2, tail offset in %g4.  */
	mov	INTRQ_NONRESUM_MONDO_HEAD, %g2
	ldxa	[%g2] ASI_QUEUE, %g2
	mov	INTRQ_NONRESUM_MONDO_TAIL, %g4
	ldxa	[%g4] ASI_QUEUE, %g4
	cmp	%g2, %g4
	be,pn	%xcc, sun4v_nonres_mondo_queue_empty
	 nop

	/* Get &trap_block[smp_processor_id()] into %g3.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g3
	sub	%g3, TRAP_PER_CPU_FAULT_INFO, %g3

	/* Get RES mondo queue base phys address into %g5.  */
	ldx	[%g3 + TRAP_PER_CPU_NONRESUM_MONDO_PA], %g5

	/* Get RES kernel buffer base phys address into %g7.  */
	ldx	[%g3 + TRAP_PER_CPU_NONRESUM_KBUF_PA], %g7

	/* If the first word is non-zero, queue is full.  */
	ldxa	[%g7 + %g2] ASI_PHYS_USE_EC, %g1
	brnz,pn	%g1, sun4v_nonres_mondo_queue_full
	 nop

	/* Remember this entry's offset in %g1.  */
	mov	%g2, %g1

	/* Copy 64-byte queue entry into kernel buffer.  */
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2
	ldxa	[%g5 + %g2] ASI_PHYS_USE_EC, %g3
	stxa	%g3, [%g7 + %g2] ASI_PHYS_USE_EC
	add	%g2, 0x08, %g2

	/* Update queue head pointer.  */
	sethi	%hi(8192 - 1), %g4
	or	%g4, %lo(8192 - 1), %g4
	and	%g2, %g4, %g2

	mov	INTRQ_NONRESUM_MONDO_HEAD, %g4
	stxa	%g2, [%g4] ASI_QUEUE
	membar	#Sync

	/* Disable interrupts and save register state so we can call
	 * C code.  The etrap handling will leave %g4 in %l4 for us
	 * when it's done.
	 */
	rdpr	%pil, %g2
	wrpr	%g0, 15, %pil
	mov	%g1, %g4
	ba,pt	%xcc, etrap_irq
	 rd	%pc, %g7

	/* Log the event.  */
	add	%sp, PTREGS_OFF, %o0
	call	sun4v_nonresum_error
	 mov	%l4, %o1

	/* Return from trap.  */
	ba,pt	%xcc, rtrap_irq
	 nop

sun4v_nonres_mondo_queue_empty:
	retry

sun4v_nonres_mondo_queue_full:
	/* The queue is full, consolidate our damage by setting
	 * the head equal to the tail.  We'll just trap again otherwise.
	 * Call C code to log the event.
	 */
	mov	INTRQ_NONRESUM_MONDO_HEAD, %g2
	stxa	%g4, [%g2] ASI_QUEUE
	membar	#Sync

	rdpr	%pil, %g2
	wrpr	%g0, 15, %pil
	ba,pt	%xcc, etrap_irq
	 rd	%pc, %g7

	call	sun4v_nonresum_overflow
	 add	%sp, PTREGS_OFF, %o0

	ba,pt	%xcc, rtrap_irq
	 nop
Commit	Line	Data
5b0c0572 DM	1	/* sun4v_ivec.S: Sun4v interrupt vector handling.
	2	*
	3	* Copyright (C) 2006 <davem@davemloft.net>
	4	*/
	5
	6	#include <asm/cpudata.h>
	7	#include <asm/intr_queue.h>
	8
	9	.text
	10	.align 32
	11
	12	sun4v_cpu_mondo:
	13	/* Head offset in %g2, tail offset in %g4.
	14	* If they are the same, no work.
	15	*/
	16	mov INTRQ_CPU_MONDO_HEAD, %g2
	17	ldxa [%g2] ASI_QUEUE, %g2
	18	mov INTRQ_CPU_MONDO_TAIL, %g4
	19	ldxa [%g4] ASI_QUEUE, %g4
	20	cmp %g2, %g4
	21	be,pn %xcc, sun4v_cpu_mondo_queue_empty
	22	nop
	23
	24	/* Get &trap_block[smp_processor_id()] into %g3. */
12eaa328 DM	25	ldxa [%g0] ASI_SCRATCHPAD, %g3
12eaa328 DM	26	sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
5b0c0572 DM	27
	28	/* Get CPU mondo queue base phys address into %g7. */
	29	ldx [%g3 + TRAP_PER_CPU_CPU_MONDO_PA], %g7
	30
	31	/* Now get the cross-call arguments and handler PC, same
	32	* layout as sun4u:
	33	*
	34	* 1st 64-bit word: low half is 32-bit PC, put into %g3 and jmpl to it
	35	* high half is context arg to MMU flushes, into %g5
	36	* 2nd 64-bit word: 64-bit arg, load into %g1
	37	* 3rd 64-bit word: 64-bit arg, load into %g7
	38	*/
	39	ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g3
	40	add %g2, 0x8, %g2
	41	srlx %g3, 32, %g5
	42	ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
	43	add %g2, 0x8, %g2
	44	srl %g3, 0, %g3
	45	ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g7
	46	add %g2, 0x40 - 0x8 - 0x8, %g2
	47
	48	/* Update queue head pointer. */
	49	sethi %hi(8192 - 1), %g4
	50	or %g4, %lo(8192 - 1), %g4
	51	and %g2, %g4, %g2
	52
	53	mov INTRQ_CPU_MONDO_HEAD, %g4
	54	stxa %g2, [%g4] ASI_QUEUE
	55	membar #Sync
	56
	57	jmpl %g3, %g0
	58	nop
	59
	60	sun4v_cpu_mondo_queue_empty:
	61	retry
	62
	63	sun4v_dev_mondo:
	64	/* Head offset in %g2, tail offset in %g4. */
	65	mov INTRQ_DEVICE_MONDO_HEAD, %g2
	66	ldxa [%g2] ASI_QUEUE, %g2
	67	mov INTRQ_DEVICE_MONDO_TAIL, %g4
	68	ldxa [%g4] ASI_QUEUE, %g4
	69	cmp %g2, %g4
	70	be,pn %xcc, sun4v_dev_mondo_queue_empty
	71	nop
	72
	73	/* Get &trap_block[smp_processor_id()] into %g3. */
12eaa328 DM	74	ldxa [%g0] ASI_SCRATCHPAD, %g3
12eaa328 DM	75	sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
5b0c0572 DM	76
	77	/* Get DEV mondo queue base phys address into %g5. */
	78	ldx [%g3 + TRAP_PER_CPU_DEV_MONDO_PA], %g5
	79
	80	/* Load IVEC into %g3. */
	81	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	82	add %g2, 0x40, %g2
	83
	84	/* XXX There can be a full 64-byte block of data here.
	85	* XXX This is how we can get at MSI vector data.
	86	* XXX Current we do not capture this, but when we do we'll
	87	* XXX need to add a 64-byte storage area in the struct ino_bucket
	88	* XXX or the struct irq_desc.
	89	*/
	90
	91	/* Update queue head pointer, this frees up some registers. */
	92	sethi %hi(8192 - 1), %g4
	93	or %g4, %lo(8192 - 1), %g4
	94	and %g2, %g4, %g2
	95
	96	mov INTRQ_DEVICE_MONDO_HEAD, %g4
	97	stxa %g2, [%g4] ASI_QUEUE
	98	membar #Sync
	99
	100	/* Get &__irq_work[smp_processor_id()] into %g1. */
a615fea4	101	TRAP_LOAD_IRQ_WORK(%g1, %g4)
5b0c0572 DM	102
	103	/* Get &ivector_table[IVEC] into %g4. */
	104	sethi %hi(ivector_table), %g4
	105	sllx %g3, 5, %g3
	106	or %g4, %lo(ivector_table), %g4
	107	add %g4, %g3, %g4
	108
	109	/* Load IRQ %pil into %g5. */
	110	ldub [%g4 + 0x04], %g5
	111
	112	/* Insert ivector_table[] entry into __irq_work[] queue. */
	113	sllx %g5, 2, %g3
	114	lduw [%g1 + %g3], %g2 /* g2 = irq_work(cpu, pil) */
	115	stw %g2, [%g4 + 0x00] /* bucket->irq_chain = g2 */
	116	stw %g4, [%g1 + %g3] /* irq_work(cpu, pil) = bucket */
	117
	118	/* Signal the interrupt by setting (1 << pil) in %softint. */
	119	mov 1, %g2
	120	sllx %g2, %g5, %g2
	121	wr %g2, 0x0, %set_softint
	122
	123	sun4v_dev_mondo_queue_empty:
	124	retry
	125
	126	sun4v_res_mondo:
	127	/* Head offset in %g2, tail offset in %g4. */
	128	mov INTRQ_RESUM_MONDO_HEAD, %g2
	129	ldxa [%g2] ASI_QUEUE, %g2
	130	mov INTRQ_RESUM_MONDO_TAIL, %g4
	131	ldxa [%g4] ASI_QUEUE, %g4
	132	cmp %g2, %g4
	133	be,pn %xcc, sun4v_res_mondo_queue_empty
	134	nop
	135
	136	/* Get &trap_block[smp_processor_id()] into %g3. */
12eaa328 DM	137	ldxa [%g0] ASI_SCRATCHPAD, %g3
12eaa328 DM	138	sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
5b0c0572 DM	139
	140	/* Get RES mondo queue base phys address into %g5. */
	141	ldx [%g3 + TRAP_PER_CPU_RESUM_MONDO_PA], %g5
	142
	143	/* Get RES kernel buffer base phys address into %g7. */
	144	ldx [%g3 + TRAP_PER_CPU_RESUM_KBUF_PA], %g7
	145
	146	/* If the first word is non-zero, queue is full. */
	147	ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
	148	brnz,pn %g1, sun4v_res_mondo_queue_full
	149	nop
	150
	151	/* Remember this entry's offset in %g1. */
	152	mov %g2, %g1
	153
	154	/* Copy 64-byte queue entry into kernel buffer. */
	155	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	156	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	157	add %g2, 0x08, %g2
	158	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	159	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	160	add %g2, 0x08, %g2
	161	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	162	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	163	add %g2, 0x08, %g2
	164	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	165	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	166	add %g2, 0x08, %g2
	167	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	168	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	169	add %g2, 0x08, %g2
	170	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	171	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	172	add %g2, 0x08, %g2
	173	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	174	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	175	add %g2, 0x08, %g2
	176	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	177	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	178	add %g2, 0x08, %g2
	179
	180	/* Update queue head pointer. */
	181	sethi %hi(8192 - 1), %g4
	182	or %g4, %lo(8192 - 1), %g4
	183	and %g2, %g4, %g2
	184
	185	mov INTRQ_RESUM_MONDO_HEAD, %g4
	186	stxa %g2, [%g4] ASI_QUEUE
	187	membar #Sync
	188
	189	/* Disable interrupts and save register state so we can call
	190	* C code. The etrap handling will leave %g4 in %l4 for us
	191	* when it's done.
	192	*/
	193	rdpr %pil, %g2
	194	wrpr %g0, 15, %pil
	195	mov %g1, %g4
	196	ba,pt %xcc, etrap_irq
	197	rd %pc, %g7
	198
	199	/* Log the event. */
	200	add %sp, PTREGS_OFF, %o0
	201	call sun4v_resum_error
	202	mov %l4, %o1
203
204	/* Return from trap. */
205	ba,pt %xcc, rtrap_irq
206	nop
207
208	sun4v_res_mondo_queue_empty:
209	retry
210
211	sun4v_res_mondo_queue_full:
212	/* The queue is full, consolidate our damage by setting
213	* the head equal to the tail. We'll just trap again otherwise.
214	* Call C code to log the event.
215	*/
216	mov INTRQ_RESUM_MONDO_HEAD, %g2
217	stxa %g4, [%g2] ASI_QUEUE
218	membar #Sync
219
220	rdpr %pil, %g2
221	wrpr %g0, 15, %pil
222	ba,pt %xcc, etrap_irq
223	rd %pc, %g7
224
225	call sun4v_resum_overflow
226	add %sp, PTREGS_OFF, %o0
227
228	ba,pt %xcc, rtrap_irq
229	nop
230
231	sun4v_nonres_mondo:
232	/* Head offset in %g2, tail offset in %g4. */
233	mov INTRQ_NONRESUM_MONDO_HEAD, %g2
234	ldxa [%g2] ASI_QUEUE, %g2
235	mov INTRQ_NONRESUM_MONDO_TAIL, %g4
236	ldxa [%g4] ASI_QUEUE, %g4
237	cmp %g2, %g4
238	be,pn %xcc, sun4v_nonres_mondo_queue_empty
239	nop
240
241	/* Get &trap_block[smp_processor_id()] into %g3. */
12eaa328 DM	242	ldxa [%g0] ASI_SCRATCHPAD, %g3
12eaa328 DM	243	sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
5b0c0572 DM	244
	245	/* Get RES mondo queue base phys address into %g5. */
	246	ldx [%g3 + TRAP_PER_CPU_NONRESUM_MONDO_PA], %g5
	247
	248	/* Get RES kernel buffer base phys address into %g7. */
	249	ldx [%g3 + TRAP_PER_CPU_NONRESUM_KBUF_PA], %g7
	250
	251	/* If the first word is non-zero, queue is full. */
	252	ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
	253	brnz,pn %g1, sun4v_nonres_mondo_queue_full
	254	nop
	255
	256	/* Remember this entry's offset in %g1. */
	257	mov %g2, %g1
	258
	259	/* Copy 64-byte queue entry into kernel buffer. */
	260	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	261	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	262	add %g2, 0x08, %g2
	263	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	264	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	265	add %g2, 0x08, %g2
	266	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	267	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	268	add %g2, 0x08, %g2
	269	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	270	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	271	add %g2, 0x08, %g2
	272	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	273	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	274	add %g2, 0x08, %g2
	275	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	276	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	277	add %g2, 0x08, %g2
	278	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	279	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	280	add %g2, 0x08, %g2
	281	ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
	282	stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
	283	add %g2, 0x08, %g2
	284
	285	/* Update queue head pointer. */
	286	sethi %hi(8192 - 1), %g4
	287	or %g4, %lo(8192 - 1), %g4
	288	and %g2, %g4, %g2
	289
	290	mov INTRQ_NONRESUM_MONDO_HEAD, %g4
	291	stxa %g2, [%g4] ASI_QUEUE
	292	membar #Sync
	293
	294	/* Disable interrupts and save register state so we can call
	295	* C code. The etrap handling will leave %g4 in %l4 for us
	296	* when it's done.
	297	*/
	298	rdpr %pil, %g2
	299	wrpr %g0, 15, %pil
	300	mov %g1, %g4
	301	ba,pt %xcc, etrap_irq
	302	rd %pc, %g7
	303
	304	/* Log the event. */
	305	add %sp, PTREGS_OFF, %o0
	306	call sun4v_nonresum_error
	307	mov %l4, %o1
308
309	/* Return from trap. */
310	ba,pt %xcc, rtrap_irq
311	nop
312
313	sun4v_nonres_mondo_queue_empty:
314	retry
315
316	sun4v_nonres_mondo_queue_full:
317	/* The queue is full, consolidate our damage by setting
318	* the head equal to the tail. We'll just trap again otherwise.
319	* Call C code to log the event.
320	*/
321	mov INTRQ_NONRESUM_MONDO_HEAD, %g2
322	stxa %g4, [%g2] ASI_QUEUE
323	membar #Sync
324
325	rdpr %pil, %g2
326	wrpr %g0, 15, %pil
327	ba,pt %xcc, etrap_irq
328	rd %pc, %g7
329
330	call sun4v_nonresum_overflow
331	add %sp, PTREGS_OFF, %o0
332
333	ba,pt %xcc, rtrap_irq
334	nop