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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * SPARC64 Huge TLB page support. | |
3 | * | |
4 | * Copyright (C) 2002, 2003 David S. Miller (davem@redhat.com) | |
5 | */ | |
6 | ||
7 | #include <linux/config.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/fs.h> | |
11 | #include <linux/mm.h> | |
12 | #include <linux/hugetlb.h> | |
13 | #include <linux/pagemap.h> | |
14 | #include <linux/smp_lock.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/sysctl.h> | |
17 | ||
18 | #include <asm/mman.h> | |
19 | #include <asm/pgalloc.h> | |
20 | #include <asm/tlb.h> | |
21 | #include <asm/tlbflush.h> | |
22 | #include <asm/cacheflush.h> | |
23 | #include <asm/mmu_context.h> | |
24 | ||
63551ae0 | 25 | pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr) |
1da177e4 LT |
26 | { |
27 | pgd_t *pgd; | |
28 | pud_t *pud; | |
29 | pmd_t *pmd; | |
30 | pte_t *pte = NULL; | |
31 | ||
32 | pgd = pgd_offset(mm, addr); | |
33 | if (pgd) { | |
34 | pud = pud_offset(pgd, addr); | |
35 | if (pud) { | |
36 | pmd = pmd_alloc(mm, pud, addr); | |
37 | if (pmd) | |
38 | pte = pte_alloc_map(mm, pmd, addr); | |
39 | } | |
40 | } | |
41 | return pte; | |
42 | } | |
43 | ||
63551ae0 | 44 | pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr) |
1da177e4 LT |
45 | { |
46 | pgd_t *pgd; | |
47 | pud_t *pud; | |
48 | pmd_t *pmd; | |
49 | pte_t *pte = NULL; | |
50 | ||
51 | pgd = pgd_offset(mm, addr); | |
52 | if (pgd) { | |
53 | pud = pud_offset(pgd, addr); | |
54 | if (pud) { | |
55 | pmd = pmd_offset(pud, addr); | |
56 | if (pmd) | |
57 | pte = pte_offset_map(pmd, addr); | |
58 | } | |
59 | } | |
60 | return pte; | |
61 | } | |
62 | ||
63 | #define mk_pte_huge(entry) do { pte_val(entry) |= _PAGE_SZHUGE; } while (0) | |
64 | ||
63551ae0 DG |
65 | void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, |
66 | pte_t *ptep, pte_t entry) | |
1da177e4 | 67 | { |
63551ae0 DG |
68 | int i; |
69 | ||
70 | for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) { | |
71 | set_pte_at(mm, addr, ptep, entry); | |
72 | ptep++; | |
73 | addr += PAGE_SIZE; | |
74 | pte_val(entry) += PAGE_SIZE; | |
75 | } | |
76 | } | |
1da177e4 | 77 | |
63551ae0 DG |
78 | pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, |
79 | pte_t *ptep) | |
80 | { | |
81 | pte_t entry; | |
82 | int i; | |
1da177e4 | 83 | |
63551ae0 | 84 | entry = *ptep; |
1da177e4 LT |
85 | |
86 | for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) { | |
63551ae0 | 87 | pte_clear(mm, addr, ptep); |
1da177e4 | 88 | addr += PAGE_SIZE; |
63551ae0 | 89 | ptep++; |
1da177e4 | 90 | } |
63551ae0 DG |
91 | |
92 | return entry; | |
1da177e4 LT |
93 | } |
94 | ||
95 | /* | |
96 | * This function checks for proper alignment of input addr and len parameters. | |
97 | */ | |
98 | int is_aligned_hugepage_range(unsigned long addr, unsigned long len) | |
99 | { | |
100 | if (len & ~HPAGE_MASK) | |
101 | return -EINVAL; | |
102 | if (addr & ~HPAGE_MASK) | |
103 | return -EINVAL; | |
104 | return 0; | |
105 | } | |
106 | ||
1da177e4 LT |
107 | struct page *follow_huge_addr(struct mm_struct *mm, |
108 | unsigned long address, int write) | |
109 | { | |
110 | return ERR_PTR(-EINVAL); | |
111 | } | |
112 | ||
113 | int pmd_huge(pmd_t pmd) | |
114 | { | |
115 | return 0; | |
116 | } | |
117 | ||
118 | struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address, | |
119 | pmd_t *pmd, int write) | |
120 | { | |
121 | return NULL; | |
122 | } | |
123 | ||
1da177e4 LT |
124 | static void context_reload(void *__data) |
125 | { | |
126 | struct mm_struct *mm = __data; | |
127 | ||
128 | if (mm == current->mm) | |
129 | load_secondary_context(mm); | |
130 | } | |
131 | ||
63551ae0 | 132 | void hugetlb_prefault_arch_hook(struct mm_struct *mm) |
1da177e4 | 133 | { |
1da177e4 LT |
134 | /* On UltraSPARC-III+ and later, configure the second half of |
135 | * the Data-TLB for huge pages. | |
136 | */ | |
137 | if (tlb_type == cheetah_plus) { | |
138 | unsigned long ctx; | |
139 | ||
140 | spin_lock(&ctx_alloc_lock); | |
141 | ctx = mm->context.sparc64_ctx_val; | |
142 | ctx &= ~CTX_PGSZ_MASK; | |
143 | ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; | |
144 | ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; | |
145 | ||
146 | if (ctx != mm->context.sparc64_ctx_val) { | |
147 | /* When changing the page size fields, we | |
148 | * must perform a context flush so that no | |
149 | * stale entries match. This flush must | |
150 | * occur with the original context register | |
151 | * settings. | |
152 | */ | |
153 | do_flush_tlb_mm(mm); | |
154 | ||
155 | /* Reload the context register of all processors | |
156 | * also executing in this address space. | |
157 | */ | |
158 | mm->context.sparc64_ctx_val = ctx; | |
159 | on_each_cpu(context_reload, mm, 0, 0); | |
160 | } | |
161 | spin_unlock(&ctx_alloc_lock); | |
162 | } | |
1da177e4 | 163 | } |