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[PATCH] remove set_page_count() outside mm/
[mirror_ubuntu-bionic-kernel.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
c4bce90e 9#include <linux/module.h>
1da177e4
LT		 10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/slab.h>
18#include <linux/initrd.h>
19#include <linux/swap.h>
20#include <linux/pagemap.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
1da177e4
LT		 26
27#include <asm/head.h>
28#include <asm/system.h>
29#include <asm/page.h>
30#include <asm/pgalloc.h>
31#include <asm/pgtable.h>
32#include <asm/oplib.h>
33#include <asm/iommu.h>
34#include <asm/io.h>
35#include <asm/uaccess.h>
36#include <asm/mmu_context.h>
37#include <asm/tlbflush.h>
38#include <asm/dma.h>
39#include <asm/starfire.h>
40#include <asm/tlb.h>
41#include <asm/spitfire.h>
42#include <asm/sections.h>
517af332 43#include <asm/tsb.h>
481295f9 44#include <asm/hypervisor.h>
1da177e4
LT		 45
46extern void device_scan(void);
47
9cc3a1ac
DM		 48#define MAX_PHYS_ADDRESS (1UL << 42UL)
49#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50#define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
52
53unsigned long kern_linear_pte_xor[2] __read_mostly;
54
55/* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
58 */
59unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
60
d7744a09
DM		 61/* A special kernel TSB for 4MB and 256MB linear mappings. */
62struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
63
13edad7a
DM		 64#define MAX_BANKS 32
65
66static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
67static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
68static int pavail_ents __initdata;
69static int pavail_rescan_ents __initdata;
70
71static int cmp_p64(const void *a, const void *b)
72{
73 const struct linux_prom64_registers *x = a, *y = b;
74
75 if (x->phys_addr > y->phys_addr)
76 return 1;
77 if (x->phys_addr < y->phys_addr)
78 return -1;
79 return 0;
80}
81
82static void __init read_obp_memory(const char *property,
83 struct linux_prom64_registers *regs,
84 int *num_ents)
85{
86 int node = prom_finddevice("/memory");
87 int prop_size = prom_getproplen(node, property);
88 int ents, ret, i;
89
90 ents = prop_size / sizeof(struct linux_prom64_registers);
91 if (ents > MAX_BANKS) {
92 prom_printf("The machine has more %s property entries than "
93 "this kernel can support (%d).\n",
94 property, MAX_BANKS);
95 prom_halt();
96 }
97
98 ret = prom_getproperty(node, property, (char *) regs, prop_size);
99 if (ret == -1) {
100 prom_printf("Couldn't get %s property from /memory.\n");
101 prom_halt();
102 }
103
104 *num_ents = ents;
10147570 105
13edad7a
DM		 106 /* Sanitize what we got from the firmware, by page aligning
107 * everything.
108 */
109 for (i = 0; i < ents; i++) {
110 unsigned long base, size;
111
112 base = regs[i].phys_addr;
113 size = regs[i].reg_size;
10147570 114
13edad7a
DM		 115 size &= PAGE_MASK;
116 if (base & ~PAGE_MASK) {
117 unsigned long new_base = PAGE_ALIGN(base);
118
119 size -= new_base - base;
120 if ((long) size < 0L)
121 size = 0UL;
122 base = new_base;
123 }
124 regs[i].phys_addr = base;
125 regs[i].reg_size = size;
126 }
c9c10830 127 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 128 cmp_p64, NULL);
129}
1da177e4 130
2bdb3cb2 131unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4 132
d1112018 133/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 134unsigned long kern_base __read_mostly;
135unsigned long kern_size __read_mostly;
1da177e4 136
1da177e4
LT		 137/* get_new_mmu_context() uses "cache + 1". */
138DEFINE_SPINLOCK(ctx_alloc_lock);
139unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
140#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
141unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
142
143/* References to special section boundaries */
144extern char _start[], _end[];
145
146/* Initial ramdisk setup */
147extern unsigned long sparc_ramdisk_image64;
148extern unsigned int sparc_ramdisk_image;
149extern unsigned int sparc_ramdisk_size;
150
1ac4f5eb 151struct page *mem_map_zero __read_mostly;
1da177e4 152
0835ae0f
DM		 153unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
154
155unsigned long sparc64_kern_pri_context __read_mostly;
156unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
157unsigned long sparc64_kern_sec_context __read_mostly;
158
1da177e4
LT		 159int bigkernel = 0;
160
3c936465 161kmem_cache_t *pgtable_cache __read_mostly;
1da177e4 162
3c936465
DM		 163static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
164{
165 clear_page(addr);
166}
05e28f9d 167
9b4006dc
DM		 168extern void tsb_cache_init(void);
169
3c936465 170void pgtable_cache_init(void)
1da177e4 171{
3c936465
DM		 172 pgtable_cache = kmem_cache_create("pgtable_cache",
173 PAGE_SIZE, PAGE_SIZE,
174 SLAB_HWCACHE_ALIGN |
175 SLAB_MUST_HWCACHE_ALIGN,
176 zero_ctor,
177 NULL);
178 if (!pgtable_cache) {
9b4006dc 179 prom_printf("Could not create pgtable_cache\n");
3c936465 180 prom_halt();
1da177e4 181 }
9b4006dc 182 tsb_cache_init();
1da177e4
LT		 183}
184
185#ifdef CONFIG_DEBUG_DCFLUSH
186atomic_t dcpage_flushes = ATOMIC_INIT(0);
187#ifdef CONFIG_SMP
188atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
189#endif
190#endif
191
7a591cfe 192inline void flush_dcache_page_impl(struct page *page)
1da177e4 193{
7a591cfe 194 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 195#ifdef CONFIG_DEBUG_DCFLUSH
196 atomic_inc(&dcpage_flushes);
197#endif
198
199#ifdef DCACHE_ALIASING_POSSIBLE
200 __flush_dcache_page(page_address(page),
201 ((tlb_type == spitfire) &&
202 page_mapping(page) != NULL));
203#else
204 if (page_mapping(page) != NULL &&
205 tlb_type == spitfire)
206 __flush_icache_page(__pa(page_address(page)));
207#endif
208}
209
210#define PG_dcache_dirty PG_arch_1
17b0e199
DM		 211#define PG_dcache_cpu_shift 24UL
212#define PG_dcache_cpu_mask (256UL - 1UL)
48b0e548
DM		 213
214#if NR_CPUS > 256
215#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
216#endif
1da177e4
LT		 217
218#define dcache_dirty_cpu(page) \
48b0e548 219 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 220
221static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
222{
223 unsigned long mask = this_cpu;
48b0e548
DM		 224 unsigned long non_cpu_bits;
225
226 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
227 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
228
1da177e4
LT		 229 __asm__ __volatile__("1:\n\t"
230 "ldx [%2], %%g7\n\t"
231 "and %%g7, %1, %%g1\n\t"
232 "or %%g1, %0, %%g1\n\t"
233 "casx [%2], %%g7, %%g1\n\t"
234 "cmp %%g7, %%g1\n\t"
b445e26c 235 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 236 "bne,pn %%xcc, 1b\n\t"
b445e26c 237 " nop"
1da177e4
LT		 238 : /* no outputs */
239 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
240 : "g1", "g7");
241}
242
243static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
244{
245 unsigned long mask = (1UL << PG_dcache_dirty);
246
247 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
248 "1:\n\t"
249 "ldx [%2], %%g7\n\t"
48b0e548 250 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 251 "and %%g1, %3, %%g1\n\t"
252 "cmp %%g1, %0\n\t"
253 "bne,pn %%icc, 2f\n\t"
254 " andn %%g7, %1, %%g1\n\t"
255 "casx [%2], %%g7, %%g1\n\t"
256 "cmp %%g7, %%g1\n\t"
b445e26c 257 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 258 "bne,pn %%xcc, 1b\n\t"
b445e26c 259 " nop\n"
1da177e4
LT		 260 "2:"
261 : /* no outputs */
262 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 263 "i" (PG_dcache_cpu_mask),
264 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 265 : "g1", "g7");
266}
267
517af332
DM		 268static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269{
270 unsigned long tsb_addr = (unsigned long) ent;
271
3b3ab2eb 272 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 273 tsb_addr = __pa(tsb_addr);
274
275 __tsb_insert(tsb_addr, tag, pte);
276}
277
c4bce90e
DM		 278unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
279unsigned long _PAGE_SZBITS __read_mostly;
280
1da177e4
LT		 281void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
282{
bd40791e 283 struct mm_struct *mm;
74ae9987 284 struct tsb *tsb;
7a1ac526 285 unsigned long tag, flags;
7a591cfe
DM		 286
287 if (tlb_type != hypervisor) {
288 unsigned long pfn = pte_pfn(pte);
289 unsigned long pg_flags;
290 struct page *page;
291
292 if (pfn_valid(pfn) &&
293 (page = pfn_to_page(pfn), page_mapping(page)) &&
294 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
295 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
296 PG_dcache_cpu_mask);
297 int this_cpu = get_cpu();
298
299 /* This is just to optimize away some function calls
300 * in the SMP case.
301 */
302 if (cpu == this_cpu)
303 flush_dcache_page_impl(page);
304 else
305 smp_flush_dcache_page_impl(page, cpu);
306
307 clear_dcache_dirty_cpu(page, cpu);
308
309 put_cpu();
310 }
1da177e4 311 }
bd40791e
DM		 312
313 mm = vma->vm_mm;
7a1ac526
DM		 314
315 spin_lock_irqsave(&mm->context.lock, flags);
316
74ae9987
DM		 317 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
318 (mm->context.tsb_nentries - 1UL)];
319 tag = (address >> 22UL);
320 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 321
322 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 323}
324
325void flush_dcache_page(struct page *page)
326{
a9546f59
DM		 327 struct address_space *mapping;
328 int this_cpu;
1da177e4 329
7a591cfe
DM		 330 if (tlb_type == hypervisor)
331 return;
332
a9546f59
DM		 333 /* Do not bother with the expensive D-cache flush if it
334 * is merely the zero page. The 'bigcore' testcase in GDB
335 * causes this case to run millions of times.
336 */
337 if (page == ZERO_PAGE(0))
338 return;
339
340 this_cpu = get_cpu();
341
342 mapping = page_mapping(page);
1da177e4 343 if (mapping && !mapping_mapped(mapping)) {
a9546f59 344 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 345 if (dirty) {
a9546f59
DM		 346 int dirty_cpu = dcache_dirty_cpu(page);
347
1da177e4
LT		 348 if (dirty_cpu == this_cpu)
349 goto out;
350 smp_flush_dcache_page_impl(page, dirty_cpu);
351 }
352 set_dcache_dirty(page, this_cpu);
353 } else {
354 /* We could delay the flush for the !page_mapping
355 * case too. But that case is for exec env/arg
356 * pages and those are %99 certainly going to get
357 * faulted into the tlb (and thus flushed) anyways.
358 */
359 flush_dcache_page_impl(page);
360 }
361
362out:
363 put_cpu();
364}
365
05e14cb3 366void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 367{
a43fe0e7 368 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 369 if (tlb_type == spitfire) {
370 unsigned long kaddr;
371
372 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
373 __flush_icache_page(__get_phys(kaddr));
374 }
375}
376
1da177e4
LT		 377void show_mem(void)
378{
379 printk("Mem-info:\n");
380 show_free_areas();
381 printk("Free swap: %6ldkB\n",
382 nr_swap_pages << (PAGE_SHIFT-10));
383 printk("%ld pages of RAM\n", num_physpages);
384 printk("%d free pages\n", nr_free_pages());
1da177e4
LT		 385}
386
387void mmu_info(struct seq_file *m)
388{
389 if (tlb_type == cheetah)
390 seq_printf(m, "MMU Type\t: Cheetah\n");
391 else if (tlb_type == cheetah_plus)
392 seq_printf(m, "MMU Type\t: Cheetah+\n");
393 else if (tlb_type == spitfire)
394 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 395 else if (tlb_type == hypervisor)
396 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 397 else
398 seq_printf(m, "MMU Type\t: ???\n");
399
400#ifdef CONFIG_DEBUG_DCFLUSH
401 seq_printf(m, "DCPageFlushes\t: %d\n",
402 atomic_read(&dcpage_flushes));
403#ifdef CONFIG_SMP
404 seq_printf(m, "DCPageFlushesXC\t: %d\n",
405 atomic_read(&dcpage_flushes_xcall));
406#endif /* CONFIG_SMP */
407#endif /* CONFIG_DEBUG_DCFLUSH */
408}
409
410struct linux_prom_translation {
411 unsigned long virt;
412 unsigned long size;
413 unsigned long data;
414};
c9c10830
DM		 415
416/* Exported for kernel TLB miss handling in ktlb.S */
417struct linux_prom_translation prom_trans[512] __read_mostly;
418unsigned int prom_trans_ents __read_mostly;
1da177e4 419
1da177e4
LT		 420/* Exported for SMP bootup purposes. */
421unsigned long kern_locked_tte_data;
422
c9c10830
DM		 423/* The obp translations are saved based on 8k pagesize, since obp can
424 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 425 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 426 */
5085b4a5
DM		 427static inline int in_obp_range(unsigned long vaddr)
428{
429 return (vaddr >= LOW_OBP_ADDRESS &&
430 vaddr < HI_OBP_ADDRESS);
431}
432
c9c10830 433static int cmp_ptrans(const void *a, const void *b)
405599bd 434{
c9c10830 435 const struct linux_prom_translation *x = a, *y = b;
405599bd 436
c9c10830
DM		 437 if (x->virt > y->virt)
438 return 1;
439 if (x->virt < y->virt)
440 return -1;
441 return 0;
405599bd
DM		 442}
443
c9c10830 444/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 445static void __init read_obp_translations(void)
405599bd 446{
c9c10830 447 int n, node, ents, first, last, i;
1da177e4
LT		 448
449 node = prom_finddevice("/virtual-memory");
450 n = prom_getproplen(node, "translations");
405599bd 451 if (unlikely(n == 0 || n == -1)) {
b206fc4c 452 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 453 prom_halt();
454 }
405599bd
DM		 455 if (unlikely(n > sizeof(prom_trans))) {
456 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 457 prom_halt();
458 }
405599bd 459
b206fc4c 460 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 461 (char *)&prom_trans[0],
462 sizeof(prom_trans))) == -1) {
b206fc4c 463 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 464 prom_halt();
465 }
9ad98c5b 466
b206fc4c 467 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 468
c9c10830
DM		 469 ents = n;
470
471 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
472 cmp_ptrans, NULL);
473
474 /* Now kick out all the non-OBP entries. */
475 for (i = 0; i < ents; i++) {
476 if (in_obp_range(prom_trans[i].virt))
477 break;
478 }
479 first = i;
480 for (; i < ents; i++) {
481 if (!in_obp_range(prom_trans[i].virt))
482 break;
483 }
484 last = i;
485
486 for (i = 0; i < (last - first); i++) {
487 struct linux_prom_translation *src = &prom_trans[i + first];
488 struct linux_prom_translation *dest = &prom_trans[i];
489
490 *dest = *src;
491 }
492 for (; i < ents; i++) {
493 struct linux_prom_translation *dest = &prom_trans[i];
494 dest->virt = dest->size = dest->data = 0x0UL;
495 }
496
497 prom_trans_ents = last - first;
498
499 if (tlb_type == spitfire) {
500 /* Clear diag TTE bits. */
501 for (i = 0; i < prom_trans_ents; i++)
502 prom_trans[i].data &= ~0x0003fe0000000000UL;
503 }
405599bd 504}
1da177e4 505
d82ace7d
DM		 506static void __init hypervisor_tlb_lock(unsigned long vaddr,
507 unsigned long pte,
508 unsigned long mmu)
509{
164c220f
DM		 510 register unsigned long func asm("%o5");
511 register unsigned long arg0 asm("%o0");
512 register unsigned long arg1 asm("%o1");
513 register unsigned long arg2 asm("%o2");
514 register unsigned long arg3 asm("%o3");
d82ace7d
DM		 515
516 func = HV_FAST_MMU_MAP_PERM_ADDR;
517 arg0 = vaddr;
518 arg1 = 0;
519 arg2 = pte;
520 arg3 = mmu;
521 __asm__ __volatile__("ta 0x80"
522 : "=&r" (func), "=&r" (arg0),
523 "=&r" (arg1), "=&r" (arg2),
524 "=&r" (arg3)
525 : "0" (func), "1" (arg0), "2" (arg1),
526 "3" (arg2), "4" (arg3));
12e126ad
DM		 527 if (arg0 != 0) {
528 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
529 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
530 prom_halt();
531 }
d82ace7d
DM		 532}
533
c4bce90e
DM		 534static unsigned long kern_large_tte(unsigned long paddr);
535
898cf0ec 536static void __init remap_kernel(void)
405599bd
DM		 537{
538 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 539 int tlb_ent = sparc64_highest_locked_tlbent();
540
1da177e4 541 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 542 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 543 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 544
545 kern_locked_tte_data = tte_data;
546
d82ace7d
DM		 547 /* Now lock us into the TLBs via Hypervisor or OBP. */
548 if (tlb_type == hypervisor) {
549 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
550 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
551 if (bigkernel) {
552 tte_vaddr += 0x400000;
553 tte_data += 0x400000;
554 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
555 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
556 }
557 } else {
558 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
559 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
560 if (bigkernel) {
561 tlb_ent -= 1;
562 prom_dtlb_load(tlb_ent,
563 tte_data + 0x400000,
564 tte_vaddr + 0x400000);
565 prom_itlb_load(tlb_ent,
566 tte_data + 0x400000,
567 tte_vaddr + 0x400000);
568 }
569 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
1da177e4 570 }
0835ae0f
DM		 571 if (tlb_type == cheetah_plus) {
572 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
573 CTX_CHEETAH_PLUS_NUC);
574 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
575 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
576 }
405599bd 577}
1da177e4 578
405599bd 579
c9c10830 580static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 581{
582 read_obp_translations();
405599bd
DM		 583
584 /* Now fixup OBP's idea about where we really are mapped. */
585 prom_printf("Remapping the kernel... ");
586 remap_kernel();
1da177e4 587 prom_printf("done.\n");
1da177e4
LT		 588}
589
1da177e4
LT		 590void prom_world(int enter)
591{
1da177e4
LT		 592 if (!enter)
593 set_fs((mm_segment_t) { get_thread_current_ds() });
594
3487d1d4 595 __asm__ __volatile__("flushw");
1da177e4
LT		 596}
597
598#ifdef DCACHE_ALIASING_POSSIBLE
599void __flush_dcache_range(unsigned long start, unsigned long end)
600{
601 unsigned long va;
602
603 if (tlb_type == spitfire) {
604 int n = 0;
605
606 for (va = start; va < end; va += 32) {
607 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
608 if (++n >= 512)
609 break;
610 }
a43fe0e7 611 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 612 start = __pa(start);
613 end = __pa(end);
614 for (va = start; va < end; va += 32)
615 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
616 "membar #Sync"
617 : /* no outputs */
618 : "r" (va),
619 "i" (ASI_DCACHE_INVALIDATE));
620 }
621}
622#endif /* DCACHE_ALIASING_POSSIBLE */
623
1da177e4
LT		 624/* Caller does TLB context flushing on local CPU if necessary.
625 * The caller also ensures that CTX_VALID(mm->context) is false.
626 *
627 * We must be careful about boundary cases so that we never
628 * let the user have CTX 0 (nucleus) or we ever use a CTX
629 * version of zero (and thus NO_CONTEXT would not be caught
630 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 631 *
632 * Always invoked with interrupts disabled.
1da177e4
LT		 633 */
634void get_new_mmu_context(struct mm_struct *mm)
635{
636 unsigned long ctx, new_ctx;
637 unsigned long orig_pgsz_bits;
a77754b4 638 unsigned long flags;
a0663a79 639 int new_version;
1da177e4 640
a77754b4 641 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 642 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
643 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
644 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 645 new_version = 0;
1da177e4
LT		 646 if (new_ctx >= (1 << CTX_NR_BITS)) {
647 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
648 if (new_ctx >= ctx) {
649 int i;
650 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
651 CTX_FIRST_VERSION;
652 if (new_ctx == 1)
653 new_ctx = CTX_FIRST_VERSION;
654
655 /* Don't call memset, for 16 entries that's just
656 * plain silly...
657 */
658 mmu_context_bmap[0] = 3;
659 mmu_context_bmap[1] = 0;
660 mmu_context_bmap[2] = 0;
661 mmu_context_bmap[3] = 0;
662 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
663 mmu_context_bmap[i + 0] = 0;
664 mmu_context_bmap[i + 1] = 0;
665 mmu_context_bmap[i + 2] = 0;
666 mmu_context_bmap[i + 3] = 0;
667 }
a0663a79 668 new_version = 1;
1da177e4
LT		 669 goto out;
670 }
671 }
672 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
673 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
674out:
675 tlb_context_cache = new_ctx;
676 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 677 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 678
679 if (unlikely(new_version))
680 smp_new_mmu_context_version();
1da177e4
LT		 681}
682
1da177e4
LT		 683void sparc_ultra_dump_itlb(void)
684{
685 int slot;
686
687 if (tlb_type == spitfire) {
688 printk ("Contents of itlb: ");
689 for (slot = 0; slot < 14; slot++) printk (" ");
690 printk ("%2x:%016lx,%016lx\n",
691 0,
692 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
693 for (slot = 1; slot < 64; slot+=3) {
694 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
695 slot,
696 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
697 slot+1,
698 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
699 slot+2,
700 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
701 }
702 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
703 printk ("Contents of itlb0:\n");
704 for (slot = 0; slot < 16; slot+=2) {
705 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
706 slot,
707 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
708 slot+1,
709 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
710 }
711 printk ("Contents of itlb2:\n");
712 for (slot = 0; slot < 128; slot+=2) {
713 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
714 slot,
715 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
716 slot+1,
717 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
718 }
719 }
720}
721
722void sparc_ultra_dump_dtlb(void)
723{
724 int slot;
725
726 if (tlb_type == spitfire) {
727 printk ("Contents of dtlb: ");
728 for (slot = 0; slot < 14; slot++) printk (" ");
729 printk ("%2x:%016lx,%016lx\n", 0,
730 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
731 for (slot = 1; slot < 64; slot+=3) {
732 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
733 slot,
734 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
735 slot+1,
736 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
737 slot+2,
738 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
739 }
740 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
741 printk ("Contents of dtlb0:\n");
742 for (slot = 0; slot < 16; slot+=2) {
743 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
744 slot,
745 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
746 slot+1,
747 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
748 }
749 printk ("Contents of dtlb2:\n");
750 for (slot = 0; slot < 512; slot+=2) {
751 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
752 slot,
753 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
754 slot+1,
755 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
756 }
757 if (tlb_type == cheetah_plus) {
758 printk ("Contents of dtlb3:\n");
759 for (slot = 0; slot < 512; slot+=2) {
760 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
761 slot,
762 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
763 slot+1,
764 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
765 }
766 }
767 }
768}
769
770extern unsigned long cmdline_memory_size;
771
d1112018
DM		 772/* Find a free area for the bootmem map, avoiding the kernel image
773 * and the initial ramdisk.
774 */
775static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
776 unsigned long end_pfn)
1da177e4 777{
d1112018
DM		 778 unsigned long avoid_start, avoid_end, bootmap_size;
779 int i;
780
781 bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
782 bootmap_size = ALIGN(bootmap_size, sizeof(long));
783
784 avoid_start = avoid_end = 0;
785#ifdef CONFIG_BLK_DEV_INITRD
786 avoid_start = initrd_start;
787 avoid_end = PAGE_ALIGN(initrd_end);
788#endif
789
790#ifdef CONFIG_DEBUG_BOOTMEM
791 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
792 kern_base, PAGE_ALIGN(kern_base + kern_size),
793 avoid_start, avoid_end);
794#endif
795 for (i = 0; i < pavail_ents; i++) {
796 unsigned long start, end;
797
798 start = pavail[i].phys_addr;
799 end = start + pavail[i].reg_size;
800
801 while (start < end) {
802 if (start >= kern_base &&
803 start < PAGE_ALIGN(kern_base + kern_size)) {
804 start = PAGE_ALIGN(kern_base + kern_size);
805 continue;
806 }
807 if (start >= avoid_start && start < avoid_end) {
808 start = avoid_end;
809 continue;
810 }
811
812 if ((end - start) < bootmap_size)
813 break;
814
815 if (start < kern_base &&
816 (start + bootmap_size) > kern_base) {
817 start = PAGE_ALIGN(kern_base + kern_size);
818 continue;
819 }
820
821 if (start < avoid_start &&
822 (start + bootmap_size) > avoid_start) {
823 start = avoid_end;
824 continue;
825 }
826
827 /* OK, it doesn't overlap anything, use it. */
828#ifdef CONFIG_DEBUG_BOOTMEM
829 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
830 start >> PAGE_SHIFT, start);
831#endif
832 return start >> PAGE_SHIFT;
833 }
834 }
835
836 prom_printf("Cannot find free area for bootmap, aborting.\n");
837 prom_halt();
838}
839
840static unsigned long __init bootmem_init(unsigned long *pages_avail,
841 unsigned long phys_base)
842{
843 unsigned long bootmap_size, end_pfn;
1da177e4
LT		 844 unsigned long end_of_phys_memory = 0UL;
845 unsigned long bootmap_pfn, bytes_avail, size;
846 int i;
847
848#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 849 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 850#endif
851
852 bytes_avail = 0UL;
13edad7a
DM		 853 for (i = 0; i < pavail_ents; i++) {
854 end_of_phys_memory = pavail[i].phys_addr +
855 pavail[i].reg_size;
856 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 857 if (cmdline_memory_size) {
858 if (bytes_avail > cmdline_memory_size) {
859 unsigned long slack = bytes_avail - cmdline_memory_size;
860
861 bytes_avail -= slack;
862 end_of_phys_memory -= slack;
863
13edad7a
DM		 864 pavail[i].reg_size -= slack;
865 if ((long)pavail[i].reg_size <= 0L) {
866 pavail[i].phys_addr = 0xdeadbeefUL;
867 pavail[i].reg_size = 0UL;
868 pavail_ents = i;
1da177e4 869 } else {
13edad7a
DM		 870 pavail[i+1].reg_size = 0Ul;
871 pavail[i+1].phys_addr = 0xdeadbeefUL;
872 pavail_ents = i + 1;
1da177e4
LT		 873 }
874 break;
875 }
876 }
877 }
878
879 *pages_avail = bytes_avail >> PAGE_SHIFT;
880
1da177e4
LT		 881 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
882
883#ifdef CONFIG_BLK_DEV_INITRD
884 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
885 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
886 unsigned long ramdisk_image = sparc_ramdisk_image ?
887 sparc_ramdisk_image : sparc_ramdisk_image64;
888 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
889 ramdisk_image -= KERNBASE;
890 initrd_start = ramdisk_image + phys_base;
891 initrd_end = initrd_start + sparc_ramdisk_size;
892 if (initrd_end > end_of_phys_memory) {
893 printk(KERN_CRIT "initrd extends beyond end of memory "
894 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
895 initrd_end, end_of_phys_memory);
896 initrd_start = 0;
d1112018 897 initrd_end = 0;
1da177e4
LT		 898 }
899 }
900#endif
901 /* Initialize the boot-time allocator. */
902 max_pfn = max_low_pfn = end_pfn;
d1112018
DM		 903 min_low_pfn = (phys_base >> PAGE_SHIFT);
904
905 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1da177e4
LT		 906
907#ifdef CONFIG_DEBUG_BOOTMEM
908 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
909 min_low_pfn, bootmap_pfn, max_low_pfn);
910#endif
d1112018 911 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
17b0e199 912 min_low_pfn, end_pfn);
1da177e4 913
1da177e4
LT		 914 /* Now register the available physical memory with the
915 * allocator.
916 */
13edad7a 917 for (i = 0; i < pavail_ents; i++) {
1da177e4 918#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 919 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
920 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 921#endif
13edad7a 922 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 923 }
924
925#ifdef CONFIG_BLK_DEV_INITRD
926 if (initrd_start) {
927 size = initrd_end - initrd_start;
928
929 /* Resert the initrd image area. */
930#ifdef CONFIG_DEBUG_BOOTMEM
931 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
932 initrd_start, initrd_end);
933#endif
934 reserve_bootmem(initrd_start, size);
935 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
936
937 initrd_start += PAGE_OFFSET;
938 initrd_end += PAGE_OFFSET;
939 }
940#endif
941 /* Reserve the kernel text/data/bss. */
942#ifdef CONFIG_DEBUG_BOOTMEM
943 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
944#endif
945 reserve_bootmem(kern_base, kern_size);
946 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
947
948 /* Reserve the bootmem map. We do not account for it
949 * in pages_avail because we will release that memory
950 * in free_all_bootmem.
951 */
952 size = bootmap_size;
953#ifdef CONFIG_DEBUG_BOOTMEM
954 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
955 (bootmap_pfn << PAGE_SHIFT), size);
956#endif
957 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
958 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
959
d1112018
DM		 960 for (i = 0; i < pavail_ents; i++) {
961 unsigned long start_pfn, end_pfn;
962
963 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
964 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
965#ifdef CONFIG_DEBUG_BOOTMEM
966 prom_printf("memory_present(0, %lx, %lx)\n",
967 start_pfn, end_pfn);
968#endif
969 memory_present(0, start_pfn, end_pfn);
970 }
971
972 sparse_init();
973
1da177e4
LT		 974 return end_pfn;
975}
976
9cc3a1ac
DM		 977static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
978static int pall_ents __initdata;
979
56425306
DM		 980#ifdef CONFIG_DEBUG_PAGEALLOC
981static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
982{
983 unsigned long vstart = PAGE_OFFSET + pstart;
984 unsigned long vend = PAGE_OFFSET + pend;
985 unsigned long alloc_bytes = 0UL;
986
987 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 988 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 989 vstart, vend);
990 prom_halt();
991 }
992
993 while (vstart < vend) {
994 unsigned long this_end, paddr = __pa(vstart);
995 pgd_t *pgd = pgd_offset_k(vstart);
996 pud_t *pud;
997 pmd_t *pmd;
998 pte_t *pte;
999
1000 pud = pud_offset(pgd, vstart);
1001 if (pud_none(*pud)) {
1002 pmd_t *new;
1003
1004 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1005 alloc_bytes += PAGE_SIZE;
1006 pud_populate(&init_mm, pud, new);
1007 }
1008
1009 pmd = pmd_offset(pud, vstart);
1010 if (!pmd_present(*pmd)) {
1011 pte_t *new;
1012
1013 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1014 alloc_bytes += PAGE_SIZE;
1015 pmd_populate_kernel(&init_mm, pmd, new);
1016 }
1017
1018 pte = pte_offset_kernel(pmd, vstart);
1019 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1020 if (this_end > vend)
1021 this_end = vend;
1022
1023 while (vstart < this_end) {
1024 pte_val(*pte) = (paddr | pgprot_val(prot));
1025
1026 vstart += PAGE_SIZE;
1027 paddr += PAGE_SIZE;
1028 pte++;
1029 }
1030 }
1031
1032 return alloc_bytes;
1033}
1034
56425306 1035extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1036#endif /* CONFIG_DEBUG_PAGEALLOC */
1037
1038static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1039{
1040 const unsigned long shift_256MB = 28;
1041 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1042 const unsigned long size_256MB = (1UL << shift_256MB);
1043
1044 while (start < end) {
1045 long remains;
1046
f7c00338
DM		 1047 remains = end - start;
1048 if (remains < size_256MB)
1049 break;
1050
9cc3a1ac
DM		 1051 if (start & mask_256MB) {
1052 start = (start + size_256MB) & ~mask_256MB;
1053 continue;
1054 }
1055
9cc3a1ac
DM		 1056 while (remains >= size_256MB) {
1057 unsigned long index = start >> shift_256MB;
1058
1059 __set_bit(index, kpte_linear_bitmap);
1060
1061 start += size_256MB;
1062 remains -= size_256MB;
1063 }
1064 }
1065}
56425306
DM		 1066
1067static void __init kernel_physical_mapping_init(void)
1068{
9cc3a1ac
DM		 1069 unsigned long i;
1070#ifdef CONFIG_DEBUG_PAGEALLOC
1071 unsigned long mem_alloced = 0UL;
1072#endif
56425306 1073
13edad7a
DM		 1074 read_obp_memory("reg", &pall[0], &pall_ents);
1075
1076 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1077 unsigned long phys_start, phys_end;
1078
13edad7a
DM		 1079 phys_start = pall[i].phys_addr;
1080 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1081
1082 mark_kpte_bitmap(phys_start, phys_end);
1083
1084#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1085 mem_alloced += kernel_map_range(phys_start, phys_end,
1086 PAGE_KERNEL);
9cc3a1ac 1087#endif
56425306
DM		 1088 }
1089
9cc3a1ac 1090#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1091 printk("Allocated %ld bytes for kernel page tables.\n",
1092 mem_alloced);
1093
1094 kvmap_linear_patch[0] = 0x01000000; /* nop */
1095 flushi(&kvmap_linear_patch[0]);
1096
1097 __flush_tlb_all();
9cc3a1ac 1098#endif
56425306
DM		 1099}
1100
9cc3a1ac 1101#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1102void kernel_map_pages(struct page *page, int numpages, int enable)
1103{
1104 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1105 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1106
1107 kernel_map_range(phys_start, phys_end,
1108 (enable ? PAGE_KERNEL : __pgprot(0)));
1109
74bf4312
DM		 1110 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1111 PAGE_OFFSET + phys_end);
1112
56425306
DM		 1113 /* we should perform an IPI and flush all tlbs,
1114 * but that can deadlock->flush only current cpu.
1115 */
1116 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1117 PAGE_OFFSET + phys_end);
1118}
1119#endif
1120
10147570
DM		 1121unsigned long __init find_ecache_flush_span(unsigned long size)
1122{
0836a0eb
DM		 1123 int i;
1124
13edad7a
DM		 1125 for (i = 0; i < pavail_ents; i++) {
1126 if (pavail[i].reg_size >= size)
1127 return pavail[i].phys_addr;
0836a0eb
DM		 1128 }
1129
13edad7a 1130 return ~0UL;
0836a0eb
DM		 1131}
1132
517af332
DM		 1133static void __init tsb_phys_patch(void)
1134{
d257d5da 1135 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1136 struct tsb_phys_patch_entry *p;
1137
d257d5da
DM		 1138 pquad = &__tsb_ldquad_phys_patch;
1139 while (pquad < &__tsb_ldquad_phys_patch_end) {
1140 unsigned long addr = pquad->addr;
1141
1142 if (tlb_type == hypervisor)
1143 *(unsigned int *) addr = pquad->sun4v_insn;
1144 else
1145 *(unsigned int *) addr = pquad->sun4u_insn;
1146 wmb();
1147 __asm__ __volatile__("flush %0"
1148 : /* no outputs */
1149 : "r" (addr));
1150
1151 pquad++;
1152 }
1153
517af332
DM		 1154 p = &__tsb_phys_patch;
1155 while (p < &__tsb_phys_patch_end) {
1156 unsigned long addr = p->addr;
1157
1158 *(unsigned int *) addr = p->insn;
1159 wmb();
1160 __asm__ __volatile__("flush %0"
1161 : /* no outputs */
1162 : "r" (addr));
1163
1164 p++;
1165 }
1166}
1167
490384e7
DM		 1168/* Don't mark as init, we give this to the Hypervisor. */
1169static struct hv_tsb_descr ktsb_descr[2];
1170extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1171
1172static void __init sun4v_ktsb_init(void)
1173{
1174 unsigned long ktsb_pa;
1175
d7744a09 1176 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1177 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1178
1179 switch (PAGE_SIZE) {
1180 case 8 * 1024:
1181 default:
1182 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1183 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1184 break;
1185
1186 case 64 * 1024:
1187 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1188 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1189 break;
1190
1191 case 512 * 1024:
1192 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1193 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1194 break;
1195
1196 case 4 * 1024 * 1024:
1197 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1198 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1199 break;
1200 };
1201
3f19a84e 1202 ktsb_descr[0].assoc = 1;
490384e7
DM		 1203 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1204 ktsb_descr[0].ctx_idx = 0;
1205 ktsb_descr[0].tsb_base = ktsb_pa;
1206 ktsb_descr[0].resv = 0;
1207
d7744a09
DM		 1208 /* Second KTSB for 4MB/256MB mappings. */
1209 ktsb_pa = (kern_base +
1210 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1211
1212 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1213 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1214 HV_PGSZ_MASK_256MB);
1215 ktsb_descr[1].assoc = 1;
1216 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1217 ktsb_descr[1].ctx_idx = 0;
1218 ktsb_descr[1].tsb_base = ktsb_pa;
1219 ktsb_descr[1].resv = 0;
490384e7
DM		 1220}
1221
1222void __cpuinit sun4v_ktsb_register(void)
1223{
1224 register unsigned long func asm("%o5");
1225 register unsigned long arg0 asm("%o0");
1226 register unsigned long arg1 asm("%o1");
1227 unsigned long pa;
1228
1229 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1230
1231 func = HV_FAST_MMU_TSB_CTX0;
d7744a09 1232 arg0 = 2;
490384e7
DM		 1233 arg1 = pa;
1234 __asm__ __volatile__("ta %6"
1235 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1236 : "0" (func), "1" (arg0), "2" (arg1),
1237 "i" (HV_FAST_TRAP));
1238}
1239
1da177e4
LT		 1240/* paging_init() sets up the page tables */
1241
1242extern void cheetah_ecache_flush_init(void);
d257d5da 1243extern void sun4v_patch_tlb_handlers(void);
1da177e4
LT		 1244
1245static unsigned long last_valid_pfn;
56425306 1246pgd_t swapper_pg_dir[2048];
1da177e4 1247
c4bce90e
DM		 1248static void sun4u_pgprot_init(void);
1249static void sun4v_pgprot_init(void);
1250
1da177e4
LT		 1251void __init paging_init(void)
1252{
d1112018 1253 unsigned long end_pfn, pages_avail, shift, phys_base;
0836a0eb
DM		 1254 unsigned long real_end, i;
1255
481295f9
DM		 1256 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1257 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1258
d7744a09 1259 /* Invalidate both kernel TSBs. */
8b234274 1260 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d7744a09 1261 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
8b234274 1262
c4bce90e
DM		 1263 if (tlb_type == hypervisor)
1264 sun4v_pgprot_init();
1265 else
1266 sun4u_pgprot_init();
1267
d257d5da
DM		 1268 if (tlb_type == cheetah_plus ||
1269 tlb_type == hypervisor)
517af332
DM		 1270 tsb_phys_patch();
1271
490384e7 1272 if (tlb_type == hypervisor) {
d257d5da 1273 sun4v_patch_tlb_handlers();
490384e7
DM		 1274 sun4v_ktsb_init();
1275 }
d257d5da 1276
13edad7a
DM		 1277 /* Find available physical memory... */
1278 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1279
1280 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1281 for (i = 0; i < pavail_ents; i++)
1282 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1283
1da177e4
LT		 1284 set_bit(0, mmu_context_bmap);
1285
2bdb3cb2
DM		 1286 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1287
1da177e4
LT		 1288 real_end = (unsigned long)_end;
1289 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1290 bigkernel = 1;
2bdb3cb2
DM		 1291 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1292 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1293 prom_halt();
1da177e4 1294 }
2bdb3cb2
DM		 1295
1296 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1297 * work.
1298 */
1299 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1300
56425306 1301 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1302
1303 /* Now can init the kernel/bad page tables. */
1304 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1305 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1306
c9c10830 1307 inherit_prom_mappings();
5085b4a5 1308
a8b900d8
DM		 1309 /* Ok, we can use our TLB miss and window trap handlers safely. */
1310 setup_tba();
1da177e4 1311
c9c10830 1312 __flush_tlb_all();
9ad98c5b 1313
490384e7
DM		 1314 if (tlb_type == hypervisor)
1315 sun4v_ktsb_register();
1316
2bdb3cb2
DM		 1317 /* Setup bootmem... */
1318 pages_avail = 0;
d1112018
DM		 1319 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1320
17b0e199 1321 max_mapnr = last_valid_pfn;
2bdb3cb2 1322
56425306 1323 kernel_physical_mapping_init();
56425306 1324
1da177e4
LT		 1325 {
1326 unsigned long zones_size[MAX_NR_ZONES];
1327 unsigned long zholes_size[MAX_NR_ZONES];
1da177e4
LT		 1328 int znum;
1329
1330 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1331 zones_size[znum] = zholes_size[znum] = 0;
1332
17b0e199
DM		 1333 zones_size[ZONE_DMA] = end_pfn;
1334 zholes_size[ZONE_DMA] = end_pfn - pages_avail;
1da177e4
LT		 1335
1336 free_area_init_node(0, &contig_page_data, zones_size,
17b0e199
DM		 1337 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1338 zholes_size);
1da177e4
LT		 1339 }
1340
1341 device_scan();
1342}
1343
1da177e4
LT		 1344static void __init taint_real_pages(void)
1345{
1da177e4
LT		 1346 int i;
1347
13edad7a 1348 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1349
13edad7a 1350 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1351 * reserve the lost portions in the bootmem maps.
1352 */
13edad7a 1353 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1354 unsigned long old_start, old_end;
1355
13edad7a 1356 old_start = pavail[i].phys_addr;
1da177e4 1357 old_end = old_start +
13edad7a 1358 pavail[i].reg_size;
1da177e4
LT		 1359 while (old_start < old_end) {
1360 int n;
1361
13edad7a 1362 for (n = 0; pavail_rescan_ents; n++) {
1da177e4
LT		 1363 unsigned long new_start, new_end;
1364
13edad7a
DM		 1365 new_start = pavail_rescan[n].phys_addr;
1366 new_end = new_start +
1367 pavail_rescan[n].reg_size;
1da177e4
LT		 1368
1369 if (new_start <= old_start &&
1370 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1371 set_bit(old_start >> 22,
1372 sparc64_valid_addr_bitmap);
1da177e4
LT		 1373 goto do_next_page;
1374 }
1375 }
1376 reserve_bootmem(old_start, PAGE_SIZE);
1377
1378 do_next_page:
1379 old_start += PAGE_SIZE;
1380 }
1381 }
1382}
1383
1384void __init mem_init(void)
1385{
1386 unsigned long codepages, datapages, initpages;
1387 unsigned long addr, last;
1388 int i;
1389
1390 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1391 i += 1;
2bdb3cb2 1392 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1393 if (sparc64_valid_addr_bitmap == NULL) {
1394 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1395 prom_halt();
1396 }
1397 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1398
1399 addr = PAGE_OFFSET + kern_base;
1400 last = PAGE_ALIGN(kern_size) + addr;
1401 while (addr < last) {
1402 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1403 addr += PAGE_SIZE;
1404 }
1405
1406 taint_real_pages();
1407
1da177e4
LT		 1408 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1409
1410#ifdef CONFIG_DEBUG_BOOTMEM
1411 prom_printf("mem_init: Calling free_all_bootmem().\n");
1412#endif
1413 totalram_pages = num_physpages = free_all_bootmem() - 1;
1414
1415 /*
1416 * Set up the zero page, mark it reserved, so that page count
1417 * is not manipulated when freeing the page from user ptes.
1418 */
1419 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1420 if (mem_map_zero == NULL) {
1421 prom_printf("paging_init: Cannot alloc zero page.\n");
1422 prom_halt();
1423 }
1424 SetPageReserved(mem_map_zero);
1425
1426 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1427 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1428 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1429 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1430 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1431 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1432
1433 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1434 nr_free_pages() << (PAGE_SHIFT-10),
1435 codepages << (PAGE_SHIFT-10),
1436 datapages << (PAGE_SHIFT-10),
1437 initpages << (PAGE_SHIFT-10),
1438 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1439
1440 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1441 cheetah_ecache_flush_init();
1442}
1443
898cf0ec 1444void free_initmem(void)
1da177e4
LT		 1445{
1446 unsigned long addr, initend;
1447
1448 /*
1449 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1450 */
1451 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1452 initend = (unsigned long)(__init_end) & PAGE_MASK;
1453 for (; addr < initend; addr += PAGE_SIZE) {
1454 unsigned long page;
1455 struct page *p;
1456
1457 page = (addr +
1458 ((unsigned long) __va(kern_base)) -
1459 ((unsigned long) KERNBASE));
1460 memset((void *)addr, 0xcc, PAGE_SIZE);
1461 p = virt_to_page(page);
1462
1463 ClearPageReserved(p);
7835e98b 1464 init_page_count(p);
1da177e4
LT		 1465 __free_page(p);
1466 num_physpages++;
1467 totalram_pages++;
1468 }
1469}
1470
1471#ifdef CONFIG_BLK_DEV_INITRD
1472void free_initrd_mem(unsigned long start, unsigned long end)
1473{
1474 if (start < end)
1475 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1476 for (; start < end; start += PAGE_SIZE) {
1477 struct page *p = virt_to_page(start);
1478
1479 ClearPageReserved(p);
7835e98b 1480 init_page_count(p);
1da177e4
LT		 1481 __free_page(p);
1482 num_physpages++;
1483 totalram_pages++;
1484 }
1485}
1486#endif
c4bce90e 1487
c4bce90e
DM		 1488#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1489#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1490#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1491#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1492#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1493#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1494
1495pgprot_t PAGE_KERNEL __read_mostly;
1496EXPORT_SYMBOL(PAGE_KERNEL);
1497
1498pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1499pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1500
1501pgprot_t PAGE_SHARED __read_mostly;
1502EXPORT_SYMBOL(PAGE_SHARED);
1503
c4bce90e
DM		 1504pgprot_t PAGE_EXEC __read_mostly;
1505unsigned long pg_iobits __read_mostly;
1506
1507unsigned long _PAGE_IE __read_mostly;
b2bef442 1508
c4bce90e 1509unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1510EXPORT_SYMBOL(_PAGE_E);
1511
c4bce90e 1512unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1513EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e
DM		 1514
1515static void prot_init_common(unsigned long page_none,
1516 unsigned long page_shared,
1517 unsigned long page_copy,
1518 unsigned long page_readonly,
1519 unsigned long page_exec_bit)
1520{
1521 PAGE_COPY = __pgprot(page_copy);
0f15952a 1522 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1523
1524 protection_map[0x0] = __pgprot(page_none);
1525 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1526 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1527 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1528 protection_map[0x4] = __pgprot(page_readonly);
1529 protection_map[0x5] = __pgprot(page_readonly);
1530 protection_map[0x6] = __pgprot(page_copy);
1531 protection_map[0x7] = __pgprot(page_copy);
1532 protection_map[0x8] = __pgprot(page_none);
1533 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1534 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1535 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1536 protection_map[0xc] = __pgprot(page_readonly);
1537 protection_map[0xd] = __pgprot(page_readonly);
1538 protection_map[0xe] = __pgprot(page_shared);
1539 protection_map[0xf] = __pgprot(page_shared);
1540}
1541
1542static void __init sun4u_pgprot_init(void)
1543{
1544 unsigned long page_none, page_shared, page_copy, page_readonly;
1545 unsigned long page_exec_bit;
1546
1547 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1548 _PAGE_CACHE_4U | _PAGE_P_4U |
1549 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1550 _PAGE_EXEC_4U);
1551 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1552 _PAGE_CACHE_4U | _PAGE_P_4U |
1553 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1554 _PAGE_EXEC_4U | _PAGE_L_4U);
1555 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1556
1557 _PAGE_IE = _PAGE_IE_4U;
1558 _PAGE_E = _PAGE_E_4U;
1559 _PAGE_CACHE = _PAGE_CACHE_4U;
1560
1561 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1562 __ACCESS_BITS_4U | _PAGE_E_4U);
1563
9cc3a1ac 1564 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1565 0xfffff80000000000;
9cc3a1ac
DM		 1566 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1567 _PAGE_P_4U | _PAGE_W_4U);
1568
1569 /* XXX Should use 256MB on Panther. XXX */
1570 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1571
1572 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1573 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1574 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1575 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1576
1577
1578 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1579 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1580 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1581 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1582 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1583 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1584 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1585
1586 page_exec_bit = _PAGE_EXEC_4U;
1587
1588 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1589 page_exec_bit);
1590}
1591
1592static void __init sun4v_pgprot_init(void)
1593{
1594 unsigned long page_none, page_shared, page_copy, page_readonly;
1595 unsigned long page_exec_bit;
1596
1597 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1598 _PAGE_CACHE_4V | _PAGE_P_4V |
1599 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1600 _PAGE_EXEC_4V);
1601 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1602 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1603
1604 _PAGE_IE = _PAGE_IE_4V;
1605 _PAGE_E = _PAGE_E_4V;
1606 _PAGE_CACHE = _PAGE_CACHE_4V;
1607
9cc3a1ac
DM		 1608 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1609 0xfffff80000000000;
1610 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1611 _PAGE_P_4V | _PAGE_W_4V);
1612
1613 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1614 0xfffff80000000000;
9cc3a1ac
DM		 1615 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1616 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1617
1618 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1619 __ACCESS_BITS_4V | _PAGE_E_4V);
1620
1621 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1622 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1623 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1624 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1625 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1626
1627 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1628 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1629 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1630 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1631 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1632 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1633 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1634
1635 page_exec_bit = _PAGE_EXEC_4V;
1636
1637 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1638 page_exec_bit);
1639}
1640
1641unsigned long pte_sz_bits(unsigned long sz)
1642{
1643 if (tlb_type == hypervisor) {
1644 switch (sz) {
1645 case 8 * 1024:
1646 default:
1647 return _PAGE_SZ8K_4V;
1648 case 64 * 1024:
1649 return _PAGE_SZ64K_4V;
1650 case 512 * 1024:
1651 return _PAGE_SZ512K_4V;
1652 case 4 * 1024 * 1024:
1653 return _PAGE_SZ4MB_4V;
1654 };
1655 } else {
1656 switch (sz) {
1657 case 8 * 1024:
1658 default:
1659 return _PAGE_SZ8K_4U;
1660 case 64 * 1024:
1661 return _PAGE_SZ64K_4U;
1662 case 512 * 1024:
1663 return _PAGE_SZ512K_4U;
1664 case 4 * 1024 * 1024:
1665 return _PAGE_SZ4MB_4U;
1666 };
1667 }
1668}
1669
1670pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1671{
1672 pte_t pte;
cf627156
DM		 1673
1674 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1675 pte_val(pte) |= (((unsigned long)space) << 32);
1676 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1677
cf627156 1678 return pte;
c4bce90e
DM		 1679}
1680
1681static unsigned long kern_large_tte(unsigned long paddr)
1682{
1683 unsigned long val;
1684
1685 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1686 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1687 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1688 if (tlb_type == hypervisor)
1689 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1690 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1691 _PAGE_EXEC_4V | _PAGE_W_4V);
1692
1693 return val | paddr;
1694}
1695
1696/*
1697 * Translate PROM's mapping we capture at boot time into physical address.
1698 * The second parameter is only set from prom_callback() invocations.
1699 */
1700unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1701{
1702 unsigned long mask;
1703 int i;
1704
1705 mask = _PAGE_PADDR_4U;
1706 if (tlb_type == hypervisor)
1707 mask = _PAGE_PADDR_4V;
1708
1709 for (i = 0; i < prom_trans_ents; i++) {
1710 struct linux_prom_translation *p = &prom_trans[i];
1711
1712 if (promva >= p->virt &&
1713 promva < (p->virt + p->size)) {
1714 unsigned long base = p->data & mask;
1715
1716 if (error)
1717 *error = 0;
1718 return base + (promva & (8192 - 1));
1719 }
1720 }
1721 if (error)
1722 *error = 1;
1723 return 0UL;
1724}
1725
1726/* XXX We should kill off this ugly thing at so me point. XXX */
1727unsigned long sun4u_get_pte(unsigned long addr)
1728{
1729 pgd_t *pgdp;
1730 pud_t *pudp;
1731 pmd_t *pmdp;
1732 pte_t *ptep;
1733 unsigned long mask = _PAGE_PADDR_4U;
1734
1735 if (tlb_type == hypervisor)
1736 mask = _PAGE_PADDR_4V;
1737
1738 if (addr >= PAGE_OFFSET)
1739 return addr & mask;
1740
1741 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1742 return prom_virt_to_phys(addr, NULL);
1743
1744 pgdp = pgd_offset_k(addr);
1745 pudp = pud_offset(pgdp, addr);
1746 pmdp = pmd_offset(pudp, addr);
1747 ptep = pte_offset_kernel(pmdp, addr);
1748
1749 return pte_val(*ptep) & mask;
1750}
1751
1752/* If not locked, zap it. */
1753void __flush_tlb_all(void)
1754{
1755 unsigned long pstate;
1756 int i;
1757
1758 __asm__ __volatile__("flushw\n\t"
1759 "rdpr %%pstate, %0\n\t"
1760 "wrpr %0, %1, %%pstate"
1761 : "=r" (pstate)
1762 : "i" (PSTATE_IE));
1763 if (tlb_type == spitfire) {
1764 for (i = 0; i < 64; i++) {
1765 /* Spitfire Errata #32 workaround */
1766 /* NOTE: Always runs on spitfire, so no
1767 * cheetah+ page size encodings.
1768 */
1769 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1770 "flush %%g6"
1771 : /* No outputs */
1772 : "r" (0),
1773 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1774
1775 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1776 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1777 "membar #Sync"
1778 : /* no outputs */
1779 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1780 spitfire_put_dtlb_data(i, 0x0UL);
1781 }
1782
1783 /* Spitfire Errata #32 workaround */
1784 /* NOTE: Always runs on spitfire, so no
1785 * cheetah+ page size encodings.
1786 */
1787 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1788 "flush %%g6"
1789 : /* No outputs */
1790 : "r" (0),
1791 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1792
1793 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1794 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1795 "membar #Sync"
1796 : /* no outputs */
1797 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1798 spitfire_put_itlb_data(i, 0x0UL);
1799 }
1800 }
1801 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1802 cheetah_flush_dtlb_all();
1803 cheetah_flush_itlb_all();
1804 }
1805 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1806 : : "r" (pstate));
1807}
88d70794
DM		 1808
1809#ifdef CONFIG_MEMORY_HOTPLUG
1810
1811void online_page(struct page *page)
1812{
1813 ClearPageReserved(page);
1814 set_page_count(page, 0);
1815 free_cold_page(page);
1816 totalram_pages++;
1817 num_physpages++;
1818}
1819
1820int remove_memory(u64 start, u64 size)
1821{
1822 return -EINVAL;
1823}
1824
1825#endif /* CONFIG_MEMORY_HOTPLUG */
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