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[mirror_ubuntu-eoan-kernel.git] / arch / tile / include / uapi / arch / spr_def_32.h
CommitLineData
e2be04c7 1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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2/*
3 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __DOXYGEN__
17
43e85859
DH
18#ifndef __ARCH_SPR_DEF_32_H__
19#define __ARCH_SPR_DEF_32_H__
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20
21#define SPR_AUX_PERF_COUNT_0 0x6005
22#define SPR_AUX_PERF_COUNT_1 0x6006
23#define SPR_AUX_PERF_COUNT_CTL 0x6007
24#define SPR_AUX_PERF_COUNT_STS 0x6008
25#define SPR_CYCLE_HIGH 0x4e06
26#define SPR_CYCLE_LOW 0x4e07
27#define SPR_DMA_BYTE 0x3900
28#define SPR_DMA_CHUNK_SIZE 0x3901
29#define SPR_DMA_CTR 0x3902
30#define SPR_DMA_CTR__REQUEST_MASK 0x1
31#define SPR_DMA_CTR__SUSPEND_MASK 0x2
32#define SPR_DMA_DST_ADDR 0x3903
33#define SPR_DMA_DST_CHUNK_ADDR 0x3904
34#define SPR_DMA_SRC_ADDR 0x3905
35#define SPR_DMA_SRC_CHUNK_ADDR 0x3906
36#define SPR_DMA_STATUS__DONE_MASK 0x1
37#define SPR_DMA_STATUS__BUSY_MASK 0x2
38#define SPR_DMA_STATUS__RUNNING_MASK 0x10
39#define SPR_DMA_STRIDE 0x3907
40#define SPR_DMA_USER_STATUS 0x3908
41#define SPR_DONE 0x4e08
42#define SPR_EVENT_BEGIN 0x4e0d
43#define SPR_EVENT_END 0x4e0e
44#define SPR_EX_CONTEXT_0_0 0x4a05
45#define SPR_EX_CONTEXT_0_1 0x4a06
46#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
47#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
48#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
49#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
50#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
51#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
52#define SPR_EX_CONTEXT_1_0 0x4805
53#define SPR_EX_CONTEXT_1_1 0x4806
54#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
55#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
56#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
57#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
58#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
59#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
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60#define SPR_EX_CONTEXT_2_0 0x4605
61#define SPR_EX_CONTEXT_2_1 0x4606
62#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
63#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
64#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
65#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
66#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
67#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
867e359b 68#define SPR_FAIL 0x4e09
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69#define SPR_IDN_AVAIL_EN 0x3e05
70#define SPR_IDN_CA_DATA 0x0b00
71#define SPR_IDN_DATA_AVAIL 0x0b03
72#define SPR_IDN_DEADLOCK_TIMEOUT 0x3406
73#define SPR_IDN_DEMUX_CA_COUNT 0x0a05
74#define SPR_IDN_DEMUX_COUNT_0 0x0a06
75#define SPR_IDN_DEMUX_COUNT_1 0x0a07
76#define SPR_IDN_DEMUX_CTL 0x0a08
77#define SPR_IDN_DEMUX_QUEUE_SEL 0x0a0a
78#define SPR_IDN_DEMUX_STATUS 0x0a0b
79#define SPR_IDN_DEMUX_WRITE_FIFO 0x0a0c
80#define SPR_IDN_DIRECTION_PROTECT 0x2e05
81#define SPR_IDN_PENDING 0x0a0e
82#define SPR_IDN_REFILL_EN 0x0e05
83#define SPR_IDN_SP_FIFO_DATA 0x0a0f
84#define SPR_IDN_SP_FIFO_SEL 0x0a10
85#define SPR_IDN_SP_FREEZE 0x0a11
86#define SPR_IDN_SP_FREEZE__SP_FRZ_MASK 0x1
87#define SPR_IDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
88#define SPR_IDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
89#define SPR_IDN_SP_STATE 0x0a12
90#define SPR_IDN_TAG_0 0x0a13
91#define SPR_IDN_TAG_1 0x0a14
92#define SPR_IDN_TAG_VALID 0x0a15
93#define SPR_IDN_TILE_COORD 0x0a16
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94#define SPR_INTCTRL_0_STATUS 0x4a07
95#define SPR_INTCTRL_1_STATUS 0x4807
a78c942d 96#define SPR_INTCTRL_2_STATUS 0x4607
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97#define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a
98#define SPR_INTERRUPT_MASK_0_0 0x4a08
99#define SPR_INTERRUPT_MASK_0_1 0x4a09
100#define SPR_INTERRUPT_MASK_1_0 0x4809
101#define SPR_INTERRUPT_MASK_1_1 0x480a
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102#define SPR_INTERRUPT_MASK_2_0 0x4608
103#define SPR_INTERRUPT_MASK_2_1 0x4609
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104#define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a
105#define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b
106#define SPR_INTERRUPT_MASK_RESET_1_0 0x480b
107#define SPR_INTERRUPT_MASK_RESET_1_1 0x480c
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108#define SPR_INTERRUPT_MASK_RESET_2_0 0x460a
109#define SPR_INTERRUPT_MASK_RESET_2_1 0x460b
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110#define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c
111#define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d
112#define SPR_INTERRUPT_MASK_SET_1_0 0x480d
113#define SPR_INTERRUPT_MASK_SET_1_1 0x480e
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114#define SPR_INTERRUPT_MASK_SET_2_0 0x460c
115#define SPR_INTERRUPT_MASK_SET_2_1 0x460d
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116#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x6000
117#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x6001
118#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x6002
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119#define SPR_MPL_DMA_CPL_SET_0 0x5800
120#define SPR_MPL_DMA_CPL_SET_1 0x5801
a78c942d 121#define SPR_MPL_DMA_CPL_SET_2 0x5802
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122#define SPR_MPL_DMA_NOTIFY_SET_0 0x3800
123#define SPR_MPL_DMA_NOTIFY_SET_1 0x3801
a78c942d 124#define SPR_MPL_DMA_NOTIFY_SET_2 0x3802
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125#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
126#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
127#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
128#define SPR_MPL_IDN_AVAIL_SET_0 0x3e00
129#define SPR_MPL_IDN_AVAIL_SET_1 0x3e01
130#define SPR_MPL_IDN_AVAIL_SET_2 0x3e02
131#define SPR_MPL_IDN_CA_SET_0 0x3a00
132#define SPR_MPL_IDN_CA_SET_1 0x3a01
133#define SPR_MPL_IDN_CA_SET_2 0x3a02
134#define SPR_MPL_IDN_COMPLETE_SET_0 0x1200
135#define SPR_MPL_IDN_COMPLETE_SET_1 0x1201
136#define SPR_MPL_IDN_COMPLETE_SET_2 0x1202
137#define SPR_MPL_IDN_FIREWALL_SET_0 0x2e00
138#define SPR_MPL_IDN_FIREWALL_SET_1 0x2e01
139#define SPR_MPL_IDN_FIREWALL_SET_2 0x2e02
140#define SPR_MPL_IDN_REFILL_SET_0 0x0e00
141#define SPR_MPL_IDN_REFILL_SET_1 0x0e01
142#define SPR_MPL_IDN_REFILL_SET_2 0x0e02
143#define SPR_MPL_IDN_TIMER_SET_0 0x3400
144#define SPR_MPL_IDN_TIMER_SET_1 0x3401
145#define SPR_MPL_IDN_TIMER_SET_2 0x3402
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146#define SPR_MPL_INTCTRL_0_SET_0 0x4a00
147#define SPR_MPL_INTCTRL_0_SET_1 0x4a01
a78c942d 148#define SPR_MPL_INTCTRL_0_SET_2 0x4a02
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149#define SPR_MPL_INTCTRL_1_SET_0 0x4800
150#define SPR_MPL_INTCTRL_1_SET_1 0x4801
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151#define SPR_MPL_INTCTRL_1_SET_2 0x4802
152#define SPR_MPL_INTCTRL_2_SET_0 0x4600
153#define SPR_MPL_INTCTRL_2_SET_1 0x4601
154#define SPR_MPL_INTCTRL_2_SET_2 0x4602
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155#define SPR_MPL_PERF_COUNT_SET_0 0x4200
156#define SPR_MPL_PERF_COUNT_SET_1 0x4201
157#define SPR_MPL_PERF_COUNT_SET_2 0x4202
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158#define SPR_MPL_SN_ACCESS_SET_0 0x0800
159#define SPR_MPL_SN_ACCESS_SET_1 0x0801
a78c942d 160#define SPR_MPL_SN_ACCESS_SET_2 0x0802
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161#define SPR_MPL_SN_CPL_SET_0 0x5a00
162#define SPR_MPL_SN_CPL_SET_1 0x5a01
a78c942d 163#define SPR_MPL_SN_CPL_SET_2 0x5a02
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164#define SPR_MPL_SN_FIREWALL_SET_0 0x2c00
165#define SPR_MPL_SN_FIREWALL_SET_1 0x2c01
a78c942d 166#define SPR_MPL_SN_FIREWALL_SET_2 0x2c02
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167#define SPR_MPL_SN_NOTIFY_SET_0 0x2a00
168#define SPR_MPL_SN_NOTIFY_SET_1 0x2a01
a78c942d 169#define SPR_MPL_SN_NOTIFY_SET_2 0x2a02
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170#define SPR_MPL_UDN_ACCESS_SET_0 0x0c00
171#define SPR_MPL_UDN_ACCESS_SET_1 0x0c01
a78c942d 172#define SPR_MPL_UDN_ACCESS_SET_2 0x0c02
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173#define SPR_MPL_UDN_AVAIL_SET_0 0x4000
174#define SPR_MPL_UDN_AVAIL_SET_1 0x4001
a78c942d 175#define SPR_MPL_UDN_AVAIL_SET_2 0x4002
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176#define SPR_MPL_UDN_CA_SET_0 0x3c00
177#define SPR_MPL_UDN_CA_SET_1 0x3c01
a78c942d 178#define SPR_MPL_UDN_CA_SET_2 0x3c02
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179#define SPR_MPL_UDN_COMPLETE_SET_0 0x1400
180#define SPR_MPL_UDN_COMPLETE_SET_1 0x1401
a78c942d 181#define SPR_MPL_UDN_COMPLETE_SET_2 0x1402
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182#define SPR_MPL_UDN_FIREWALL_SET_0 0x3000
183#define SPR_MPL_UDN_FIREWALL_SET_1 0x3001
a78c942d 184#define SPR_MPL_UDN_FIREWALL_SET_2 0x3002
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185#define SPR_MPL_UDN_REFILL_SET_0 0x1000
186#define SPR_MPL_UDN_REFILL_SET_1 0x1001
a78c942d 187#define SPR_MPL_UDN_REFILL_SET_2 0x1002
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188#define SPR_MPL_UDN_TIMER_SET_0 0x3600
189#define SPR_MPL_UDN_TIMER_SET_1 0x3601
a78c942d 190#define SPR_MPL_UDN_TIMER_SET_2 0x3602
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191#define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00
192#define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01
a78c942d 193#define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02
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194#define SPR_PASS 0x4e0b
195#define SPR_PERF_COUNT_0 0x4205
196#define SPR_PERF_COUNT_1 0x4206
197#define SPR_PERF_COUNT_CTL 0x4207
a78c942d 198#define SPR_PERF_COUNT_DN_CTL 0x4210
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199#define SPR_PERF_COUNT_STS 0x4208
200#define SPR_PROC_STATUS 0x4f00
201#define SPR_SIM_CONTROL 0x4e0c
202#define SPR_SNCTL 0x0805
203#define SPR_SNCTL__FRZFABRIC_MASK 0x1
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204#define SPR_SNSTATIC 0x080c
205#define SPR_SYSTEM_SAVE_0_0 0x4b00
206#define SPR_SYSTEM_SAVE_0_1 0x4b01
207#define SPR_SYSTEM_SAVE_0_2 0x4b02
208#define SPR_SYSTEM_SAVE_0_3 0x4b03
209#define SPR_SYSTEM_SAVE_1_0 0x4900
210#define SPR_SYSTEM_SAVE_1_1 0x4901
211#define SPR_SYSTEM_SAVE_1_2 0x4902
212#define SPR_SYSTEM_SAVE_1_3 0x4903
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213#define SPR_SYSTEM_SAVE_2_0 0x4700
214#define SPR_SYSTEM_SAVE_2_1 0x4701
215#define SPR_SYSTEM_SAVE_2_2 0x4702
216#define SPR_SYSTEM_SAVE_2_3 0x4703
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217#define SPR_TILE_COORD 0x4c17
218#define SPR_TILE_RTF_HWM 0x4e10
219#define SPR_TILE_TIMER_CONTROL 0x3205
220#define SPR_TILE_WRITE_PENDING 0x4e0f
221#define SPR_UDN_AVAIL_EN 0x4005
222#define SPR_UDN_CA_DATA 0x0d00
223#define SPR_UDN_DATA_AVAIL 0x0d03
224#define SPR_UDN_DEADLOCK_TIMEOUT 0x3606
225#define SPR_UDN_DEMUX_CA_COUNT 0x0c05
226#define SPR_UDN_DEMUX_COUNT_0 0x0c06
227#define SPR_UDN_DEMUX_COUNT_1 0x0c07
228#define SPR_UDN_DEMUX_COUNT_2 0x0c08
229#define SPR_UDN_DEMUX_COUNT_3 0x0c09
230#define SPR_UDN_DEMUX_CTL 0x0c0a
231#define SPR_UDN_DEMUX_QUEUE_SEL 0x0c0c
232#define SPR_UDN_DEMUX_STATUS 0x0c0d
233#define SPR_UDN_DEMUX_WRITE_FIFO 0x0c0e
234#define SPR_UDN_DIRECTION_PROTECT 0x3005
b8ace083 235#define SPR_UDN_PENDING 0x0c10
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236#define SPR_UDN_REFILL_EN 0x1005
237#define SPR_UDN_SP_FIFO_DATA 0x0c11
238#define SPR_UDN_SP_FIFO_SEL 0x0c12
239#define SPR_UDN_SP_FREEZE 0x0c13
240#define SPR_UDN_SP_FREEZE__SP_FRZ_MASK 0x1
241#define SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
242#define SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
243#define SPR_UDN_SP_STATE 0x0c14
244#define SPR_UDN_TAG_0 0x0c15
245#define SPR_UDN_TAG_1 0x0c16
246#define SPR_UDN_TAG_2 0x0c17
247#define SPR_UDN_TAG_3 0x0c18
248#define SPR_UDN_TAG_VALID 0x0c19
249#define SPR_UDN_TILE_COORD 0x0c1a
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250#define SPR_WATCH_CTL 0x4209
251#define SPR_WATCH_MASK 0x420a
252#define SPR_WATCH_VAL 0x420b
867e359b 253
43e85859 254#endif /* !defined(__ARCH_SPR_DEF_32_H__) */
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255
256#endif /* !defined(__DOXYGEN__) */