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867e359b | 1 | /* |
eb7c792d | 2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
867e359b CM |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/string.h> | |
867e359b | 17 | #include <asm/backtrace.h> |
eb7c792d | 18 | #include <asm/tile-desc.h> |
93013a0f | 19 | #include <arch/abi.h> |
867e359b | 20 | |
93013a0f | 21 | #ifdef __tilegx__ |
1fcbe027 | 22 | #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE |
1fcbe027 CM |
23 | #define tile_decoded_instruction tilegx_decoded_instruction |
24 | #define tile_mnemonic tilegx_mnemonic | |
25 | #define parse_insn_tile parse_insn_tilegx | |
26 | #define TILE_OPC_IRET TILEGX_OPC_IRET | |
27 | #define TILE_OPC_ADDI TILEGX_OPC_ADDI | |
28 | #define TILE_OPC_ADDLI TILEGX_OPC_ADDLI | |
29 | #define TILE_OPC_INFO TILEGX_OPC_INFO | |
30 | #define TILE_OPC_INFOL TILEGX_OPC_INFOL | |
31 | #define TILE_OPC_JRP TILEGX_OPC_JRP | |
32 | #define TILE_OPC_MOVE TILEGX_OPC_MOVE | |
33 | #define OPCODE_STORE TILEGX_OPC_ST | |
34 | typedef long long bt_int_reg_t; | |
35 | #else | |
eb7c792d CM |
36 | #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE |
37 | #define tile_decoded_instruction tilepro_decoded_instruction | |
38 | #define tile_mnemonic tilepro_mnemonic | |
39 | #define parse_insn_tile parse_insn_tilepro | |
40 | #define TILE_OPC_IRET TILEPRO_OPC_IRET | |
41 | #define TILE_OPC_ADDI TILEPRO_OPC_ADDI | |
42 | #define TILE_OPC_ADDLI TILEPRO_OPC_ADDLI | |
43 | #define TILE_OPC_INFO TILEPRO_OPC_INFO | |
44 | #define TILE_OPC_INFOL TILEPRO_OPC_INFOL | |
45 | #define TILE_OPC_JRP TILEPRO_OPC_JRP | |
46 | #define TILE_OPC_MOVE TILEPRO_OPC_MOVE | |
47 | #define OPCODE_STORE TILEPRO_OPC_SW | |
1fcbe027 CM |
48 | typedef int bt_int_reg_t; |
49 | #endif | |
50 | ||
93013a0f | 51 | /* A decoded bundle used for backtracer analysis. */ |
0707ad30 | 52 | struct BacktraceBundle { |
867e359b CM |
53 | tile_bundle_bits bits; |
54 | int num_insns; | |
55 | struct tile_decoded_instruction | |
56 | insns[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]; | |
0707ad30 | 57 | }; |
867e359b CM |
58 | |
59 | ||
93013a0f | 60 | /* Locates an instruction inside the given bundle that |
867e359b CM |
61 | * has the specified mnemonic, and whose first 'num_operands_to_match' |
62 | * operands exactly match those in 'operand_values'. | |
63 | */ | |
0707ad30 CM |
64 | static const struct tile_decoded_instruction *find_matching_insn( |
65 | const struct BacktraceBundle *bundle, | |
66 | tile_mnemonic mnemonic, | |
67 | const int *operand_values, | |
68 | int num_operands_to_match) | |
867e359b CM |
69 | { |
70 | int i, j; | |
71 | bool match; | |
72 | ||
73 | for (i = 0; i < bundle->num_insns; i++) { | |
74 | const struct tile_decoded_instruction *insn = | |
75 | &bundle->insns[i]; | |
76 | ||
77 | if (insn->opcode->mnemonic != mnemonic) | |
78 | continue; | |
79 | ||
80 | match = true; | |
81 | for (j = 0; j < num_operands_to_match; j++) { | |
82 | if (operand_values[j] != insn->operand_values[j]) { | |
83 | match = false; | |
84 | break; | |
85 | } | |
86 | } | |
87 | ||
88 | if (match) | |
89 | return insn; | |
90 | } | |
91 | ||
92 | return NULL; | |
93 | } | |
94 | ||
93013a0f | 95 | /* Does this bundle contain an 'iret' instruction? */ |
0707ad30 | 96 | static inline bool bt_has_iret(const struct BacktraceBundle *bundle) |
867e359b CM |
97 | { |
98 | return find_matching_insn(bundle, TILE_OPC_IRET, NULL, 0) != NULL; | |
99 | } | |
100 | ||
93013a0f | 101 | /* Does this bundle contain an 'addi sp, sp, OFFSET' or |
867e359b CM |
102 | * 'addli sp, sp, OFFSET' instruction, and if so, what is OFFSET? |
103 | */ | |
0707ad30 | 104 | static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust) |
867e359b CM |
105 | { |
106 | static const int vals[2] = { TREG_SP, TREG_SP }; | |
107 | ||
108 | const struct tile_decoded_instruction *insn = | |
109 | find_matching_insn(bundle, TILE_OPC_ADDI, vals, 2); | |
110 | if (insn == NULL) | |
111 | insn = find_matching_insn(bundle, TILE_OPC_ADDLI, vals, 2); | |
93013a0f | 112 | #ifdef __tilegx__ |
1fcbe027 CM |
113 | if (insn == NULL) |
114 | insn = find_matching_insn(bundle, TILEGX_OPC_ADDXLI, vals, 2); | |
115 | if (insn == NULL) | |
116 | insn = find_matching_insn(bundle, TILEGX_OPC_ADDXI, vals, 2); | |
117 | #endif | |
867e359b CM |
118 | if (insn == NULL) |
119 | return false; | |
120 | ||
121 | *adjust = insn->operand_values[2]; | |
122 | return true; | |
123 | } | |
124 | ||
93013a0f | 125 | /* Does this bundle contain any 'info OP' or 'infol OP' |
867e359b CM |
126 | * instruction, and if so, what are their OP? Note that OP is interpreted |
127 | * as an unsigned value by this code since that's what the caller wants. | |
128 | * Returns the number of info ops found. | |
129 | */ | |
0707ad30 | 130 | static int bt_get_info_ops(const struct BacktraceBundle *bundle, |
867e359b CM |
131 | int operands[MAX_INFO_OPS_PER_BUNDLE]) |
132 | { | |
133 | int num_ops = 0; | |
134 | int i; | |
135 | ||
136 | for (i = 0; i < bundle->num_insns; i++) { | |
137 | const struct tile_decoded_instruction *insn = | |
138 | &bundle->insns[i]; | |
139 | ||
140 | if (insn->opcode->mnemonic == TILE_OPC_INFO || | |
141 | insn->opcode->mnemonic == TILE_OPC_INFOL) { | |
142 | operands[num_ops++] = insn->operand_values[0]; | |
143 | } | |
144 | } | |
145 | ||
146 | return num_ops; | |
147 | } | |
148 | ||
93013a0f | 149 | /* Does this bundle contain a jrp instruction, and if so, to which |
867e359b CM |
150 | * register is it jumping? |
151 | */ | |
0707ad30 | 152 | static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg) |
867e359b CM |
153 | { |
154 | const struct tile_decoded_instruction *insn = | |
155 | find_matching_insn(bundle, TILE_OPC_JRP, NULL, 0); | |
156 | if (insn == NULL) | |
157 | return false; | |
158 | ||
159 | *target_reg = insn->operand_values[0]; | |
160 | return true; | |
161 | } | |
162 | ||
93013a0f | 163 | /* Does this bundle modify the specified register in any way? */ |
0707ad30 | 164 | static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg) |
867e359b CM |
165 | { |
166 | int i, j; | |
167 | for (i = 0; i < bundle->num_insns; i++) { | |
168 | const struct tile_decoded_instruction *insn = | |
169 | &bundle->insns[i]; | |
170 | ||
171 | if (insn->opcode->implicitly_written_register == reg) | |
172 | return true; | |
173 | ||
174 | for (j = 0; j < insn->opcode->num_operands; j++) | |
175 | if (insn->operands[j]->is_dest_reg && | |
176 | insn->operand_values[j] == reg) | |
177 | return true; | |
178 | } | |
179 | ||
180 | return false; | |
181 | } | |
182 | ||
93013a0f | 183 | /* Does this bundle modify sp? */ |
0707ad30 | 184 | static inline bool bt_modifies_sp(const struct BacktraceBundle *bundle) |
867e359b CM |
185 | { |
186 | return bt_modifies_reg(bundle, TREG_SP); | |
187 | } | |
188 | ||
93013a0f | 189 | /* Does this bundle modify lr? */ |
0707ad30 | 190 | static inline bool bt_modifies_lr(const struct BacktraceBundle *bundle) |
867e359b CM |
191 | { |
192 | return bt_modifies_reg(bundle, TREG_LR); | |
193 | } | |
194 | ||
93013a0f | 195 | /* Does this bundle contain the instruction 'move fp, sp'? */ |
0707ad30 | 196 | static inline bool bt_has_move_r52_sp(const struct BacktraceBundle *bundle) |
867e359b CM |
197 | { |
198 | static const int vals[2] = { 52, TREG_SP }; | |
199 | return find_matching_insn(bundle, TILE_OPC_MOVE, vals, 2) != NULL; | |
200 | } | |
201 | ||
93013a0f | 202 | /* Does this bundle contain a store of lr to sp? */ |
0707ad30 | 203 | static inline bool bt_has_sw_sp_lr(const struct BacktraceBundle *bundle) |
867e359b CM |
204 | { |
205 | static const int vals[2] = { TREG_SP, TREG_LR }; | |
1fcbe027 CM |
206 | return find_matching_insn(bundle, OPCODE_STORE, vals, 2) != NULL; |
207 | } | |
208 | ||
93013a0f CM |
209 | #ifdef __tilegx__ |
210 | /* Track moveli values placed into registers. */ | |
1fcbe027 CM |
211 | static inline void bt_update_moveli(const struct BacktraceBundle *bundle, |
212 | int moveli_args[]) | |
213 | { | |
214 | int i; | |
215 | for (i = 0; i < bundle->num_insns; i++) { | |
216 | const struct tile_decoded_instruction *insn = | |
217 | &bundle->insns[i]; | |
218 | ||
219 | if (insn->opcode->mnemonic == TILEGX_OPC_MOVELI) { | |
220 | int reg = insn->operand_values[0]; | |
221 | moveli_args[reg] = insn->operand_values[1]; | |
222 | } | |
223 | } | |
867e359b CM |
224 | } |
225 | ||
93013a0f | 226 | /* Does this bundle contain an 'add sp, sp, reg' instruction |
1fcbe027 CM |
227 | * from a register that we saw a moveli into, and if so, what |
228 | * is the value in the register? | |
229 | */ | |
230 | static bool bt_has_add_sp(const struct BacktraceBundle *bundle, int *adjust, | |
231 | int moveli_args[]) | |
232 | { | |
233 | static const int vals[2] = { TREG_SP, TREG_SP }; | |
234 | ||
235 | const struct tile_decoded_instruction *insn = | |
236 | find_matching_insn(bundle, TILEGX_OPC_ADDX, vals, 2); | |
237 | if (insn) { | |
238 | int reg = insn->operand_values[2]; | |
239 | if (moveli_args[reg]) { | |
240 | *adjust = moveli_args[reg]; | |
241 | return true; | |
242 | } | |
243 | } | |
244 | return false; | |
245 | } | |
246 | #endif | |
247 | ||
93013a0f | 248 | /* Locates the caller's PC and SP for a program starting at the |
867e359b CM |
249 | * given address. |
250 | */ | |
0707ad30 | 251 | static void find_caller_pc_and_caller_sp(CallerLocation *location, |
93013a0f | 252 | const unsigned long start_pc, |
0707ad30 CM |
253 | BacktraceMemoryReader read_memory_func, |
254 | void *read_memory_func_extra) | |
867e359b CM |
255 | { |
256 | /* Have we explicitly decided what the sp is, | |
257 | * rather than just the default? | |
258 | */ | |
259 | bool sp_determined = false; | |
260 | ||
261 | /* Has any bundle seen so far modified lr? */ | |
262 | bool lr_modified = false; | |
263 | ||
264 | /* Have we seen a move from sp to fp? */ | |
265 | bool sp_moved_to_r52 = false; | |
266 | ||
267 | /* Have we seen a terminating bundle? */ | |
268 | bool seen_terminating_bundle = false; | |
269 | ||
270 | /* Cut down on round-trip reading overhead by reading several | |
271 | * bundles at a time. | |
272 | */ | |
273 | tile_bundle_bits prefetched_bundles[32]; | |
274 | int num_bundles_prefetched = 0; | |
275 | int next_bundle = 0; | |
93013a0f | 276 | unsigned long pc; |
867e359b | 277 | |
93013a0f | 278 | #ifdef __tilegx__ |
1fcbe027 CM |
279 | /* Naively try to track moveli values to support addx for -m32. */ |
280 | int moveli_args[TILEGX_NUM_REGISTERS] = { 0 }; | |
281 | #endif | |
282 | ||
867e359b CM |
283 | /* Default to assuming that the caller's sp is the current sp. |
284 | * This is necessary to handle the case where we start backtracing | |
285 | * right at the end of the epilog. | |
286 | */ | |
287 | location->sp_location = SP_LOC_OFFSET; | |
288 | location->sp_offset = 0; | |
289 | ||
290 | /* Default to having no idea where the caller PC is. */ | |
291 | location->pc_location = PC_LOC_UNKNOWN; | |
292 | ||
293 | /* Don't even try if the PC is not aligned. */ | |
294 | if (start_pc % TILE_BUNDLE_ALIGNMENT_IN_BYTES != 0) | |
295 | return; | |
296 | ||
297 | for (pc = start_pc;; pc += sizeof(tile_bundle_bits)) { | |
298 | ||
0707ad30 | 299 | struct BacktraceBundle bundle; |
867e359b CM |
300 | int num_info_ops, info_operands[MAX_INFO_OPS_PER_BUNDLE]; |
301 | int one_ago, jrp_reg; | |
302 | bool has_jrp; | |
303 | ||
304 | if (next_bundle >= num_bundles_prefetched) { | |
305 | /* Prefetch some bytes, but don't cross a page | |
306 | * boundary since that might cause a read failure we | |
307 | * don't care about if we only need the first few | |
308 | * bytes. Note: we don't care what the actual page | |
309 | * size is; using the minimum possible page size will | |
310 | * prevent any problems. | |
311 | */ | |
312 | unsigned int bytes_to_prefetch = 4096 - (pc & 4095); | |
313 | if (bytes_to_prefetch > sizeof prefetched_bundles) | |
314 | bytes_to_prefetch = sizeof prefetched_bundles; | |
315 | ||
316 | if (!read_memory_func(prefetched_bundles, pc, | |
317 | bytes_to_prefetch, | |
318 | read_memory_func_extra)) { | |
319 | if (pc == start_pc) { | |
320 | /* The program probably called a bad | |
321 | * address, such as a NULL pointer. | |
322 | * So treat this as if we are at the | |
323 | * start of the function prolog so the | |
324 | * backtrace will show how we got here. | |
325 | */ | |
326 | location->pc_location = PC_LOC_IN_LR; | |
327 | return; | |
328 | } | |
329 | ||
330 | /* Unreadable address. Give up. */ | |
331 | break; | |
332 | } | |
333 | ||
334 | next_bundle = 0; | |
335 | num_bundles_prefetched = | |
336 | bytes_to_prefetch / sizeof(tile_bundle_bits); | |
337 | } | |
338 | ||
339 | /* Decode the next bundle. */ | |
340 | bundle.bits = prefetched_bundles[next_bundle++]; | |
341 | bundle.num_insns = | |
342 | parse_insn_tile(bundle.bits, pc, bundle.insns); | |
343 | num_info_ops = bt_get_info_ops(&bundle, info_operands); | |
344 | ||
345 | /* First look at any one_ago info ops if they are interesting, | |
346 | * since they should shadow any non-one-ago info ops. | |
347 | */ | |
348 | for (one_ago = (pc != start_pc) ? 1 : 0; | |
349 | one_ago >= 0; one_ago--) { | |
350 | int i; | |
351 | for (i = 0; i < num_info_ops; i++) { | |
352 | int info_operand = info_operands[i]; | |
353 | if (info_operand < CALLER_UNKNOWN_BASE) { | |
354 | /* Weird; reserved value, ignore it. */ | |
355 | continue; | |
356 | } | |
357 | ||
358 | /* Skip info ops which are not in the | |
359 | * "one_ago" mode we want right now. | |
360 | */ | |
361 | if (((info_operand & ONE_BUNDLE_AGO_FLAG) != 0) | |
362 | != (one_ago != 0)) | |
363 | continue; | |
364 | ||
365 | /* Clear the flag to make later checking | |
366 | * easier. */ | |
367 | info_operand &= ~ONE_BUNDLE_AGO_FLAG; | |
368 | ||
369 | /* Default to looking at PC_IN_LR_FLAG. */ | |
370 | if (info_operand & PC_IN_LR_FLAG) | |
371 | location->pc_location = | |
372 | PC_LOC_IN_LR; | |
373 | else | |
374 | location->pc_location = | |
375 | PC_LOC_ON_STACK; | |
376 | ||
377 | switch (info_operand) { | |
378 | case CALLER_UNKNOWN_BASE: | |
379 | location->pc_location = PC_LOC_UNKNOWN; | |
380 | location->sp_location = SP_LOC_UNKNOWN; | |
381 | return; | |
382 | ||
383 | case CALLER_SP_IN_R52_BASE: | |
384 | case CALLER_SP_IN_R52_BASE | PC_IN_LR_FLAG: | |
385 | location->sp_location = SP_LOC_IN_R52; | |
386 | return; | |
387 | ||
388 | default: | |
389 | { | |
390 | const unsigned int val = info_operand | |
391 | - CALLER_SP_OFFSET_BASE; | |
392 | const unsigned int sp_offset = | |
393 | (val >> NUM_INFO_OP_FLAGS) * 8; | |
394 | if (sp_offset < 32768) { | |
395 | /* This is a properly encoded | |
396 | * SP offset. */ | |
397 | location->sp_location = | |
398 | SP_LOC_OFFSET; | |
399 | location->sp_offset = | |
400 | sp_offset; | |
401 | return; | |
402 | } else { | |
403 | /* This looked like an SP | |
404 | * offset, but it's outside | |
405 | * the legal range, so this | |
406 | * must be an unrecognized | |
407 | * info operand. Ignore it. | |
408 | */ | |
409 | } | |
410 | } | |
411 | break; | |
412 | } | |
413 | } | |
414 | } | |
415 | ||
416 | if (seen_terminating_bundle) { | |
417 | /* We saw a terminating bundle during the previous | |
418 | * iteration, so we were only looking for an info op. | |
419 | */ | |
420 | break; | |
421 | } | |
422 | ||
423 | if (bundle.bits == 0) { | |
424 | /* Wacky terminating bundle. Stop looping, and hope | |
425 | * we've already seen enough to find the caller. | |
426 | */ | |
427 | break; | |
428 | } | |
429 | ||
430 | /* | |
431 | * Try to determine caller's SP. | |
432 | */ | |
433 | ||
434 | if (!sp_determined) { | |
435 | int adjust; | |
1fcbe027 | 436 | if (bt_has_addi_sp(&bundle, &adjust) |
93013a0f | 437 | #ifdef __tilegx__ |
1fcbe027 CM |
438 | || bt_has_add_sp(&bundle, &adjust, moveli_args) |
439 | #endif | |
440 | ) { | |
867e359b CM |
441 | location->sp_location = SP_LOC_OFFSET; |
442 | ||
443 | if (adjust <= 0) { | |
444 | /* We are in prolog about to adjust | |
445 | * SP. */ | |
446 | location->sp_offset = 0; | |
447 | } else { | |
448 | /* We are in epilog restoring SP. */ | |
449 | location->sp_offset = adjust; | |
450 | } | |
451 | ||
452 | sp_determined = true; | |
453 | } else { | |
454 | if (bt_has_move_r52_sp(&bundle)) { | |
455 | /* Maybe in prolog, creating an | |
456 | * alloca-style frame. But maybe in | |
457 | * the middle of a fixed-size frame | |
458 | * clobbering r52 with SP. | |
459 | */ | |
460 | sp_moved_to_r52 = true; | |
461 | } | |
462 | ||
463 | if (bt_modifies_sp(&bundle)) { | |
464 | if (sp_moved_to_r52) { | |
465 | /* We saw SP get saved into | |
466 | * r52 earlier (or now), which | |
467 | * must have been in the | |
468 | * prolog, so we now know that | |
469 | * SP is still holding the | |
470 | * caller's sp value. | |
471 | */ | |
472 | location->sp_location = | |
473 | SP_LOC_OFFSET; | |
474 | location->sp_offset = 0; | |
475 | } else { | |
476 | /* Someone must have saved | |
477 | * aside the caller's SP value | |
478 | * into r52, so r52 holds the | |
479 | * current value. | |
480 | */ | |
481 | location->sp_location = | |
482 | SP_LOC_IN_R52; | |
483 | } | |
484 | sp_determined = true; | |
485 | } | |
486 | } | |
1fcbe027 | 487 | |
93013a0f | 488 | #ifdef __tilegx__ |
1fcbe027 CM |
489 | /* Track moveli arguments for -m32 mode. */ |
490 | bt_update_moveli(&bundle, moveli_args); | |
491 | #endif | |
867e359b CM |
492 | } |
493 | ||
494 | if (bt_has_iret(&bundle)) { | |
495 | /* This is a terminating bundle. */ | |
496 | seen_terminating_bundle = true; | |
497 | continue; | |
498 | } | |
499 | ||
500 | /* | |
501 | * Try to determine caller's PC. | |
502 | */ | |
503 | ||
504 | jrp_reg = -1; | |
505 | has_jrp = bt_has_jrp(&bundle, &jrp_reg); | |
506 | if (has_jrp) | |
507 | seen_terminating_bundle = true; | |
508 | ||
509 | if (location->pc_location == PC_LOC_UNKNOWN) { | |
510 | if (has_jrp) { | |
511 | if (jrp_reg == TREG_LR && !lr_modified) { | |
512 | /* Looks like a leaf function, or else | |
513 | * lr is already restored. */ | |
514 | location->pc_location = | |
515 | PC_LOC_IN_LR; | |
516 | } else { | |
517 | location->pc_location = | |
518 | PC_LOC_ON_STACK; | |
519 | } | |
520 | } else if (bt_has_sw_sp_lr(&bundle)) { | |
521 | /* In prolog, spilling initial lr to stack. */ | |
522 | location->pc_location = PC_LOC_IN_LR; | |
523 | } else if (bt_modifies_lr(&bundle)) { | |
524 | lr_modified = true; | |
525 | } | |
526 | } | |
527 | } | |
528 | } | |
529 | ||
93013a0f CM |
530 | /* Initializes a backtracer to start from the given location. |
531 | * | |
532 | * If the frame pointer cannot be determined it is set to -1. | |
533 | * | |
534 | * state: The state to be filled in. | |
535 | * read_memory_func: A callback that reads memory. | |
536 | * read_memory_func_extra: An arbitrary argument to read_memory_func. | |
537 | * pc: The current PC. | |
538 | * lr: The current value of the 'lr' register. | |
539 | * sp: The current value of the 'sp' register. | |
540 | * r52: The current value of the 'r52' register. | |
541 | */ | |
0707ad30 CM |
542 | void backtrace_init(BacktraceIterator *state, |
543 | BacktraceMemoryReader read_memory_func, | |
544 | void *read_memory_func_extra, | |
93013a0f CM |
545 | unsigned long pc, unsigned long lr, |
546 | unsigned long sp, unsigned long r52) | |
867e359b CM |
547 | { |
548 | CallerLocation location; | |
93013a0f | 549 | unsigned long fp, initial_frame_caller_pc; |
867e359b CM |
550 | |
551 | /* Find out where we are in the initial frame. */ | |
552 | find_caller_pc_and_caller_sp(&location, pc, | |
553 | read_memory_func, read_memory_func_extra); | |
554 | ||
555 | switch (location.sp_location) { | |
556 | case SP_LOC_UNKNOWN: | |
557 | /* Give up. */ | |
558 | fp = -1; | |
559 | break; | |
560 | ||
561 | case SP_LOC_IN_R52: | |
562 | fp = r52; | |
563 | break; | |
564 | ||
565 | case SP_LOC_OFFSET: | |
566 | fp = sp + location.sp_offset; | |
567 | break; | |
568 | ||
569 | default: | |
570 | /* Give up. */ | |
571 | fp = -1; | |
572 | break; | |
573 | } | |
574 | ||
1fcbe027 CM |
575 | /* If the frame pointer is not aligned to the basic word size |
576 | * something terrible happened and we should mark it as invalid. | |
867e359b | 577 | */ |
1fcbe027 | 578 | if (fp % sizeof(bt_int_reg_t) != 0) |
867e359b CM |
579 | fp = -1; |
580 | ||
581 | /* -1 means "don't know initial_frame_caller_pc". */ | |
582 | initial_frame_caller_pc = -1; | |
583 | ||
584 | switch (location.pc_location) { | |
585 | case PC_LOC_UNKNOWN: | |
586 | /* Give up. */ | |
587 | fp = -1; | |
588 | break; | |
589 | ||
590 | case PC_LOC_IN_LR: | |
591 | if (lr == 0 || lr % TILE_BUNDLE_ALIGNMENT_IN_BYTES != 0) { | |
592 | /* Give up. */ | |
593 | fp = -1; | |
594 | } else { | |
595 | initial_frame_caller_pc = lr; | |
596 | } | |
597 | break; | |
598 | ||
599 | case PC_LOC_ON_STACK: | |
600 | /* Leave initial_frame_caller_pc as -1, | |
601 | * meaning check the stack. | |
602 | */ | |
603 | break; | |
604 | ||
605 | default: | |
606 | /* Give up. */ | |
607 | fp = -1; | |
608 | break; | |
609 | } | |
610 | ||
611 | state->pc = pc; | |
612 | state->sp = sp; | |
613 | state->fp = fp; | |
614 | state->initial_frame_caller_pc = initial_frame_caller_pc; | |
615 | state->read_memory_func = read_memory_func; | |
616 | state->read_memory_func_extra = read_memory_func_extra; | |
617 | } | |
618 | ||
1fcbe027 CM |
619 | /* Handle the case where the register holds more bits than the VA. */ |
620 | static bool valid_addr_reg(bt_int_reg_t reg) | |
621 | { | |
93013a0f | 622 | return ((unsigned long)reg == reg); |
1fcbe027 CM |
623 | } |
624 | ||
93013a0f CM |
625 | /* Advances the backtracing state to the calling frame, returning |
626 | * true iff successful. | |
627 | */ | |
0707ad30 | 628 | bool backtrace_next(BacktraceIterator *state) |
867e359b | 629 | { |
93013a0f | 630 | unsigned long next_fp, next_pc; |
1fcbe027 | 631 | bt_int_reg_t next_frame[2]; |
867e359b CM |
632 | |
633 | if (state->fp == -1) { | |
634 | /* No parent frame. */ | |
635 | return false; | |
636 | } | |
637 | ||
638 | /* Try to read the frame linkage data chaining to the next function. */ | |
639 | if (!state->read_memory_func(&next_frame, state->fp, sizeof next_frame, | |
640 | state->read_memory_func_extra)) { | |
641 | return false; | |
642 | } | |
643 | ||
644 | next_fp = next_frame[1]; | |
1fcbe027 CM |
645 | if (!valid_addr_reg(next_frame[1]) || |
646 | next_fp % sizeof(bt_int_reg_t) != 0) { | |
647 | /* Caller's frame pointer is suspect, so give up. */ | |
867e359b CM |
648 | return false; |
649 | } | |
650 | ||
651 | if (state->initial_frame_caller_pc != -1) { | |
652 | /* We must be in the initial stack frame and already know the | |
653 | * caller PC. | |
654 | */ | |
655 | next_pc = state->initial_frame_caller_pc; | |
656 | ||
657 | /* Force reading stack next time, in case we were in the | |
658 | * initial frame. We don't do this above just to paranoidly | |
659 | * avoid changing the struct at all when we return false. | |
660 | */ | |
661 | state->initial_frame_caller_pc = -1; | |
662 | } else { | |
663 | /* Get the caller PC from the frame linkage area. */ | |
664 | next_pc = next_frame[0]; | |
1fcbe027 | 665 | if (!valid_addr_reg(next_frame[0]) || next_pc == 0 || |
867e359b CM |
666 | next_pc % TILE_BUNDLE_ALIGNMENT_IN_BYTES != 0) { |
667 | /* The PC is suspect, so give up. */ | |
668 | return false; | |
669 | } | |
670 | } | |
671 | ||
672 | /* Update state to become the caller's stack frame. */ | |
673 | state->pc = next_pc; | |
674 | state->sp = state->fp; | |
675 | state->fp = next_fp; | |
676 | ||
677 | return true; | |
678 | } |