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867e359b CM |
1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/seq_file.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel_stat.h> | |
20 | #include <linux/uaccess.h> | |
21 | #include <hv/drv_pcie_rc_intf.h> | |
fb702b94 CM |
22 | #include <arch/spr_def.h> |
23 | #include <asm/traps.h> | |
24 | ||
25 | /* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */ | |
26 | #define IS_HW_CLEARED 1 | |
867e359b CM |
27 | |
28 | /* | |
5d966115 | 29 | * The set of interrupts we enable for arch_local_irq_enable(). |
867e359b CM |
30 | * This is initialized to have just a single interrupt that the kernel |
31 | * doesn't actually use as a sentinel. During kernel init, | |
32 | * interrupts are added as the kernel gets prepared to support them. | |
33 | * NOTE: we could probably initialize them all statically up front. | |
34 | */ | |
35 | DEFINE_PER_CPU(unsigned long long, interrupts_enabled_mask) = | |
36 | INITIAL_INTERRUPTS_ENABLED; | |
37 | EXPORT_PER_CPU_SYMBOL(interrupts_enabled_mask); | |
38 | ||
fb702b94 | 39 | /* Define per-tile device interrupt statistics state. */ |
867e359b CM |
40 | DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp; |
41 | EXPORT_PER_CPU_SYMBOL(irq_stat); | |
42 | ||
fb702b94 CM |
43 | /* |
44 | * Define per-tile irq disable mask; the hardware/HV only has a single | |
45 | * mask that we use to implement both masking and disabling. | |
46 | */ | |
47 | static DEFINE_PER_CPU(unsigned long, irq_disable_mask) | |
48 | ____cacheline_internodealigned_in_smp; | |
49 | ||
50 | /* | |
51 | * Per-tile IRQ nesting depth. Used to make sure we enable newly | |
52 | * enabled IRQs before exiting the outermost interrupt. | |
53 | */ | |
54 | static DEFINE_PER_CPU(int, irq_depth); | |
55 | ||
56 | /* State for allocating IRQs on Gx. */ | |
57 | #if CHIP_HAS_IPI() | |
8d8cf067 CM |
58 | static unsigned long available_irqs = ((1UL << NR_IRQS) - 1) & |
59 | (~(1UL << IRQ_RESCHEDULE)); | |
fb702b94 CM |
60 | static DEFINE_SPINLOCK(available_irqs_lock); |
61 | #endif | |
867e359b | 62 | |
fb702b94 CM |
63 | #if CHIP_HAS_IPI() |
64 | /* Use SPRs to manipulate device interrupts. */ | |
a78c942d CM |
65 | #define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask) |
66 | #define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask) | |
67 | #define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask) | |
fb702b94 CM |
68 | #else |
69 | /* Use HV to manipulate device interrupts. */ | |
70 | #define mask_irqs(irq_mask) hv_disable_intr(irq_mask) | |
71 | #define unmask_irqs(irq_mask) hv_enable_intr(irq_mask) | |
72 | #define clear_irqs(irq_mask) hv_clear_intr(irq_mask) | |
73 | #endif | |
867e359b CM |
74 | |
75 | /* | |
fb702b94 | 76 | * The interrupt handling path, implemented in terms of HV interrupt |
d7c96611 | 77 | * emulation on TILEPro, and IPI hardware on TILE-Gx. |
bc1a298f | 78 | * Entered with interrupts disabled. |
867e359b CM |
79 | */ |
80 | void tile_dev_intr(struct pt_regs *regs, int intnum) | |
81 | { | |
fb702b94 CM |
82 | int depth = __get_cpu_var(irq_depth)++; |
83 | unsigned long original_irqs; | |
84 | unsigned long remaining_irqs; | |
85 | struct pt_regs *old_regs; | |
867e359b | 86 | |
fb702b94 | 87 | #if CHIP_HAS_IPI() |
867e359b | 88 | /* |
fb702b94 CM |
89 | * Pending interrupts are listed in an SPR. We might be |
90 | * nested, so be sure to only handle irqs that weren't already | |
91 | * masked by a previous interrupt. Then, mask out the ones | |
92 | * we're going to handle. | |
867e359b | 93 | */ |
a78c942d CM |
94 | unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K); |
95 | original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked; | |
96 | __insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs); | |
fb702b94 CM |
97 | #else |
98 | /* | |
99 | * Hypervisor performs the equivalent of the Gx code above and | |
100 | * then puts the pending interrupt mask into a system save reg | |
101 | * for us to find. | |
102 | */ | |
a78c942d | 103 | original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3); |
fb702b94 CM |
104 | #endif |
105 | remaining_irqs = original_irqs; | |
867e359b CM |
106 | |
107 | /* Track time spent here in an interrupt context. */ | |
fb702b94 | 108 | old_regs = set_irq_regs(regs); |
867e359b CM |
109 | irq_enter(); |
110 | ||
111 | #ifdef CONFIG_DEBUG_STACKOVERFLOW | |
112 | /* Debugging check for stack overflow: less than 1/8th stack free? */ | |
113 | { | |
114 | long sp = stack_pointer - (long) current_thread_info(); | |
115 | if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { | |
fb702b94 | 116 | pr_emerg("tile_dev_intr: " |
867e359b CM |
117 | "stack overflow: %ld\n", |
118 | sp - sizeof(struct thread_info)); | |
119 | dump_stack(); | |
120 | } | |
121 | } | |
122 | #endif | |
fb702b94 CM |
123 | while (remaining_irqs) { |
124 | unsigned long irq = __ffs(remaining_irqs); | |
125 | remaining_irqs &= ~(1UL << irq); | |
867e359b | 126 | |
fb702b94 CM |
127 | /* Count device irqs; Linux IPIs are counted elsewhere. */ |
128 | if (irq != IRQ_RESCHEDULE) | |
129 | __get_cpu_var(irq_stat).irq_dev_intr_count++; | |
867e359b | 130 | |
fb702b94 | 131 | generic_handle_irq(irq); |
867e359b CM |
132 | } |
133 | ||
fb702b94 CM |
134 | /* |
135 | * If we weren't nested, turn on all enabled interrupts, | |
136 | * including any that were reenabled during interrupt | |
137 | * handling. | |
138 | */ | |
139 | if (depth == 0) | |
140 | unmask_irqs(~__get_cpu_var(irq_disable_mask)); | |
141 | ||
142 | __get_cpu_var(irq_depth)--; | |
143 | ||
867e359b CM |
144 | /* |
145 | * Track time spent against the current process again and | |
146 | * process any softirqs if they are waiting. | |
147 | */ | |
148 | irq_exit(); | |
149 | set_irq_regs(old_regs); | |
150 | } | |
151 | ||
152 | ||
fb702b94 CM |
153 | /* |
154 | * Remove an irq from the disabled mask. If we're in an interrupt | |
155 | * context, defer enabling the HW interrupt until we leave. | |
156 | */ | |
0c90547b | 157 | static void tile_irq_chip_enable(struct irq_data *d) |
fb702b94 | 158 | { |
0c90547b | 159 | get_cpu_var(irq_disable_mask) &= ~(1UL << d->irq); |
fb702b94 | 160 | if (__get_cpu_var(irq_depth) == 0) |
0c90547b | 161 | unmask_irqs(1UL << d->irq); |
fb702b94 CM |
162 | put_cpu_var(irq_disable_mask); |
163 | } | |
fb702b94 CM |
164 | |
165 | /* | |
166 | * Add an irq to the disabled mask. We disable the HW interrupt | |
167 | * immediately so that there's no possibility of it firing. If we're | |
168 | * in an interrupt context, the return path is careful to avoid | |
169 | * unmasking a newly disabled interrupt. | |
170 | */ | |
0c90547b | 171 | static void tile_irq_chip_disable(struct irq_data *d) |
fb702b94 | 172 | { |
0c90547b CM |
173 | get_cpu_var(irq_disable_mask) |= (1UL << d->irq); |
174 | mask_irqs(1UL << d->irq); | |
fb702b94 CM |
175 | put_cpu_var(irq_disable_mask); |
176 | } | |
fb702b94 | 177 | |
867e359b | 178 | /* Mask an interrupt. */ |
f5b42c93 | 179 | static void tile_irq_chip_mask(struct irq_data *d) |
867e359b | 180 | { |
f5b42c93 | 181 | mask_irqs(1UL << d->irq); |
867e359b CM |
182 | } |
183 | ||
184 | /* Unmask an interrupt. */ | |
f5b42c93 | 185 | static void tile_irq_chip_unmask(struct irq_data *d) |
867e359b | 186 | { |
f5b42c93 | 187 | unmask_irqs(1UL << d->irq); |
867e359b CM |
188 | } |
189 | ||
190 | /* | |
fb702b94 CM |
191 | * Clear an interrupt before processing it so that any new assertions |
192 | * will trigger another irq. | |
867e359b | 193 | */ |
f5b42c93 | 194 | static void tile_irq_chip_ack(struct irq_data *d) |
867e359b | 195 | { |
f5b42c93 TG |
196 | if ((unsigned long)irq_data_get_irq_chip_data(d) != IS_HW_CLEARED) |
197 | clear_irqs(1UL << d->irq); | |
867e359b CM |
198 | } |
199 | ||
200 | /* | |
fb702b94 CM |
201 | * For per-cpu interrupts, we need to avoid unmasking any interrupts |
202 | * that we disabled via disable_percpu_irq(). | |
867e359b | 203 | */ |
f5b42c93 | 204 | static void tile_irq_chip_eoi(struct irq_data *d) |
867e359b | 205 | { |
f5b42c93 TG |
206 | if (!(__get_cpu_var(irq_disable_mask) & (1UL << d->irq))) |
207 | unmask_irqs(1UL << d->irq); | |
867e359b CM |
208 | } |
209 | ||
fb702b94 | 210 | static struct irq_chip tile_irq_chip = { |
d1ea13c6 | 211 | .name = "tile_irq_chip", |
0c90547b CM |
212 | .irq_enable = tile_irq_chip_enable, |
213 | .irq_disable = tile_irq_chip_disable, | |
f5b42c93 TG |
214 | .irq_ack = tile_irq_chip_ack, |
215 | .irq_eoi = tile_irq_chip_eoi, | |
216 | .irq_mask = tile_irq_chip_mask, | |
217 | .irq_unmask = tile_irq_chip_unmask, | |
867e359b CM |
218 | }; |
219 | ||
220 | void __init init_IRQ(void) | |
221 | { | |
fb702b94 | 222 | ipi_init(); |
867e359b CM |
223 | } |
224 | ||
18f894c1 | 225 | void setup_irq_regs(void) |
867e359b | 226 | { |
fb702b94 CM |
227 | /* Enable interrupt delivery. */ |
228 | unmask_irqs(~0UL); | |
229 | #if CHIP_HAS_IPI() | |
5d966115 | 230 | arch_local_irq_unmask(INT_IPI_K); |
fb702b94 | 231 | #endif |
867e359b CM |
232 | } |
233 | ||
fb702b94 | 234 | void tile_irq_activate(unsigned int irq, int tile_irq_type) |
867e359b CM |
235 | { |
236 | /* | |
fb702b94 | 237 | * We use handle_level_irq() by default because the pending |
d7c96611 | 238 | * interrupt vector (whether modeled by the HV on |
fb702b94 CM |
239 | * TILEPro or implemented in hardware on TILE-Gx) has |
240 | * level-style semantics for each bit. An interrupt fires | |
241 | * whenever a bit is high, not just at edges. | |
242 | */ | |
243 | irq_flow_handler_t handle = handle_level_irq; | |
244 | if (tile_irq_type == TILE_IRQ_PERCPU) | |
245 | handle = handle_percpu_irq; | |
1919d641 | 246 | irq_set_chip_and_handler(irq, &tile_irq_chip, handle); |
fb702b94 CM |
247 | |
248 | /* | |
249 | * Flag interrupts that are hardware-cleared so that ack() | |
250 | * won't clear them. | |
867e359b | 251 | */ |
fb702b94 | 252 | if (tile_irq_type == TILE_IRQ_HW_CLEAR) |
1919d641 | 253 | irq_set_chip_data(irq, (void *)IS_HW_CLEARED); |
867e359b | 254 | } |
fb702b94 CM |
255 | EXPORT_SYMBOL(tile_irq_activate); |
256 | ||
867e359b CM |
257 | |
258 | void ack_bad_irq(unsigned int irq) | |
259 | { | |
fb702b94 | 260 | pr_err("unexpected IRQ trap at vector %02x\n", irq); |
867e359b CM |
261 | } |
262 | ||
263 | /* | |
264 | * Generic, controller-independent functions: | |
265 | */ | |
266 | ||
fb702b94 CM |
267 | #if CHIP_HAS_IPI() |
268 | int create_irq(void) | |
269 | { | |
270 | unsigned long flags; | |
271 | int result; | |
272 | ||
273 | spin_lock_irqsave(&available_irqs_lock, flags); | |
274 | if (available_irqs == 0) | |
275 | result = -ENOMEM; | |
276 | else { | |
277 | result = __ffs(available_irqs); | |
278 | available_irqs &= ~(1UL << result); | |
279 | dynamic_irq_init(result); | |
280 | } | |
281 | spin_unlock_irqrestore(&available_irqs_lock, flags); | |
282 | ||
283 | return result; | |
284 | } | |
285 | EXPORT_SYMBOL(create_irq); | |
286 | ||
287 | void destroy_irq(unsigned int irq) | |
288 | { | |
289 | unsigned long flags; | |
290 | ||
291 | spin_lock_irqsave(&available_irqs_lock, flags); | |
292 | available_irqs |= (1UL << irq); | |
293 | dynamic_irq_cleanup(irq); | |
294 | spin_unlock_irqrestore(&available_irqs_lock, flags); | |
295 | } | |
296 | EXPORT_SYMBOL(destroy_irq); | |
297 | #endif |