[mirror_ubuntu-bionic-kernel.git] / arch / tile / kernel / pci.c

/*
 * Copyright 2011 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/capability.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/export.h>

#include <asm/processor.h>
#include <asm/sections.h>
#include <asm/byteorder.h>
#include <asm/hv_driver.h>
#include <hv/drv_pcie_rc_intf.h>


/*
 * Initialization flow and process
 * -------------------------------
 *
 * This files contains the routines to search for PCI buses,
 * enumerate the buses, and configure any attached devices.
 *
 * There are two entry points here:
 * 1) tile_pci_init
 *    This sets up the pci_controller structs, and opens the
 *    FDs to the hypervisor.  This is called from setup_arch() early
 *    in the boot process.
 * 2) pcibios_init
 *    This probes the PCI bus(es) for any attached hardware.  It's
 *    called by subsys_initcall.  All of the real work is done by the
 *    generic Linux PCI layer.
 *
 */

static int pci_probe = 1;

/*
 * This flag tells if the platform is TILEmpower that needs
 * special configuration for the PLX switch chip.
 */
int __write_once tile_plx_gen1;

static struct pci_controller controllers[TILE_NUM_PCIE];
static int num_controllers;
static int pci_scan_flags[TILE_NUM_PCIE];

static struct pci_ops tile_cfg_ops;


/*
 * We don't need to worry about the alignment of resources.
 */
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
			    resource_size_t size, resource_size_t align)
{
	return res->start;
}
EXPORT_SYMBOL(pcibios_align_resource);

/*
 * Open a FD to the hypervisor PCI device.
 *
 * controller_id is the controller number, config type is 0 or 1 for
 * config0 or config1 operations.
 */
static int tile_pcie_open(int controller_id, int config_type)
{
	char filename[32];
	int fd;

	sprintf(filename, "pcie/%d/config%d", controller_id, config_type);

	fd = hv_dev_open((HV_VirtAddr)filename, 0);

	return fd;
}


/*
 * Get the IRQ numbers from the HV and set up the handlers for them.
 */
static int tile_init_irqs(int controller_id, struct pci_controller *controller)
{
	char filename[32];
	int fd;
	int ret;
	int x;
	struct pcie_rc_config rc_config;

	sprintf(filename, "pcie/%d/ctl", controller_id);
	fd = hv_dev_open((HV_VirtAddr)filename, 0);
	if (fd < 0) {
		pr_err("PCI: hv_dev_open(%s) failed\n", filename);
		return -1;
	}
	ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
			   sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
	hv_dev_close(fd);
	if (ret != sizeof(rc_config)) {
		pr_err("PCI: wanted %zd bytes, got %d\n",
		       sizeof(rc_config), ret);
		return -1;
	}
	/* Record irq_base so that we can map INTx to IRQ # later. */
	controller->irq_base = rc_config.intr;

	for (x = 0; x < 4; x++)
		tile_irq_activate(rc_config.intr + x,
				  TILE_IRQ_HW_CLEAR);

	if (rc_config.plx_gen1)
		controller->plx_gen1 = 1;

	return 0;
}

/*
 * First initialization entry point, called from setup_arch().
 *
 * Find valid controllers and fill in pci_controller structs for each
 * of them.
 *
 * Returns the number of controllers discovered.
 */
int __init tile_pci_init(void)
{
	int i;

	if (!pci_probe) {
		pr_info("PCI: disabled by boot argument\n");
		return 0;
	}

	pr_info("PCI: Searching for controllers...\n");

	/* Re-init number of PCIe controllers to support hot-plug feature. */
	num_controllers = 0;

	/* Do any configuration we need before using the PCIe */

	for (i = 0; i < TILE_NUM_PCIE; i++) {
		/*
		 * To see whether we need a real config op based on
		 * the results of pcibios_init(), to support PCIe hot-plug.
		 */
		if (pci_scan_flags[i] == 0) {
			int hv_cfg_fd0 = -1;
			int hv_cfg_fd1 = -1;
			int hv_mem_fd = -1;
			char name[32];
			struct pci_controller *controller;

			/*
			 * Open the fd to the HV.  If it fails then this
			 * device doesn't exist.
			 */
			hv_cfg_fd0 = tile_pcie_open(i, 0);
			if (hv_cfg_fd0 < 0)
				continue;
			hv_cfg_fd1 = tile_pcie_open(i, 1);
			if (hv_cfg_fd1 < 0) {
				pr_err("PCI: Couldn't open config fd to HV for controller %d\n",
				       i);
				goto err_cont;
			}

			sprintf(name, "pcie/%d/mem", i);
			hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
			if (hv_mem_fd < 0) {
				pr_err("PCI: Could not open mem fd to HV!\n");
				goto err_cont;
			}

			pr_info("PCI: Found PCI controller #%d\n", i);

			controller = &controllers[i];

			controller->index = i;
			controller->hv_cfg_fd[0] = hv_cfg_fd0;
			controller->hv_cfg_fd[1] = hv_cfg_fd1;
			controller->hv_mem_fd = hv_mem_fd;
			controller->last_busno = 0xff;
			controller->ops = &tile_cfg_ops;

			num_controllers++;
			continue;

err_cont:
			if (hv_cfg_fd0 >= 0)
				hv_dev_close(hv_cfg_fd0);
			if (hv_cfg_fd1 >= 0)
				hv_dev_close(hv_cfg_fd1);
			if (hv_mem_fd >= 0)
				hv_dev_close(hv_mem_fd);
			continue;
		}
	}

	/*
	 * Before using the PCIe, see if we need to do any platform-specific
	 * configuration, such as the PLX switch Gen 1 issue on TILEmpower.
	 */
	for (i = 0; i < num_controllers; i++) {
		struct pci_controller *controller = &controllers[i];

		if (controller->plx_gen1)
			tile_plx_gen1 = 1;
	}

	return num_controllers;
}

/*
 * (pin - 1) converts from the PCI standard's [1:4] convention to
 * a normal [0:3] range.
 */
static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_controller *controller =
		(struct pci_controller *)dev->sysdata;
	return (pin - 1) + controller->irq_base;
}


static void fixup_read_and_payload_sizes(void)
{
	struct pci_dev *dev = NULL;
	int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
	int max_read_size = 0x2; /* Limit to 512 byte reads. */
	u16 new_values;

	/* Scan for the smallest maximum payload size. */
	for_each_pci_dev(dev) {
		if (!pci_is_pcie(dev))
			continue;

		if (dev->pcie_mpss < smallest_max_payload)
			smallest_max_payload = dev->pcie_mpss;
	}

	/* Now, set the max_payload_size for all devices to that value. */
	new_values = (max_read_size << 12) | (smallest_max_payload << 5);
	for_each_pci_dev(dev)
		pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
				PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
				new_values);
}


/*
 * Second PCI initialization entry point, called by subsys_initcall.
 *
 * The controllers have been set up by the time we get here, by a call to
 * tile_pci_init.
 */
int __init pcibios_init(void)
{
	int i;

	pr_info("PCI: Probing PCI hardware\n");

	/*
	 * Delay a bit in case devices aren't ready.  Some devices are
	 * known to require at least 20ms here, but we use a more
	 * conservative value.
	 */
	msleep(250);

	/* Scan all of the recorded PCI controllers.  */
	for (i = 0; i < TILE_NUM_PCIE; i++) {
		/*
		 * Do real pcibios init ops if the controller is initialized
		 * by tile_pci_init() successfully and not initialized by
		 * pcibios_init() yet to support PCIe hot-plug.
		 */
		if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
			struct pci_controller *controller = &controllers[i];
			struct pci_bus *bus;
			LIST_HEAD(resources);

			if (tile_init_irqs(i, controller)) {
				pr_err("PCI: Could not initialize IRQs\n");
				continue;
			}

			pr_info("PCI: initializing controller #%d\n", i);

			pci_add_resource(&resources, &ioport_resource);
			pci_add_resource(&resources, &iomem_resource);
			bus = pci_scan_root_bus(NULL, 0, controller->ops,
						controller, &resources);
			controller->root_bus = bus;
			controller->last_busno = bus->busn_res.end;
		}
	}

	/* Do machine dependent PCI interrupt routing */
	pci_fixup_irqs(pci_common_swizzle, tile_map_irq);

	/*
	 * This comes from the generic Linux PCI driver.
	 *
	 * It allocates all of the resources (I/O memory, etc)
	 * associated with the devices read in above.
	 */
	pci_assign_unassigned_resources();

	/* Configure the max_read_size and max_payload_size values. */
	fixup_read_and_payload_sizes();

	/* Record the I/O resources in the PCI controller structure. */
	for (i = 0; i < TILE_NUM_PCIE; i++) {
		/*
		 * Do real pcibios init ops if the controller is initialized
		 * by tile_pci_init() successfully and not initialized by
		 * pcibios_init() yet to support PCIe hot-plug.
		 */
		if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
			struct pci_bus *root_bus = controllers[i].root_bus;
			struct pci_bus *next_bus;
			struct pci_dev *dev;

			list_for_each_entry(dev, &root_bus->devices, bus_list) {
				/*
				 * Find the PCI host controller, ie. the 1st
				 * bridge.
				 */
				if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
					(PCI_SLOT(dev->devfn) == 0)) {
					next_bus = dev->subordinate;
					controllers[i].mem_resources[0] =
						*next_bus->resource[0];
					controllers[i].mem_resources[1] =
						 *next_bus->resource[1];
					controllers[i].mem_resources[2] =
						 *next_bus->resource[2];

					/* Setup flags. */
					pci_scan_flags[i] = 1;

					break;
				}
			}
		}
	}

	return 0;
}
subsys_initcall(pcibios_init);

/*
 * No bus fixups needed.
 */
void pcibios_fixup_bus(struct pci_bus *bus)
{
	/* Nothing needs to be done. */
}

void pcibios_set_master(struct pci_dev *dev)
{
	/* No special bus mastering setup handling. */
}

/* Process any "pci=" kernel boot arguments. */
char *__init pcibios_setup(char *str)
{
	if (!strcmp(str, "off")) {
		pci_probe = 0;
		return NULL;
	}
	return str;
}

/*
 * Enable memory and/or address decoding, as appropriate, for the
 * device described by the 'dev' struct.
 *
 * This is called from the generic PCI layer, and can be called
 * for bridges or endpoints.
 */
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	u8 header_type;
	int i;
	struct resource *r;

	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
		/*
		 * For bridges, we enable both memory and I/O decoding
		 * in call cases.
		 */
		cmd |= PCI_COMMAND_IO;
		cmd |= PCI_COMMAND_MEMORY;
	} else {
		/*
		 * For endpoints, we enable memory and/or I/O decoding
		 * only if they have a memory resource of that type.
		 */
		for (i = 0; i < 6; i++) {
			r = &dev->resource[i];
			if (r->flags & IORESOURCE_UNSET) {
				pr_err("PCI: Device %s not available because of resource collisions\n",
				       pci_name(dev));
				return -EINVAL;
			}
			if (r->flags & IORESOURCE_IO)
				cmd |= PCI_COMMAND_IO;
			if (r->flags & IORESOURCE_MEM)
				cmd |= PCI_COMMAND_MEMORY;
		}
	}

	/*
	 * We only write the command if it changed.
	 */
	if (cmd != old_cmd)
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	return 0;
}

/****************************************************************
 *
 * Tile PCI config space read/write routines
 *
 ****************************************************************/

/*
 * These are the normal read and write ops
 * These are expanded with macros from  pci_bus_read_config_byte() etc.
 *
 * devfn is the combined PCI slot & function.
 *
 * offset is in bytes, from the start of config space for the
 * specified bus & slot.
 */

static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
			 int size, u32 *val)
{
	struct pci_controller *controller = bus->sysdata;
	int busnum = bus->number & 0xff;
	int slot = (devfn >> 3) & 0x1f;
	int function = devfn & 0x7;
	u32 addr;
	int config_mode = 1;

	/*
	 * There is no bridge between the Tile and bus 0, so we
	 * use config0 to talk to bus 0.
	 *
	 * If we're talking to a bus other than zero then we
	 * must have found a bridge.
	 */
	if (busnum == 0) {
		/*
		 * We fake an empty slot for (busnum == 0) && (slot > 0),
		 * since there is only one slot on bus 0.
		 */
		if (slot) {
			*val = 0xFFFFFFFF;
			return 0;
		}
		config_mode = 0;
	}

	addr = busnum << 20;		/* Bus in 27:20 */
	addr |= slot << 15;		/* Slot (device) in 19:15 */
	addr |= function << 12;		/* Function is in 14:12 */
	addr |= (offset & 0xFFF);	/* byte address in 0:11 */

	return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
			    (HV_VirtAddr)(val), size, addr);
}


/*
 * See tile_cfg_read() for relevant comments.
 * Note that "val" is the value to write, not a pointer to that value.
 */
static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
			  int size, u32 val)
{
	struct pci_controller *controller = bus->sysdata;
	int busnum = bus->number & 0xff;
	int slot = (devfn >> 3) & 0x1f;
	int function = devfn & 0x7;
	u32 addr;
	int config_mode = 1;
	HV_VirtAddr valp = (HV_VirtAddr)&val;

	/*
	 * For bus 0 slot 0 we use config 0 accesses.
	 */
	if (busnum == 0) {
		/*
		 * We fake an empty slot for (busnum == 0) && (slot > 0),
		 * since there is only one slot on bus 0.
		 */
		if (slot)
			return 0;
		config_mode = 0;
	}

	addr = busnum << 20;		/* Bus in 27:20 */
	addr |= slot << 15;		/* Slot (device) in 19:15 */
	addr |= function << 12;		/* Function is in 14:12 */
	addr |= (offset & 0xFFF);	/* byte address in 0:11 */

#ifdef __BIG_ENDIAN
	/* Point to the correct part of the 32-bit "val". */
	valp += 4 - size;
#endif

	return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
			     valp, size, addr);
}


static struct pci_ops tile_cfg_ops = {
	.read =         tile_cfg_read,
	.write =        tile_cfg_write,
};


/*
 * In the following, each PCI controller's mem_resources[1]
 * represents its (non-prefetchable) PCI memory resource.
 * mem_resources[0] and mem_resources[2] refer to its PCI I/O and
 * prefetchable PCI memory resources, respectively.
 * For more details, see pci_setup_bridge() in setup-bus.c.
 * By comparing the target PCI memory address against the
 * end address of controller 0, we can determine the controller
 * that should accept the PCI memory access.
 */
#define TILE_READ(size, type)						\
type _tile_read##size(unsigned long addr)				\
{									\
	type val;							\
	int idx = 0;							\
	if (addr > controllers[0].mem_resources[1].end &&		\
	    addr > controllers[0].mem_resources[2].end)			\
		idx = 1;                                                \
	if (hv_dev_pread(controllers[idx].hv_mem_fd, 0,			\
			 (HV_VirtAddr)(&val), sizeof(type), addr))	\
		pr_err("PCI: read %zd bytes at 0x%lX failed\n",		\
		       sizeof(type), addr);				\
	return val;							\
}									\
EXPORT_SYMBOL(_tile_read##size)

TILE_READ(b, u8);
TILE_READ(w, u16);
TILE_READ(l, u32);
TILE_READ(q, u64);

#define TILE_WRITE(size, type)						\
void _tile_write##size(type val, unsigned long addr)			\
{									\
	int idx = 0;							\
	if (addr > controllers[0].mem_resources[1].end &&		\
	    addr > controllers[0].mem_resources[2].end)			\
		idx = 1;                                                \
	if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0,		\
			  (HV_VirtAddr)(&val), sizeof(type), addr))	\
		pr_err("PCI: write %zd bytes at 0x%lX failed\n",	\
		       sizeof(type), addr);				\
}									\
EXPORT_SYMBOL(_tile_write##size)

TILE_WRITE(b, u8);
TILE_WRITE(w, u16);
TILE_WRITE(l, u32);
TILE_WRITE(q, u64);
Commit	Line	Data
f02cbbe6	1	/*
398fa5a9	2	* Copyright 2011 Tilera Corporation. All Rights Reserved.
f02cbbe6 CM	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/pci.h>
	17	#include <linux/delay.h>
	18	#include <linux/string.h>
	19	#include <linux/init.h>
	20	#include <linux/capability.h>
	21	#include <linux/sched.h>
	22	#include <linux/errno.h>
f02cbbe6 CM	23	#include <linux/irq.h>
	24	#include <linux/io.h>
	25	#include <linux/uaccess.h>
3989efb7	26	#include <linux/export.h>
f02cbbe6 CM	27
	28	#include <asm/processor.h>
	29	#include <asm/sections.h>
	30	#include <asm/byteorder.h>
	31	#include <asm/hv_driver.h>
	32	#include <hv/drv_pcie_rc_intf.h>
	33
	34
	35	/*
	36	* Initialization flow and process
	37	* -------------------------------
	38	*
25985edc	39	* This files contains the routines to search for PCI buses,
f02cbbe6 CM	40	* enumerate the buses, and configure any attached devices.
	41	*
	42	* There are two entry points here:
	43	* 1) tile_pci_init
	44	* This sets up the pci_controller structs, and opens the
	45	* FDs to the hypervisor. This is called from setup_arch() early
	46	* in the boot process.
	47	* 2) pcibios_init
	48	* This probes the PCI bus(es) for any attached hardware. It's
	49	* called by subsys_initcall. All of the real work is done by the
	50	* generic Linux PCI layer.
	51	*
	52	*/
	53
2be70552 CM	54	static int pci_probe = 1;
2be70552 CM	55
f02cbbe6 CM	56	/*
	57	* This flag tells if the platform is TILEmpower that needs
	58	* special configuration for the PLX switch chip.
	59	*/
	60	int __write_once tile_plx_gen1;
	61
	62	static struct pci_controller controllers[TILE_NUM_PCIE];
	63	static int num_controllers;
398fa5a9	64	static int pci_scan_flags[TILE_NUM_PCIE];
f02cbbe6 CM	65
	66	static struct pci_ops tile_cfg_ops;
	67
	68
	69	/*
	70	* We don't need to worry about the alignment of resources.
	71	*/
	72	resource_size_t pcibios_align_resource(void data, const struct resource res,
	73	resource_size_t size, resource_size_t align)
	74	{
	75	return res->start;
	76	}
	77	EXPORT_SYMBOL(pcibios_align_resource);
	78
	79	/*
	80	* Open a FD to the hypervisor PCI device.
	81	*
	82	* controller_id is the controller number, config type is 0 or 1 for
	83	* config0 or config1 operations.
	84	*/
b881bc46	85	static int tile_pcie_open(int controller_id, int config_type)
f02cbbe6 CM	86	{
	87	char filename[32];
	88	int fd;
	89
	90	sprintf(filename, "pcie/%d/config%d", controller_id, config_type);
	91
	92	fd = hv_dev_open((HV_VirtAddr)filename, 0);
	93
	94	return fd;
	95	}
	96
	97
	98	/*
	99	* Get the IRQ numbers from the HV and set up the handlers for them.
	100	*/
b881bc46	101	static int tile_init_irqs(int controller_id, struct pci_controller *controller)
f02cbbe6 CM	102	{
	103	char filename[32];
	104	int fd;
	105	int ret;
	106	int x;
	107	struct pcie_rc_config rc_config;
	108
	109	sprintf(filename, "pcie/%d/ctl", controller_id);
	110	fd = hv_dev_open((HV_VirtAddr)filename, 0);
	111	if (fd < 0) {
	112	pr_err("PCI: hv_dev_open(%s) failed\n", filename);
	113	return -1;
	114	}
	115	ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
	116	sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
	117	hv_dev_close(fd);
	118	if (ret != sizeof(rc_config)) {
	119	pr_err("PCI: wanted %zd bytes, got %d\n",
	120	sizeof(rc_config), ret);
	121	return -1;
	122	}
	123	/* Record irq_base so that we can map INTx to IRQ # later. */
	124	controller->irq_base = rc_config.intr;
	125
	126	for (x = 0; x < 4; x++)
	127	tile_irq_activate(rc_config.intr + x,
	128	TILE_IRQ_HW_CLEAR);
	129
	130	if (rc_config.plx_gen1)
	131	controller->plx_gen1 = 1;
	132
	133	return 0;
	134	}
	135
	136	/*
	137	* First initialization entry point, called from setup_arch().
	138	*
	139	* Find valid controllers and fill in pci_controller structs for each
	140	* of them.
	141	*
	142	* Returns the number of controllers discovered.
	143	*/
05ef1b79	144	int __init tile_pci_init(void)
f02cbbe6 CM	145	{
	146	int i;
	147
2be70552 CM	148	if (!pci_probe) {
	149	pr_info("PCI: disabled by boot argument\n");
	150	return 0;
	151	}
	152
f02cbbe6 CM	153	pr_info("PCI: Searching for controllers...\n");
f02cbbe6 CM	154
398fa5a9 CM	155	/* Re-init number of PCIe controllers to support hot-plug feature. */
	156	num_controllers = 0;
	157
f02cbbe6 CM	158	/* Do any configuration we need before using the PCIe */
	159
	160	for (i = 0; i < TILE_NUM_PCIE; i++) {
f02cbbe6	161	/*
398fa5a9 CM	162	* To see whether we need a real config op based on
398fa5a9 CM	163	* the results of pcibios_init(), to support PCIe hot-plug.
f02cbbe6	164	*/
398fa5a9 CM	165	if (pci_scan_flags[i] == 0) {
	166	int hv_cfg_fd0 = -1;
	167	int hv_cfg_fd1 = -1;
	168	int hv_mem_fd = -1;
	169	char name[32];
	170	struct pci_controller *controller;
	171
	172	/*
	173	* Open the fd to the HV. If it fails then this
	174	* device doesn't exist.
	175	*/
	176	hv_cfg_fd0 = tile_pcie_open(i, 0);
	177	if (hv_cfg_fd0 < 0)
	178	continue;
	179	hv_cfg_fd1 = tile_pcie_open(i, 1);
	180	if (hv_cfg_fd1 < 0) {
f4743673 JP	181	pr_err("PCI: Couldn't open config fd to HV for controller %d\n",
f4743673 JP	182	i);
398fa5a9 CM	183	goto err_cont;
398fa5a9 CM	184	}
f02cbbe6	185
398fa5a9 CM	186	sprintf(name, "pcie/%d/mem", i);
	187	hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
	188	if (hv_mem_fd < 0) {
	189	pr_err("PCI: Could not open mem fd to HV!\n");
	190	goto err_cont;
	191	}
f02cbbe6	192
398fa5a9	193	pr_info("PCI: Found PCI controller #%d\n", i);
f02cbbe6	194
398fa5a9	195	controller = &controllers[i];
f02cbbe6	196
398fa5a9 CM	197	controller->index = i;
	198	controller->hv_cfg_fd[0] = hv_cfg_fd0;
	199	controller->hv_cfg_fd[1] = hv_cfg_fd1;
	200	controller->hv_mem_fd = hv_mem_fd;
398fa5a9 CM	201	controller->last_busno = 0xff;
398fa5a9 CM	202	controller->ops = &tile_cfg_ops;
f02cbbe6	203
398fa5a9 CM	204	num_controllers++;
398fa5a9 CM	205	continue;
f02cbbe6 CM	206
f02cbbe6 CM	207	err_cont:
398fa5a9 CM	208	if (hv_cfg_fd0 >= 0)
	209	hv_dev_close(hv_cfg_fd0);
	210	if (hv_cfg_fd1 >= 0)
	211	hv_dev_close(hv_cfg_fd1);
	212	if (hv_mem_fd >= 0)
	213	hv_dev_close(hv_mem_fd);
	214	continue;
	215	}
f02cbbe6 CM	216	}
	217
	218	/*
	219	* Before using the PCIe, see if we need to do any platform-specific
	220	* configuration, such as the PLX switch Gen 1 issue on TILEmpower.
	221	*/
	222	for (i = 0; i < num_controllers; i++) {
	223	struct pci_controller *controller = &controllers[i];
	224
	225	if (controller->plx_gen1)
	226	tile_plx_gen1 = 1;
	227	}
	228
	229	return num_controllers;
	230	}
	231
	232	/*
	233	* (pin - 1) converts from the PCI standard's [1:4] convention to
	234	* a normal [0:3] range.
	235	*/
d5341942	236	static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
f02cbbe6 CM	237	{
	238	struct pci_controller *controller =
	239	(struct pci_controller *)dev->sysdata;
	240	return (pin - 1) + controller->irq_base;
	241	}
	242
	243
b881bc46	244	static void fixup_read_and_payload_sizes(void)
f02cbbe6 CM	245	{
	246	struct pci_dev *dev = NULL;
	247	int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
	248	int max_read_size = 0x2; /* Limit to 512 byte reads. */
	249	u16 new_values;
	250
	251	/* Scan for the smallest maximum payload size. */
17a26354	252	for_each_pci_dev(dev) {
424ffc94	253	if (!pci_is_pcie(dev))
f02cbbe6 CM	254	continue;
f02cbbe6 CM	255
503275bf YW	256	if (dev->pcie_mpss < smallest_max_payload)
503275bf YW	257	smallest_max_payload = dev->pcie_mpss;
f02cbbe6 CM	258	}
	259
	260	/* Now, set the max_payload_size for all devices to that value. */
	261	new_values = (max_read_size << 12) \| (smallest_max_payload << 5);
17a26354	262	for_each_pci_dev(dev)
424ffc94 JL	263	pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
	264	PCI_EXP_DEVCTL_PAYLOAD \| PCI_EXP_DEVCTL_READRQ,
	265	new_values);
f02cbbe6 CM	266	}
	267
	268
	269	/*
	270	* Second PCI initialization entry point, called by subsys_initcall.
	271	*
	272	* The controllers have been set up by the time we get here, by a call to
	273	* tile_pci_init.
	274	*/
05ef1b79	275	int __init pcibios_init(void)
f02cbbe6 CM	276	{
	277	int i;
	278
	279	pr_info("PCI: Probing PCI hardware\n");
	280
	281	/*
	282	* Delay a bit in case devices aren't ready. Some devices are
	283	* known to require at least 20ms here, but we use a more
	284	* conservative value.
	285	*/
9bbb08fa	286	msleep(250);
f02cbbe6 CM	287
f02cbbe6 CM	288	/* Scan all of the recorded PCI controllers. */
398fa5a9	289	for (i = 0; i < TILE_NUM_PCIE; i++) {
f02cbbe6	290	/*
398fa5a9 CM	291	* Do real pcibios init ops if the controller is initialized
	292	* by tile_pci_init() successfully and not initialized by
	293	* pcibios_init() yet to support PCIe hot-plug.
f02cbbe6	294	*/
398fa5a9 CM	295	if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
	296	struct pci_controller *controller = &controllers[i];
	297	struct pci_bus *bus;
b17c0e6f	298	LIST_HEAD(resources);
398fa5a9	299
f4de51de CM	300	if (tile_init_irqs(i, controller)) {
	301	pr_err("PCI: Could not initialize IRQs\n");
	302	continue;
	303	}
	304
398fa5a9 CM	305	pr_info("PCI: initializing controller #%d\n", i);
398fa5a9 CM	306
b17c0e6f YL	307	pci_add_resource(&resources, &ioport_resource);
b17c0e6f YL	308	pci_add_resource(&resources, &iomem_resource);
9bbb08fa CM	309	bus = pci_scan_root_bus(NULL, 0, controller->ops,
9bbb08fa CM	310	controller, &resources);
398fa5a9	311	controller->root_bus = bus;
b918c62e	312	controller->last_busno = bus->busn_res.end;
398fa5a9	313	}
f02cbbe6 CM	314	}
	315
	316	/* Do machine dependent PCI interrupt routing */
	317	pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
	318
	319	/*
	320	* This comes from the generic Linux PCI driver.
	321	*
	322	* It allocates all of the resources (I/O memory, etc)
	323	* associated with the devices read in above.
	324	*/
f02cbbe6 CM	325	pci_assign_unassigned_resources();
	326
	327	/* Configure the max_read_size and max_payload_size values. */
	328	fixup_read_and_payload_sizes();
	329
	330	/* Record the I/O resources in the PCI controller structure. */
398fa5a9 CM	331	for (i = 0; i < TILE_NUM_PCIE; i++) {
	332	/*
	333	* Do real pcibios init ops if the controller is initialized
	334	* by tile_pci_init() successfully and not initialized by
	335	* pcibios_init() yet to support PCIe hot-plug.
	336	*/
	337	if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
	338	struct pci_bus *root_bus = controllers[i].root_bus;
	339	struct pci_bus *next_bus;
	340	struct pci_dev *dev;
	341
	342	list_for_each_entry(dev, &root_bus->devices, bus_list) {
	343	/*
	344	* Find the PCI host controller, ie. the 1st
	345	* bridge.
	346	*/
	347	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
	348	(PCI_SLOT(dev->devfn) == 0)) {
7f240b7d	349	next_bus = dev->subordinate;
398fa5a9 CM	350	controllers[i].mem_resources[0] =
	351	*next_bus->resource[0];
	352	controllers[i].mem_resources[1] =
	353	*next_bus->resource[1];
	354	controllers[i].mem_resources[2] =
	355	*next_bus->resource[2];
	356
	357	/* Setup flags. */
	358	pci_scan_flags[i] = 1;
	359
	360	break;
	361	}
f02cbbe6 CM	362	}
f02cbbe6 CM	363	}
f02cbbe6 CM	364	}
	365
	366	return 0;
	367	}
	368	subsys_initcall(pcibios_init);
	369
	370	/*
	371	* No bus fixups needed.
	372	*/
b881bc46	373	void pcibios_fixup_bus(struct pci_bus *bus)
f02cbbe6 CM	374	{
	375	/* Nothing needs to be done. */
	376	}
	377
cf1c5230 MS	378	void pcibios_set_master(struct pci_dev *dev)
	379	{
	380	/* No special bus mastering setup handling. */
	381	}
	382
2be70552	383	/* Process any "pci=" kernel boot arguments. */
7b770a6a	384	char __init pcibios_setup(char str)
2be70552 CM	385	{
	386	if (!strcmp(str, "off")) {
	387	pci_probe = 0;
	388	return NULL;
	389	}
	390	return str;
	391	}
	392
f02cbbe6 CM	393	/*
	394	* Enable memory and/or address decoding, as appropriate, for the
	395	* device described by the 'dev' struct.
	396	*
	397	* This is called from the generic PCI layer, and can be called
	398	* for bridges or endpoints.
	399	*/
	400	int pcibios_enable_device(struct pci_dev *dev, int mask)
	401	{
	402	u16 cmd, old_cmd;
	403	u8 header_type;
	404	int i;
	405	struct resource *r;
	406
	407	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
	408
	409	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	410	old_cmd = cmd;
	411	if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
	412	/*
	413	* For bridges, we enable both memory and I/O decoding
	414	* in call cases.
	415	*/
	416	cmd \|= PCI_COMMAND_IO;
	417	cmd \|= PCI_COMMAND_MEMORY;
	418	} else {
	419	/*
	420	* For endpoints, we enable memory and/or I/O decoding
	421	* only if they have a memory resource of that type.
	422	*/
	423	for (i = 0; i < 6; i++) {
	424	r = &dev->resource[i];
	425	if (r->flags & IORESOURCE_UNSET) {
f4743673	426	pr_err("PCI: Device %s not available because of resource collisions\n",
f02cbbe6 CM	427	pci_name(dev));
	428	return -EINVAL;
	429	}
	430	if (r->flags & IORESOURCE_IO)
	431	cmd \|= PCI_COMMAND_IO;
	432	if (r->flags & IORESOURCE_MEM)
	433	cmd \|= PCI_COMMAND_MEMORY;
	434	}
	435	}
	436
	437	/*
	438	* We only write the command if it changed.
	439	*/
	440	if (cmd != old_cmd)
	441	pci_write_config_word(dev, PCI_COMMAND, cmd);
	442	return 0;
	443	}
	444
f02cbbe6 CM	445	/****************************************************************
	446	*
	447	* Tile PCI config space read/write routines
	448	*
	449	****************************************************************/
	450
	451	/*
	452	* These are the normal read and write ops
	453	* These are expanded with macros from pci_bus_read_config_byte() etc.
	454	*
	455	* devfn is the combined PCI slot & function.
	456	*
	457	* offset is in bytes, from the start of config space for the
	458	* specified bus & slot.
	459	*/
	460
b881bc46 GKH	461	static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
b881bc46 GKH	462	int size, u32 *val)
f02cbbe6 CM	463	{
	464	struct pci_controller *controller = bus->sysdata;
	465	int busnum = bus->number & 0xff;
	466	int slot = (devfn >> 3) & 0x1f;
	467	int function = devfn & 0x7;
	468	u32 addr;
	469	int config_mode = 1;
	470
	471	/*
	472	* There is no bridge between the Tile and bus 0, so we
	473	* use config0 to talk to bus 0.
	474	*
	475	* If we're talking to a bus other than zero then we
	476	* must have found a bridge.
	477	*/
	478	if (busnum == 0) {
	479	/*
	480	* We fake an empty slot for (busnum == 0) && (slot > 0),
	481	* since there is only one slot on bus 0.
	482	*/
	483	if (slot) {
	484	*val = 0xFFFFFFFF;
	485	return 0;
	486	}
	487	config_mode = 0;
	488	}
	489
	490	addr = busnum << 20; /* Bus in 27:20 */
	491	addr \|= slot << 15; /* Slot (device) in 19:15 */
	492	addr \|= function << 12; /* Function is in 14:12 */
	493	addr \|= (offset & 0xFFF); /* byte address in 0:11 */
	494
	495	return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
	496	(HV_VirtAddr)(val), size, addr);
	497	}
	498
	499
	500	/*
25985edc	501	* See tile_cfg_read() for relevant comments.
f02cbbe6 CM	502	* Note that "val" is the value to write, not a pointer to that value.
f02cbbe6 CM	503	*/
b881bc46 GKH	504	static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
b881bc46 GKH	505	int size, u32 val)
f02cbbe6 CM	506	{
	507	struct pci_controller *controller = bus->sysdata;
	508	int busnum = bus->number & 0xff;
	509	int slot = (devfn >> 3) & 0x1f;
	510	int function = devfn & 0x7;
	511	u32 addr;
	512	int config_mode = 1;
	513	HV_VirtAddr valp = (HV_VirtAddr)&val;
	514
	515	/*
	516	* For bus 0 slot 0 we use config 0 accesses.
	517	*/
	518	if (busnum == 0) {
	519	/*
	520	* We fake an empty slot for (busnum == 0) && (slot > 0),
	521	* since there is only one slot on bus 0.
	522	*/
	523	if (slot)
	524	return 0;
	525	config_mode = 0;
	526	}
	527
	528	addr = busnum << 20; /* Bus in 27:20 */
	529	addr \|= slot << 15; /* Slot (device) in 19:15 */
	530	addr \|= function << 12; /* Function is in 14:12 */
	531	addr \|= (offset & 0xFFF); /* byte address in 0:11 */
	532
	533	#ifdef __BIG_ENDIAN
	534	/* Point to the correct part of the 32-bit "val". */
	535	valp += 4 - size;
	536	#endif
	537
	538	return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
	539	valp, size, addr);
	540	}
	541
	542
	543	static struct pci_ops tile_cfg_ops = {
	544	.read = tile_cfg_read,
	545	.write = tile_cfg_write,
	546	};
	547
	548
	549	/*
	550	* In the following, each PCI controller's mem_resources[1]
	551	* represents its (non-prefetchable) PCI memory resource.
	552	* mem_resources[0] and mem_resources[2] refer to its PCI I/O and
	553	* prefetchable PCI memory resources, respectively.
	554	* For more details, see pci_setup_bridge() in setup-bus.c.
	555	* By comparing the target PCI memory address against the
	556	* end address of controller 0, we can determine the controller
	557	* that should accept the PCI memory access.
	558	*/
	559	#define TILE_READ(size, type) \
	560	type _tile_read##size(unsigned long addr) \
	561	{ \
	562	type val; \
	563	int idx = 0; \
	564	if (addr > controllers[0].mem_resources[1].end && \
	565	addr > controllers[0].mem_resources[2].end) \
	566	idx = 1; \
	567	if (hv_dev_pread(controllers[idx].hv_mem_fd, 0, \
	568	(HV_VirtAddr)(&val), sizeof(type), addr)) \
	569	pr_err("PCI: read %zd bytes at 0x%lX failed\n", \
570	sizeof(type), addr); \
571	return val; \
572	} \
573	EXPORT_SYMBOL(_tile_read##size)
574
575	TILE_READ(b, u8);
576	TILE_READ(w, u16);
577	TILE_READ(l, u32);
578	TILE_READ(q, u64);
579
580	#define TILE_WRITE(size, type) \
581	void _tile_write##size(type val, unsigned long addr) \
582	{ \
583	int idx = 0; \
584	if (addr > controllers[0].mem_resources[1].end && \
585	addr > controllers[0].mem_resources[2].end) \
586	idx = 1; \
587	if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0, \
588	(HV_VirtAddr)(&val), sizeof(type), addr)) \
589	pr_err("PCI: write %zd bytes at 0x%lX failed\n", \
590	sizeof(type), addr); \
591	} \
592	EXPORT_SYMBOL(_tile_write##size)
593
594	TILE_WRITE(b, u8);
595	TILE_WRITE(w, u16);
596	TILE_WRITE(l, u32);
597	TILE_WRITE(q, u64);