]>
Commit | Line | Data |
---|---|---|
f02cbbe6 CM |
1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/capability.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/uaccess.h> | |
27 | ||
28 | #include <asm/processor.h> | |
29 | #include <asm/sections.h> | |
30 | #include <asm/byteorder.h> | |
31 | #include <asm/hv_driver.h> | |
32 | #include <hv/drv_pcie_rc_intf.h> | |
33 | ||
34 | ||
35 | /* | |
36 | * Initialization flow and process | |
37 | * ------------------------------- | |
38 | * | |
25985edc | 39 | * This files contains the routines to search for PCI buses, |
f02cbbe6 CM |
40 | * enumerate the buses, and configure any attached devices. |
41 | * | |
42 | * There are two entry points here: | |
43 | * 1) tile_pci_init | |
44 | * This sets up the pci_controller structs, and opens the | |
45 | * FDs to the hypervisor. This is called from setup_arch() early | |
46 | * in the boot process. | |
47 | * 2) pcibios_init | |
48 | * This probes the PCI bus(es) for any attached hardware. It's | |
49 | * called by subsys_initcall. All of the real work is done by the | |
50 | * generic Linux PCI layer. | |
51 | * | |
52 | */ | |
53 | ||
54 | /* | |
55 | * This flag tells if the platform is TILEmpower that needs | |
56 | * special configuration for the PLX switch chip. | |
57 | */ | |
58 | int __write_once tile_plx_gen1; | |
59 | ||
60 | static struct pci_controller controllers[TILE_NUM_PCIE]; | |
61 | static int num_controllers; | |
62 | ||
63 | static struct pci_ops tile_cfg_ops; | |
64 | ||
65 | ||
66 | /* | |
67 | * We don't need to worry about the alignment of resources. | |
68 | */ | |
69 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, | |
70 | resource_size_t size, resource_size_t align) | |
71 | { | |
72 | return res->start; | |
73 | } | |
74 | EXPORT_SYMBOL(pcibios_align_resource); | |
75 | ||
76 | /* | |
77 | * Open a FD to the hypervisor PCI device. | |
78 | * | |
79 | * controller_id is the controller number, config type is 0 or 1 for | |
80 | * config0 or config1 operations. | |
81 | */ | |
82 | static int __init tile_pcie_open(int controller_id, int config_type) | |
83 | { | |
84 | char filename[32]; | |
85 | int fd; | |
86 | ||
87 | sprintf(filename, "pcie/%d/config%d", controller_id, config_type); | |
88 | ||
89 | fd = hv_dev_open((HV_VirtAddr)filename, 0); | |
90 | ||
91 | return fd; | |
92 | } | |
93 | ||
94 | ||
95 | /* | |
96 | * Get the IRQ numbers from the HV and set up the handlers for them. | |
97 | */ | |
98 | static int __init tile_init_irqs(int controller_id, | |
99 | struct pci_controller *controller) | |
100 | { | |
101 | char filename[32]; | |
102 | int fd; | |
103 | int ret; | |
104 | int x; | |
105 | struct pcie_rc_config rc_config; | |
106 | ||
107 | sprintf(filename, "pcie/%d/ctl", controller_id); | |
108 | fd = hv_dev_open((HV_VirtAddr)filename, 0); | |
109 | if (fd < 0) { | |
110 | pr_err("PCI: hv_dev_open(%s) failed\n", filename); | |
111 | return -1; | |
112 | } | |
113 | ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config), | |
114 | sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF); | |
115 | hv_dev_close(fd); | |
116 | if (ret != sizeof(rc_config)) { | |
117 | pr_err("PCI: wanted %zd bytes, got %d\n", | |
118 | sizeof(rc_config), ret); | |
119 | return -1; | |
120 | } | |
121 | /* Record irq_base so that we can map INTx to IRQ # later. */ | |
122 | controller->irq_base = rc_config.intr; | |
123 | ||
124 | for (x = 0; x < 4; x++) | |
125 | tile_irq_activate(rc_config.intr + x, | |
126 | TILE_IRQ_HW_CLEAR); | |
127 | ||
128 | if (rc_config.plx_gen1) | |
129 | controller->plx_gen1 = 1; | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | /* | |
135 | * First initialization entry point, called from setup_arch(). | |
136 | * | |
137 | * Find valid controllers and fill in pci_controller structs for each | |
138 | * of them. | |
139 | * | |
140 | * Returns the number of controllers discovered. | |
141 | */ | |
142 | int __init tile_pci_init(void) | |
143 | { | |
144 | int i; | |
145 | ||
146 | pr_info("PCI: Searching for controllers...\n"); | |
147 | ||
148 | /* Do any configuration we need before using the PCIe */ | |
149 | ||
150 | for (i = 0; i < TILE_NUM_PCIE; i++) { | |
151 | int hv_cfg_fd0 = -1; | |
152 | int hv_cfg_fd1 = -1; | |
153 | int hv_mem_fd = -1; | |
154 | char name[32]; | |
155 | struct pci_controller *controller; | |
156 | ||
157 | /* | |
158 | * Open the fd to the HV. If it fails then this | |
159 | * device doesn't exist. | |
160 | */ | |
161 | hv_cfg_fd0 = tile_pcie_open(i, 0); | |
162 | if (hv_cfg_fd0 < 0) | |
163 | continue; | |
164 | hv_cfg_fd1 = tile_pcie_open(i, 1); | |
165 | if (hv_cfg_fd1 < 0) { | |
166 | pr_err("PCI: Couldn't open config fd to HV " | |
167 | "for controller %d\n", i); | |
168 | goto err_cont; | |
169 | } | |
170 | ||
171 | sprintf(name, "pcie/%d/mem", i); | |
172 | hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0); | |
173 | if (hv_mem_fd < 0) { | |
174 | pr_err("PCI: Could not open mem fd to HV!\n"); | |
175 | goto err_cont; | |
176 | } | |
177 | ||
178 | pr_info("PCI: Found PCI controller #%d\n", i); | |
179 | ||
180 | controller = &controllers[num_controllers]; | |
181 | ||
182 | if (tile_init_irqs(i, controller)) { | |
183 | pr_err("PCI: Could not initialize " | |
184 | "IRQs, aborting.\n"); | |
185 | goto err_cont; | |
186 | } | |
187 | ||
188 | controller->index = num_controllers; | |
189 | controller->hv_cfg_fd[0] = hv_cfg_fd0; | |
190 | controller->hv_cfg_fd[1] = hv_cfg_fd1; | |
191 | controller->hv_mem_fd = hv_mem_fd; | |
192 | controller->first_busno = 0; | |
193 | controller->last_busno = 0xff; | |
194 | controller->ops = &tile_cfg_ops; | |
195 | ||
196 | num_controllers++; | |
197 | continue; | |
198 | ||
199 | err_cont: | |
200 | if (hv_cfg_fd0 >= 0) | |
201 | hv_dev_close(hv_cfg_fd0); | |
202 | if (hv_cfg_fd1 >= 0) | |
203 | hv_dev_close(hv_cfg_fd1); | |
204 | if (hv_mem_fd >= 0) | |
205 | hv_dev_close(hv_mem_fd); | |
206 | continue; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Before using the PCIe, see if we need to do any platform-specific | |
211 | * configuration, such as the PLX switch Gen 1 issue on TILEmpower. | |
212 | */ | |
213 | for (i = 0; i < num_controllers; i++) { | |
214 | struct pci_controller *controller = &controllers[i]; | |
215 | ||
216 | if (controller->plx_gen1) | |
217 | tile_plx_gen1 = 1; | |
218 | } | |
219 | ||
220 | return num_controllers; | |
221 | } | |
222 | ||
223 | /* | |
224 | * (pin - 1) converts from the PCI standard's [1:4] convention to | |
225 | * a normal [0:3] range. | |
226 | */ | |
227 | static int tile_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
228 | { | |
229 | struct pci_controller *controller = | |
230 | (struct pci_controller *)dev->sysdata; | |
231 | return (pin - 1) + controller->irq_base; | |
232 | } | |
233 | ||
234 | ||
235 | static void __init fixup_read_and_payload_sizes(void) | |
236 | { | |
237 | struct pci_dev *dev = NULL; | |
238 | int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */ | |
239 | int max_read_size = 0x2; /* Limit to 512 byte reads. */ | |
240 | u16 new_values; | |
241 | ||
242 | /* Scan for the smallest maximum payload size. */ | |
243 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
244 | int pcie_caps_offset; | |
245 | u32 devcap; | |
246 | int max_payload; | |
247 | ||
248 | pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
249 | if (pcie_caps_offset == 0) | |
250 | continue; | |
251 | ||
252 | pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP, | |
253 | &devcap); | |
254 | max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD; | |
255 | if (max_payload < smallest_max_payload) | |
256 | smallest_max_payload = max_payload; | |
257 | } | |
258 | ||
259 | /* Now, set the max_payload_size for all devices to that value. */ | |
260 | new_values = (max_read_size << 12) | (smallest_max_payload << 5); | |
261 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
262 | int pcie_caps_offset; | |
263 | u16 devctl; | |
264 | ||
265 | pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
266 | if (pcie_caps_offset == 0) | |
267 | continue; | |
268 | ||
269 | pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, | |
270 | &devctl); | |
271 | devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ); | |
272 | devctl |= new_values; | |
273 | pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, | |
274 | devctl); | |
275 | } | |
276 | } | |
277 | ||
278 | ||
279 | /* | |
280 | * Second PCI initialization entry point, called by subsys_initcall. | |
281 | * | |
282 | * The controllers have been set up by the time we get here, by a call to | |
283 | * tile_pci_init. | |
284 | */ | |
285 | static int __init pcibios_init(void) | |
286 | { | |
287 | int i; | |
288 | ||
289 | pr_info("PCI: Probing PCI hardware\n"); | |
290 | ||
291 | /* | |
292 | * Delay a bit in case devices aren't ready. Some devices are | |
293 | * known to require at least 20ms here, but we use a more | |
294 | * conservative value. | |
295 | */ | |
296 | mdelay(250); | |
297 | ||
298 | /* Scan all of the recorded PCI controllers. */ | |
299 | for (i = 0; i < num_controllers; i++) { | |
300 | struct pci_controller *controller = &controllers[i]; | |
301 | struct pci_bus *bus; | |
302 | ||
303 | pr_info("PCI: initializing controller #%d\n", i); | |
304 | ||
305 | /* | |
306 | * This comes from the generic Linux PCI driver. | |
307 | * | |
308 | * It reads the PCI tree for this bus into the Linux | |
309 | * data structures. | |
310 | * | |
311 | * This is inlined in linux/pci.h and calls into | |
312 | * pci_scan_bus_parented() in probe.c. | |
313 | */ | |
314 | bus = pci_scan_bus(0, controller->ops, controller); | |
315 | controller->root_bus = bus; | |
316 | controller->last_busno = bus->subordinate; | |
317 | ||
318 | } | |
319 | ||
320 | /* Do machine dependent PCI interrupt routing */ | |
321 | pci_fixup_irqs(pci_common_swizzle, tile_map_irq); | |
322 | ||
323 | /* | |
324 | * This comes from the generic Linux PCI driver. | |
325 | * | |
326 | * It allocates all of the resources (I/O memory, etc) | |
327 | * associated with the devices read in above. | |
328 | */ | |
329 | ||
330 | pci_assign_unassigned_resources(); | |
331 | ||
332 | /* Configure the max_read_size and max_payload_size values. */ | |
333 | fixup_read_and_payload_sizes(); | |
334 | ||
335 | /* Record the I/O resources in the PCI controller structure. */ | |
336 | for (i = 0; i < num_controllers; i++) { | |
337 | struct pci_bus *root_bus = controllers[i].root_bus; | |
338 | struct pci_bus *next_bus; | |
339 | struct pci_dev *dev; | |
340 | ||
341 | list_for_each_entry(dev, &root_bus->devices, bus_list) { | |
342 | /* Find the PCI host controller, ie. the 1st bridge. */ | |
343 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && | |
344 | (PCI_SLOT(dev->devfn) == 0)) { | |
345 | next_bus = dev->subordinate; | |
346 | controllers[i].mem_resources[0] = | |
347 | *next_bus->resource[0]; | |
348 | controllers[i].mem_resources[1] = | |
349 | *next_bus->resource[1]; | |
350 | controllers[i].mem_resources[2] = | |
351 | *next_bus->resource[2]; | |
352 | ||
353 | break; | |
354 | } | |
355 | } | |
356 | ||
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | subsys_initcall(pcibios_init); | |
362 | ||
363 | /* | |
364 | * No bus fixups needed. | |
365 | */ | |
366 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) | |
367 | { | |
368 | /* Nothing needs to be done. */ | |
369 | } | |
370 | ||
371 | /* | |
372 | * This can be called from the generic PCI layer, but doesn't need to | |
373 | * do anything. | |
374 | */ | |
375 | char __devinit *pcibios_setup(char *str) | |
376 | { | |
377 | /* Nothing needs to be done. */ | |
378 | return str; | |
379 | } | |
380 | ||
381 | /* | |
382 | * This is called from the generic Linux layer. | |
383 | */ | |
384 | void __init pcibios_update_irq(struct pci_dev *dev, int irq) | |
385 | { | |
386 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
387 | } | |
388 | ||
389 | /* | |
390 | * Enable memory and/or address decoding, as appropriate, for the | |
391 | * device described by the 'dev' struct. | |
392 | * | |
393 | * This is called from the generic PCI layer, and can be called | |
394 | * for bridges or endpoints. | |
395 | */ | |
396 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
397 | { | |
398 | u16 cmd, old_cmd; | |
399 | u8 header_type; | |
400 | int i; | |
401 | struct resource *r; | |
402 | ||
403 | pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); | |
404 | ||
405 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
406 | old_cmd = cmd; | |
407 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { | |
408 | /* | |
409 | * For bridges, we enable both memory and I/O decoding | |
410 | * in call cases. | |
411 | */ | |
412 | cmd |= PCI_COMMAND_IO; | |
413 | cmd |= PCI_COMMAND_MEMORY; | |
414 | } else { | |
415 | /* | |
416 | * For endpoints, we enable memory and/or I/O decoding | |
417 | * only if they have a memory resource of that type. | |
418 | */ | |
419 | for (i = 0; i < 6; i++) { | |
420 | r = &dev->resource[i]; | |
421 | if (r->flags & IORESOURCE_UNSET) { | |
422 | pr_err("PCI: Device %s not available " | |
423 | "because of resource collisions\n", | |
424 | pci_name(dev)); | |
425 | return -EINVAL; | |
426 | } | |
427 | if (r->flags & IORESOURCE_IO) | |
428 | cmd |= PCI_COMMAND_IO; | |
429 | if (r->flags & IORESOURCE_MEM) | |
430 | cmd |= PCI_COMMAND_MEMORY; | |
431 | } | |
432 | } | |
433 | ||
434 | /* | |
435 | * We only write the command if it changed. | |
436 | */ | |
437 | if (cmd != old_cmd) | |
438 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
439 | return 0; | |
440 | } | |
441 | ||
442 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) | |
443 | { | |
444 | unsigned long start = pci_resource_start(dev, bar); | |
445 | unsigned long len = pci_resource_len(dev, bar); | |
446 | unsigned long flags = pci_resource_flags(dev, bar); | |
447 | ||
448 | if (!len) | |
449 | return NULL; | |
450 | if (max && len > max) | |
451 | len = max; | |
452 | ||
453 | if (!(flags & IORESOURCE_MEM)) { | |
454 | pr_info("PCI: Trying to map invalid resource %#lx\n", flags); | |
455 | start = 0; | |
456 | } | |
457 | ||
458 | return (void __iomem *)start; | |
459 | } | |
460 | EXPORT_SYMBOL(pci_iomap); | |
461 | ||
462 | ||
463 | /**************************************************************** | |
464 | * | |
465 | * Tile PCI config space read/write routines | |
466 | * | |
467 | ****************************************************************/ | |
468 | ||
469 | /* | |
470 | * These are the normal read and write ops | |
471 | * These are expanded with macros from pci_bus_read_config_byte() etc. | |
472 | * | |
473 | * devfn is the combined PCI slot & function. | |
474 | * | |
475 | * offset is in bytes, from the start of config space for the | |
476 | * specified bus & slot. | |
477 | */ | |
478 | ||
479 | static int __devinit tile_cfg_read(struct pci_bus *bus, | |
480 | unsigned int devfn, | |
481 | int offset, | |
482 | int size, | |
483 | u32 *val) | |
484 | { | |
485 | struct pci_controller *controller = bus->sysdata; | |
486 | int busnum = bus->number & 0xff; | |
487 | int slot = (devfn >> 3) & 0x1f; | |
488 | int function = devfn & 0x7; | |
489 | u32 addr; | |
490 | int config_mode = 1; | |
491 | ||
492 | /* | |
493 | * There is no bridge between the Tile and bus 0, so we | |
494 | * use config0 to talk to bus 0. | |
495 | * | |
496 | * If we're talking to a bus other than zero then we | |
497 | * must have found a bridge. | |
498 | */ | |
499 | if (busnum == 0) { | |
500 | /* | |
501 | * We fake an empty slot for (busnum == 0) && (slot > 0), | |
502 | * since there is only one slot on bus 0. | |
503 | */ | |
504 | if (slot) { | |
505 | *val = 0xFFFFFFFF; | |
506 | return 0; | |
507 | } | |
508 | config_mode = 0; | |
509 | } | |
510 | ||
511 | addr = busnum << 20; /* Bus in 27:20 */ | |
512 | addr |= slot << 15; /* Slot (device) in 19:15 */ | |
513 | addr |= function << 12; /* Function is in 14:12 */ | |
514 | addr |= (offset & 0xFFF); /* byte address in 0:11 */ | |
515 | ||
516 | return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0, | |
517 | (HV_VirtAddr)(val), size, addr); | |
518 | } | |
519 | ||
520 | ||
521 | /* | |
25985edc | 522 | * See tile_cfg_read() for relevant comments. |
f02cbbe6 CM |
523 | * Note that "val" is the value to write, not a pointer to that value. |
524 | */ | |
525 | static int __devinit tile_cfg_write(struct pci_bus *bus, | |
526 | unsigned int devfn, | |
527 | int offset, | |
528 | int size, | |
529 | u32 val) | |
530 | { | |
531 | struct pci_controller *controller = bus->sysdata; | |
532 | int busnum = bus->number & 0xff; | |
533 | int slot = (devfn >> 3) & 0x1f; | |
534 | int function = devfn & 0x7; | |
535 | u32 addr; | |
536 | int config_mode = 1; | |
537 | HV_VirtAddr valp = (HV_VirtAddr)&val; | |
538 | ||
539 | /* | |
540 | * For bus 0 slot 0 we use config 0 accesses. | |
541 | */ | |
542 | if (busnum == 0) { | |
543 | /* | |
544 | * We fake an empty slot for (busnum == 0) && (slot > 0), | |
545 | * since there is only one slot on bus 0. | |
546 | */ | |
547 | if (slot) | |
548 | return 0; | |
549 | config_mode = 0; | |
550 | } | |
551 | ||
552 | addr = busnum << 20; /* Bus in 27:20 */ | |
553 | addr |= slot << 15; /* Slot (device) in 19:15 */ | |
554 | addr |= function << 12; /* Function is in 14:12 */ | |
555 | addr |= (offset & 0xFFF); /* byte address in 0:11 */ | |
556 | ||
557 | #ifdef __BIG_ENDIAN | |
558 | /* Point to the correct part of the 32-bit "val". */ | |
559 | valp += 4 - size; | |
560 | #endif | |
561 | ||
562 | return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0, | |
563 | valp, size, addr); | |
564 | } | |
565 | ||
566 | ||
567 | static struct pci_ops tile_cfg_ops = { | |
568 | .read = tile_cfg_read, | |
569 | .write = tile_cfg_write, | |
570 | }; | |
571 | ||
572 | ||
573 | /* | |
574 | * In the following, each PCI controller's mem_resources[1] | |
575 | * represents its (non-prefetchable) PCI memory resource. | |
576 | * mem_resources[0] and mem_resources[2] refer to its PCI I/O and | |
577 | * prefetchable PCI memory resources, respectively. | |
578 | * For more details, see pci_setup_bridge() in setup-bus.c. | |
579 | * By comparing the target PCI memory address against the | |
580 | * end address of controller 0, we can determine the controller | |
581 | * that should accept the PCI memory access. | |
582 | */ | |
583 | #define TILE_READ(size, type) \ | |
584 | type _tile_read##size(unsigned long addr) \ | |
585 | { \ | |
586 | type val; \ | |
587 | int idx = 0; \ | |
588 | if (addr > controllers[0].mem_resources[1].end && \ | |
589 | addr > controllers[0].mem_resources[2].end) \ | |
590 | idx = 1; \ | |
591 | if (hv_dev_pread(controllers[idx].hv_mem_fd, 0, \ | |
592 | (HV_VirtAddr)(&val), sizeof(type), addr)) \ | |
593 | pr_err("PCI: read %zd bytes at 0x%lX failed\n", \ | |
594 | sizeof(type), addr); \ | |
595 | return val; \ | |
596 | } \ | |
597 | EXPORT_SYMBOL(_tile_read##size) | |
598 | ||
599 | TILE_READ(b, u8); | |
600 | TILE_READ(w, u16); | |
601 | TILE_READ(l, u32); | |
602 | TILE_READ(q, u64); | |
603 | ||
604 | #define TILE_WRITE(size, type) \ | |
605 | void _tile_write##size(type val, unsigned long addr) \ | |
606 | { \ | |
607 | int idx = 0; \ | |
608 | if (addr > controllers[0].mem_resources[1].end && \ | |
609 | addr > controllers[0].mem_resources[2].end) \ | |
610 | idx = 1; \ | |
611 | if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0, \ | |
612 | (HV_VirtAddr)(&val), sizeof(type), addr)) \ | |
613 | pr_err("PCI: write %zd bytes at 0x%lX failed\n", \ | |
614 | sizeof(type), addr); \ | |
615 | } \ | |
616 | EXPORT_SYMBOL(_tile_write##size) | |
617 | ||
618 | TILE_WRITE(b, u8); | |
619 | TILE_WRITE(w, u16); | |
620 | TILE_WRITE(l, u32); | |
621 | TILE_WRITE(q, u64); |