[mirror_ubuntu-eoan-kernel.git] / arch / tile / kernel / pci.c

/*
 * Copyright 2011 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/capability.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/export.h>

#include <asm/processor.h>
#include <asm/sections.h>
#include <asm/byteorder.h>
#include <asm/hv_driver.h>
#include <hv/drv_pcie_rc_intf.h>


/*
 * Initialization flow and process
 * -------------------------------
 *
 * This files contains the routines to search for PCI buses,
 * enumerate the buses, and configure any attached devices.
 *
 * There are two entry points here:
 * 1) tile_pci_init
 *    This sets up the pci_controller structs, and opens the
 *    FDs to the hypervisor.  This is called from setup_arch() early
 *    in the boot process.
 * 2) pcibios_init
 *    This probes the PCI bus(es) for any attached hardware.  It's
 *    called by subsys_initcall.  All of the real work is done by the
 *    generic Linux PCI layer.
 *
 */

/*
 * This flag tells if the platform is TILEmpower that needs
 * special configuration for the PLX switch chip.
 */
int __write_once tile_plx_gen1;

static struct pci_controller controllers[TILE_NUM_PCIE];
static int num_controllers;
static int pci_scan_flags[TILE_NUM_PCIE];

static struct pci_ops tile_cfg_ops;


/*
 * We don't need to worry about the alignment of resources.
 */
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
			    resource_size_t size, resource_size_t align)
{
	return res->start;
}
EXPORT_SYMBOL(pcibios_align_resource);

/*
 * Open a FD to the hypervisor PCI device.
 *
 * controller_id is the controller number, config type is 0 or 1 for
 * config0 or config1 operations.
 */
static int __devinit tile_pcie_open(int controller_id, int config_type)
{
	char filename[32];
	int fd;

	sprintf(filename, "pcie/%d/config%d", controller_id, config_type);

	fd = hv_dev_open((HV_VirtAddr)filename, 0);

	return fd;
}


/*
 * Get the IRQ numbers from the HV and set up the handlers for them.
 */
static int __devinit tile_init_irqs(int controller_id,
				 struct pci_controller *controller)
{
	char filename[32];
	int fd;
	int ret;
	int x;
	struct pcie_rc_config rc_config;

	sprintf(filename, "pcie/%d/ctl", controller_id);
	fd = hv_dev_open((HV_VirtAddr)filename, 0);
	if (fd < 0) {
		pr_err("PCI: hv_dev_open(%s) failed\n", filename);
		return -1;
	}
	ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
			   sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
	hv_dev_close(fd);
	if (ret != sizeof(rc_config)) {
		pr_err("PCI: wanted %zd bytes, got %d\n",
		       sizeof(rc_config), ret);
		return -1;
	}
	/* Record irq_base so that we can map INTx to IRQ # later. */
	controller->irq_base = rc_config.intr;

	for (x = 0; x < 4; x++)
		tile_irq_activate(rc_config.intr + x,
				  TILE_IRQ_HW_CLEAR);

	if (rc_config.plx_gen1)
		controller->plx_gen1 = 1;

	return 0;
}

/*
 * First initialization entry point, called from setup_arch().
 *
 * Find valid controllers and fill in pci_controller structs for each
 * of them.
 *
 * Returns the number of controllers discovered.
 */
int __devinit tile_pci_init(void)
{
	int i;

	pr_info("PCI: Searching for controllers...\n");

	/* Re-init number of PCIe controllers to support hot-plug feature. */
	num_controllers = 0;

	/* Do any configuration we need before using the PCIe */

	for (i = 0; i < TILE_NUM_PCIE; i++) {
		/*
		 * To see whether we need a real config op based on
		 * the results of pcibios_init(), to support PCIe hot-plug.
		 */
		if (pci_scan_flags[i] == 0) {
			int hv_cfg_fd0 = -1;
			int hv_cfg_fd1 = -1;
			int hv_mem_fd = -1;
			char name[32];
			struct pci_controller *controller;

			/*
			 * Open the fd to the HV.  If it fails then this
			 * device doesn't exist.
			 */
			hv_cfg_fd0 = tile_pcie_open(i, 0);
			if (hv_cfg_fd0 < 0)
				continue;
			hv_cfg_fd1 = tile_pcie_open(i, 1);
			if (hv_cfg_fd1 < 0) {
				pr_err("PCI: Couldn't open config fd to HV "
				    "for controller %d\n", i);
				goto err_cont;
			}

			sprintf(name, "pcie/%d/mem", i);
			hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
			if (hv_mem_fd < 0) {
				pr_err("PCI: Could not open mem fd to HV!\n");
				goto err_cont;
			}

			pr_info("PCI: Found PCI controller #%d\n", i);

			controller = &controllers[i];

			controller->index = i;
			controller->hv_cfg_fd[0] = hv_cfg_fd0;
			controller->hv_cfg_fd[1] = hv_cfg_fd1;
			controller->hv_mem_fd = hv_mem_fd;
			controller->first_busno = 0;
			controller->last_busno = 0xff;
			controller->ops = &tile_cfg_ops;

			num_controllers++;
			continue;

err_cont:
			if (hv_cfg_fd0 >= 0)
				hv_dev_close(hv_cfg_fd0);
			if (hv_cfg_fd1 >= 0)
				hv_dev_close(hv_cfg_fd1);
			if (hv_mem_fd >= 0)
				hv_dev_close(hv_mem_fd);
			continue;
		}
	}

	/*
	 * Before using the PCIe, see if we need to do any platform-specific
	 * configuration, such as the PLX switch Gen 1 issue on TILEmpower.
	 */
	for (i = 0; i < num_controllers; i++) {
		struct pci_controller *controller = &controllers[i];

		if (controller->plx_gen1)
			tile_plx_gen1 = 1;
	}

	return num_controllers;
}

/*
 * (pin - 1) converts from the PCI standard's [1:4] convention to
 * a normal [0:3] range.
 */
static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_controller *controller =
		(struct pci_controller *)dev->sysdata;
	return (pin - 1) + controller->irq_base;
}


static void __devinit fixup_read_and_payload_sizes(void)
{
	struct pci_dev *dev = NULL;
	int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
	int max_read_size = 0x2; /* Limit to 512 byte reads. */
	u16 new_values;

	/* Scan for the smallest maximum payload size. */
	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
		int pcie_caps_offset;
		u32 devcap;
		int max_payload;

		pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
		if (pcie_caps_offset == 0)
			continue;

		pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
				      &devcap);
		max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
		if (max_payload < smallest_max_payload)
			smallest_max_payload = max_payload;
	}

	/* Now, set the max_payload_size for all devices to that value. */
	new_values = (max_read_size << 12) | (smallest_max_payload << 5);
	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
		int pcie_caps_offset;
		u16 devctl;

		pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
		if (pcie_caps_offset == 0)
			continue;

		pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
				     &devctl);
		devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
		devctl |= new_values;
		pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
				      devctl);
	}
}


/*
 * Second PCI initialization entry point, called by subsys_initcall.
 *
 * The controllers have been set up by the time we get here, by a call to
 * tile_pci_init.
 */
int __devinit pcibios_init(void)
{
	int i;

	pr_info("PCI: Probing PCI hardware\n");

	/*
	 * Delay a bit in case devices aren't ready.  Some devices are
	 * known to require at least 20ms here, but we use a more
	 * conservative value.
	 */
	mdelay(250);

	/* Scan all of the recorded PCI controllers.  */
	for (i = 0; i < TILE_NUM_PCIE; i++) {
		/*
		 * Do real pcibios init ops if the controller is initialized
		 * by tile_pci_init() successfully and not initialized by
		 * pcibios_init() yet to support PCIe hot-plug.
		 */
		if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
			struct pci_controller *controller = &controllers[i];
			struct pci_bus *bus;

			if (tile_init_irqs(i, controller)) {
				pr_err("PCI: Could not initialize IRQs\n");
				continue;
			}

			pr_info("PCI: initializing controller #%d\n", i);

			/*
			 * This comes from the generic Linux PCI driver.
			 *
			 * It reads the PCI tree for this bus into the Linux
			 * data structures.
			 *
			 * This is inlined in linux/pci.h and calls into
			 * pci_scan_bus_parented() in probe.c.
			 */
			bus = pci_scan_bus(0, controller->ops, controller);
			controller->root_bus = bus;
			controller->last_busno = bus->subordinate;
		}
	}

	/* Do machine dependent PCI interrupt routing */
	pci_fixup_irqs(pci_common_swizzle, tile_map_irq);

	/*
	 * This comes from the generic Linux PCI driver.
	 *
	 * It allocates all of the resources (I/O memory, etc)
	 * associated with the devices read in above.
	 */
	pci_assign_unassigned_resources();

	/* Configure the max_read_size and max_payload_size values. */
	fixup_read_and_payload_sizes();

	/* Record the I/O resources in the PCI controller structure. */
	for (i = 0; i < TILE_NUM_PCIE; i++) {
		/*
		 * Do real pcibios init ops if the controller is initialized
		 * by tile_pci_init() successfully and not initialized by
		 * pcibios_init() yet to support PCIe hot-plug.
		 */
		if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
			struct pci_bus *root_bus = controllers[i].root_bus;
			struct pci_bus *next_bus;
			struct pci_dev *dev;

			list_for_each_entry(dev, &root_bus->devices, bus_list) {
				/*
				 * Find the PCI host controller, ie. the 1st
				 * bridge.
				 */
				if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
					(PCI_SLOT(dev->devfn) == 0)) {
					next_bus = dev->subordinate;
					controllers[i].mem_resources[0] =
						*next_bus->resource[0];
					controllers[i].mem_resources[1] =
						 *next_bus->resource[1];
					controllers[i].mem_resources[2] =
						 *next_bus->resource[2];

					/* Setup flags. */
					pci_scan_flags[i] = 1;

					break;
				}
			}
		}
	}

	return 0;
}
subsys_initcall(pcibios_init);

/*
 * No bus fixups needed.
 */
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
	/* Nothing needs to be done. */
}

/*
 * This can be called from the generic PCI layer, but doesn't need to
 * do anything.
 */
char __devinit *pcibios_setup(char *str)
{
	/* Nothing needs to be done. */
	return str;
}

/*
 * This is called from the generic Linux layer.
 */
void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

/*
 * Enable memory and/or address decoding, as appropriate, for the
 * device described by the 'dev' struct.
 *
 * This is called from the generic PCI layer, and can be called
 * for bridges or endpoints.
 */
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	u8 header_type;
	int i;
	struct resource *r;

	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
		/*
		 * For bridges, we enable both memory and I/O decoding
		 * in call cases.
		 */
		cmd |= PCI_COMMAND_IO;
		cmd |= PCI_COMMAND_MEMORY;
	} else {
		/*
		 * For endpoints, we enable memory and/or I/O decoding
		 * only if they have a memory resource of that type.
		 */
		for (i = 0; i < 6; i++) {
			r = &dev->resource[i];
			if (r->flags & IORESOURCE_UNSET) {
				pr_err("PCI: Device %s not available "
				       "because of resource collisions\n",
				       pci_name(dev));
				return -EINVAL;
			}
			if (r->flags & IORESOURCE_IO)
				cmd |= PCI_COMMAND_IO;
			if (r->flags & IORESOURCE_MEM)
				cmd |= PCI_COMMAND_MEMORY;
		}
	}

	/*
	 * We only write the command if it changed.
	 */
	if (cmd != old_cmd)
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	return 0;
}

void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
{
	unsigned long start = pci_resource_start(dev, bar);
	unsigned long len = pci_resource_len(dev, bar);
	unsigned long flags = pci_resource_flags(dev, bar);

	if (!len)
		return NULL;
	if (max && len > max)
		len = max;

	if (!(flags & IORESOURCE_MEM)) {
		pr_info("PCI: Trying to map invalid resource %#lx\n", flags);
		start = 0;
	}

	return (void __iomem *)start;
}
EXPORT_SYMBOL(pci_iomap);


/****************************************************************
 *
 * Tile PCI config space read/write routines
 *
 ****************************************************************/

/*
 * These are the normal read and write ops
 * These are expanded with macros from  pci_bus_read_config_byte() etc.
 *
 * devfn is the combined PCI slot & function.
 *
 * offset is in bytes, from the start of config space for the
 * specified bus & slot.
 */

static int __devinit tile_cfg_read(struct pci_bus *bus,
				   unsigned int devfn,
				   int offset,
				   int size,
				   u32 *val)
{
	struct pci_controller *controller = bus->sysdata;
	int busnum = bus->number & 0xff;
	int slot = (devfn >> 3) & 0x1f;
	int function = devfn & 0x7;
	u32 addr;
	int config_mode = 1;

	/*
	 * There is no bridge between the Tile and bus 0, so we
	 * use config0 to talk to bus 0.
	 *
	 * If we're talking to a bus other than zero then we
	 * must have found a bridge.
	 */
	if (busnum == 0) {
		/*
		 * We fake an empty slot for (busnum == 0) && (slot > 0),
		 * since there is only one slot on bus 0.
		 */
		if (slot) {
			*val = 0xFFFFFFFF;
			return 0;
		}
		config_mode = 0;
	}

	addr = busnum << 20;		/* Bus in 27:20 */
	addr |= slot << 15;		/* Slot (device) in 19:15 */
	addr |= function << 12;		/* Function is in 14:12 */
	addr |= (offset & 0xFFF);	/* byte address in 0:11 */

	return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
			    (HV_VirtAddr)(val), size, addr);
}


/*
 * See tile_cfg_read() for relevant comments.
 * Note that "val" is the value to write, not a pointer to that value.
 */
static int __devinit tile_cfg_write(struct pci_bus *bus,
				    unsigned int devfn,
				    int offset,
				    int size,
				    u32 val)
{
	struct pci_controller *controller = bus->sysdata;
	int busnum = bus->number & 0xff;
	int slot = (devfn >> 3) & 0x1f;
	int function = devfn & 0x7;
	u32 addr;
	int config_mode = 1;
	HV_VirtAddr valp = (HV_VirtAddr)&val;

	/*
	 * For bus 0 slot 0 we use config 0 accesses.
	 */
	if (busnum == 0) {
		/*
		 * We fake an empty slot for (busnum == 0) && (slot > 0),
		 * since there is only one slot on bus 0.
		 */
		if (slot)
			return 0;
		config_mode = 0;
	}

	addr = busnum << 20;		/* Bus in 27:20 */
	addr |= slot << 15;		/* Slot (device) in 19:15 */
	addr |= function << 12;		/* Function is in 14:12 */
	addr |= (offset & 0xFFF);	/* byte address in 0:11 */

#ifdef __BIG_ENDIAN
	/* Point to the correct part of the 32-bit "val". */
	valp += 4 - size;
#endif

	return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
			     valp, size, addr);
}


static struct pci_ops tile_cfg_ops = {
	.read =         tile_cfg_read,
	.write =        tile_cfg_write,
};


/*
 * In the following, each PCI controller's mem_resources[1]
 * represents its (non-prefetchable) PCI memory resource.
 * mem_resources[0] and mem_resources[2] refer to its PCI I/O and
 * prefetchable PCI memory resources, respectively.
 * For more details, see pci_setup_bridge() in setup-bus.c.
 * By comparing the target PCI memory address against the
 * end address of controller 0, we can determine the controller
 * that should accept the PCI memory access.
 */
#define TILE_READ(size, type)						\
type _tile_read##size(unsigned long addr)				\
{									\
	type val;							\
	int idx = 0;							\
	if (addr > controllers[0].mem_resources[1].end &&		\
	    addr > controllers[0].mem_resources[2].end)			\
		idx = 1;                                                \
	if (hv_dev_pread(controllers[idx].hv_mem_fd, 0,			\
			 (HV_VirtAddr)(&val), sizeof(type), addr))	\
		pr_err("PCI: read %zd bytes at 0x%lX failed\n",		\
		       sizeof(type), addr);				\
	return val;							\
}									\
EXPORT_SYMBOL(_tile_read##size)

TILE_READ(b, u8);
TILE_READ(w, u16);
TILE_READ(l, u32);
TILE_READ(q, u64);

#define TILE_WRITE(size, type)						\
void _tile_write##size(type val, unsigned long addr)			\
{									\
	int idx = 0;							\
	if (addr > controllers[0].mem_resources[1].end &&		\
	    addr > controllers[0].mem_resources[2].end)			\
		idx = 1;                                                \
	if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0,		\
			  (HV_VirtAddr)(&val), sizeof(type), addr))	\
		pr_err("PCI: write %zd bytes at 0x%lX failed\n",	\
		       sizeof(type), addr);				\
}									\
EXPORT_SYMBOL(_tile_write##size)

TILE_WRITE(b, u8);
TILE_WRITE(w, u16);
TILE_WRITE(l, u32);
TILE_WRITE(q, u64);
Commit	Line	Data
f02cbbe6	1	/*
398fa5a9	2	* Copyright 2011 Tilera Corporation. All Rights Reserved.
f02cbbe6 CM	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/pci.h>
	17	#include <linux/delay.h>
	18	#include <linux/string.h>
	19	#include <linux/init.h>
	20	#include <linux/capability.h>
	21	#include <linux/sched.h>
	22	#include <linux/errno.h>
	23	#include <linux/bootmem.h>
	24	#include <linux/irq.h>
	25	#include <linux/io.h>
	26	#include <linux/uaccess.h>
3989efb7	27	#include <linux/export.h>
f02cbbe6 CM	28
	29	#include <asm/processor.h>
	30	#include <asm/sections.h>
	31	#include <asm/byteorder.h>
	32	#include <asm/hv_driver.h>
	33	#include <hv/drv_pcie_rc_intf.h>
	34
	35
	36	/*
	37	* Initialization flow and process
	38	* -------------------------------
	39	*
25985edc	40	* This files contains the routines to search for PCI buses,
f02cbbe6 CM	41	* enumerate the buses, and configure any attached devices.
	42	*
	43	* There are two entry points here:
	44	* 1) tile_pci_init
	45	* This sets up the pci_controller structs, and opens the
	46	* FDs to the hypervisor. This is called from setup_arch() early
	47	* in the boot process.
	48	* 2) pcibios_init
	49	* This probes the PCI bus(es) for any attached hardware. It's
	50	* called by subsys_initcall. All of the real work is done by the
	51	* generic Linux PCI layer.
	52	*
	53	*/
	54
	55	/*
	56	* This flag tells if the platform is TILEmpower that needs
	57	* special configuration for the PLX switch chip.
	58	*/
	59	int __write_once tile_plx_gen1;
	60
	61	static struct pci_controller controllers[TILE_NUM_PCIE];
	62	static int num_controllers;
398fa5a9	63	static int pci_scan_flags[TILE_NUM_PCIE];
f02cbbe6 CM	64
	65	static struct pci_ops tile_cfg_ops;
	66
	67
	68	/*
	69	* We don't need to worry about the alignment of resources.
	70	*/
	71	resource_size_t pcibios_align_resource(void data, const struct resource res,
	72	resource_size_t size, resource_size_t align)
	73	{
	74	return res->start;
	75	}
	76	EXPORT_SYMBOL(pcibios_align_resource);
	77
	78	/*
	79	* Open a FD to the hypervisor PCI device.
	80	*
	81	* controller_id is the controller number, config type is 0 or 1 for
	82	* config0 or config1 operations.
	83	*/
398fa5a9	84	static int __devinit tile_pcie_open(int controller_id, int config_type)
f02cbbe6 CM	85	{
	86	char filename[32];
	87	int fd;
	88
	89	sprintf(filename, "pcie/%d/config%d", controller_id, config_type);
	90
	91	fd = hv_dev_open((HV_VirtAddr)filename, 0);
	92
	93	return fd;
	94	}
	95
	96
	97	/*
	98	* Get the IRQ numbers from the HV and set up the handlers for them.
	99	*/
398fa5a9	100	static int __devinit tile_init_irqs(int controller_id,
f02cbbe6 CM	101	struct pci_controller *controller)
	102	{
	103	char filename[32];
	104	int fd;
	105	int ret;
	106	int x;
	107	struct pcie_rc_config rc_config;
	108
	109	sprintf(filename, "pcie/%d/ctl", controller_id);
	110	fd = hv_dev_open((HV_VirtAddr)filename, 0);
	111	if (fd < 0) {
	112	pr_err("PCI: hv_dev_open(%s) failed\n", filename);
	113	return -1;
	114	}
	115	ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
	116	sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
	117	hv_dev_close(fd);
	118	if (ret != sizeof(rc_config)) {
	119	pr_err("PCI: wanted %zd bytes, got %d\n",
	120	sizeof(rc_config), ret);
	121	return -1;
	122	}
	123	/* Record irq_base so that we can map INTx to IRQ # later. */
	124	controller->irq_base = rc_config.intr;
	125
	126	for (x = 0; x < 4; x++)
	127	tile_irq_activate(rc_config.intr + x,
	128	TILE_IRQ_HW_CLEAR);
	129
	130	if (rc_config.plx_gen1)
	131	controller->plx_gen1 = 1;
	132
	133	return 0;
	134	}
	135
	136	/*
	137	* First initialization entry point, called from setup_arch().
	138	*
	139	* Find valid controllers and fill in pci_controller structs for each
	140	* of them.
	141	*
	142	* Returns the number of controllers discovered.
	143	*/
398fa5a9	144	int __devinit tile_pci_init(void)
f02cbbe6 CM	145	{
	146	int i;
	147
	148	pr_info("PCI: Searching for controllers...\n");
	149
398fa5a9 CM	150	/* Re-init number of PCIe controllers to support hot-plug feature. */
	151	num_controllers = 0;
	152
f02cbbe6 CM	153	/* Do any configuration we need before using the PCIe */
	154
	155	for (i = 0; i < TILE_NUM_PCIE; i++) {
f02cbbe6	156	/*
398fa5a9 CM	157	* To see whether we need a real config op based on
398fa5a9 CM	158	* the results of pcibios_init(), to support PCIe hot-plug.
f02cbbe6	159	*/
398fa5a9 CM	160	if (pci_scan_flags[i] == 0) {
	161	int hv_cfg_fd0 = -1;
	162	int hv_cfg_fd1 = -1;
	163	int hv_mem_fd = -1;
	164	char name[32];
	165	struct pci_controller *controller;
	166
	167	/*
	168	* Open the fd to the HV. If it fails then this
	169	* device doesn't exist.
	170	*/
	171	hv_cfg_fd0 = tile_pcie_open(i, 0);
	172	if (hv_cfg_fd0 < 0)
	173	continue;
	174	hv_cfg_fd1 = tile_pcie_open(i, 1);
	175	if (hv_cfg_fd1 < 0) {
	176	pr_err("PCI: Couldn't open config fd to HV "
	177	"for controller %d\n", i);
	178	goto err_cont;
	179	}
f02cbbe6	180
398fa5a9 CM	181	sprintf(name, "pcie/%d/mem", i);
	182	hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
	183	if (hv_mem_fd < 0) {
	184	pr_err("PCI: Could not open mem fd to HV!\n");
	185	goto err_cont;
	186	}
f02cbbe6	187
398fa5a9	188	pr_info("PCI: Found PCI controller #%d\n", i);
f02cbbe6	189
398fa5a9	190	controller = &controllers[i];
f02cbbe6	191
398fa5a9 CM	192	controller->index = i;
	193	controller->hv_cfg_fd[0] = hv_cfg_fd0;
	194	controller->hv_cfg_fd[1] = hv_cfg_fd1;
	195	controller->hv_mem_fd = hv_mem_fd;
	196	controller->first_busno = 0;
	197	controller->last_busno = 0xff;
	198	controller->ops = &tile_cfg_ops;
f02cbbe6	199
398fa5a9 CM	200	num_controllers++;
398fa5a9 CM	201	continue;
f02cbbe6 CM	202
f02cbbe6 CM	203	err_cont:
398fa5a9 CM	204	if (hv_cfg_fd0 >= 0)
	205	hv_dev_close(hv_cfg_fd0);
	206	if (hv_cfg_fd1 >= 0)
	207	hv_dev_close(hv_cfg_fd1);
	208	if (hv_mem_fd >= 0)
	209	hv_dev_close(hv_mem_fd);
	210	continue;
	211	}
f02cbbe6 CM	212	}
	213
	214	/*
	215	* Before using the PCIe, see if we need to do any platform-specific
	216	* configuration, such as the PLX switch Gen 1 issue on TILEmpower.
	217	*/
	218	for (i = 0; i < num_controllers; i++) {
	219	struct pci_controller *controller = &controllers[i];
	220
	221	if (controller->plx_gen1)
	222	tile_plx_gen1 = 1;
	223	}
	224
	225	return num_controllers;
	226	}
	227
	228	/*
	229	* (pin - 1) converts from the PCI standard's [1:4] convention to
	230	* a normal [0:3] range.
	231	*/
d5341942	232	static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
f02cbbe6 CM	233	{
	234	struct pci_controller *controller =
	235	(struct pci_controller *)dev->sysdata;
	236	return (pin - 1) + controller->irq_base;
	237	}
	238
	239
398fa5a9	240	static void __devinit fixup_read_and_payload_sizes(void)
f02cbbe6 CM	241	{
	242	struct pci_dev *dev = NULL;
	243	int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
	244	int max_read_size = 0x2; /* Limit to 512 byte reads. */
	245	u16 new_values;
	246
	247	/* Scan for the smallest maximum payload size. */
	248	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
	249	int pcie_caps_offset;
	250	u32 devcap;
	251	int max_payload;
	252
	253	pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
	254	if (pcie_caps_offset == 0)
	255	continue;
	256
	257	pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
	258	&devcap);
	259	max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
	260	if (max_payload < smallest_max_payload)
	261	smallest_max_payload = max_payload;
	262	}
	263
	264	/* Now, set the max_payload_size for all devices to that value. */
	265	new_values = (max_read_size << 12) \| (smallest_max_payload << 5);
	266	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
	267	int pcie_caps_offset;
	268	u16 devctl;
	269
	270	pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
	271	if (pcie_caps_offset == 0)
	272	continue;
	273
	274	pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
	275	&devctl);
	276	devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD \| PCI_EXP_DEVCTL_READRQ);
	277	devctl \|= new_values;
	278	pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
	279	devctl);
	280	}
	281	}
	282
	283
	284	/*
	285	* Second PCI initialization entry point, called by subsys_initcall.
	286	*
	287	* The controllers have been set up by the time we get here, by a call to
	288	* tile_pci_init.
	289	*/
398fa5a9	290	int __devinit pcibios_init(void)
f02cbbe6 CM	291	{
	292	int i;
	293
	294	pr_info("PCI: Probing PCI hardware\n");
	295
	296	/*
	297	* Delay a bit in case devices aren't ready. Some devices are
	298	* known to require at least 20ms here, but we use a more
	299	* conservative value.
	300	*/
	301	mdelay(250);
	302
	303	/* Scan all of the recorded PCI controllers. */
398fa5a9	304	for (i = 0; i < TILE_NUM_PCIE; i++) {
f02cbbe6	305	/*
398fa5a9 CM	306	* Do real pcibios init ops if the controller is initialized
	307	* by tile_pci_init() successfully and not initialized by
	308	* pcibios_init() yet to support PCIe hot-plug.
f02cbbe6	309	*/
398fa5a9 CM	310	if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
	311	struct pci_controller *controller = &controllers[i];
	312	struct pci_bus *bus;
	313
f4de51de CM	314	if (tile_init_irqs(i, controller)) {
	315	pr_err("PCI: Could not initialize IRQs\n");
	316	continue;
	317	}
	318
398fa5a9 CM	319	pr_info("PCI: initializing controller #%d\n", i);
	320
	321	/*
	322	* This comes from the generic Linux PCI driver.
	323	*
	324	* It reads the PCI tree for this bus into the Linux
	325	* data structures.
	326	*
	327	* This is inlined in linux/pci.h and calls into
	328	* pci_scan_bus_parented() in probe.c.
	329	*/
	330	bus = pci_scan_bus(0, controller->ops, controller);
	331	controller->root_bus = bus;
	332	controller->last_busno = bus->subordinate;
	333	}
f02cbbe6 CM	334	}
	335
	336	/* Do machine dependent PCI interrupt routing */
	337	pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
	338
	339	/*
	340	* This comes from the generic Linux PCI driver.
	341	*
	342	* It allocates all of the resources (I/O memory, etc)
	343	* associated with the devices read in above.
	344	*/
f02cbbe6 CM	345	pci_assign_unassigned_resources();
	346
	347	/* Configure the max_read_size and max_payload_size values. */
	348	fixup_read_and_payload_sizes();
	349
	350	/* Record the I/O resources in the PCI controller structure. */
398fa5a9 CM	351	for (i = 0; i < TILE_NUM_PCIE; i++) {
	352	/*
	353	* Do real pcibios init ops if the controller is initialized
	354	* by tile_pci_init() successfully and not initialized by
	355	* pcibios_init() yet to support PCIe hot-plug.
	356	*/
	357	if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
	358	struct pci_bus *root_bus = controllers[i].root_bus;
	359	struct pci_bus *next_bus;
	360	struct pci_dev *dev;
	361
	362	list_for_each_entry(dev, &root_bus->devices, bus_list) {
	363	/*
	364	* Find the PCI host controller, ie. the 1st
	365	* bridge.
	366	*/
	367	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
	368	(PCI_SLOT(dev->devfn) == 0)) {
	369	next_bus = dev->subordinate;
	370	controllers[i].mem_resources[0] =
	371	*next_bus->resource[0];
	372	controllers[i].mem_resources[1] =
	373	*next_bus->resource[1];
	374	controllers[i].mem_resources[2] =
	375	*next_bus->resource[2];
	376
	377	/* Setup flags. */
	378	pci_scan_flags[i] = 1;
	379
	380	break;
	381	}
f02cbbe6 CM	382	}
f02cbbe6 CM	383	}
f02cbbe6 CM	384	}
	385
	386	return 0;
	387	}
	388	subsys_initcall(pcibios_init);
	389
	390	/*
	391	* No bus fixups needed.
	392	*/
	393	void __devinit pcibios_fixup_bus(struct pci_bus *bus)
	394	{
	395	/* Nothing needs to be done. */
	396	}
	397
	398	/*
	399	* This can be called from the generic PCI layer, but doesn't need to
	400	* do anything.
	401	*/
	402	char __devinit pcibios_setup(char str)
	403	{
	404	/* Nothing needs to be done. */
	405	return str;
	406	}
	407
	408	/*
	409	* This is called from the generic Linux layer.
	410	*/
398fa5a9	411	void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
f02cbbe6 CM	412	{
	413	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	414	}
	415
	416	/*
	417	* Enable memory and/or address decoding, as appropriate, for the
	418	* device described by the 'dev' struct.
	419	*
	420	* This is called from the generic PCI layer, and can be called
	421	* for bridges or endpoints.
	422	*/
	423	int pcibios_enable_device(struct pci_dev *dev, int mask)
	424	{
	425	u16 cmd, old_cmd;
	426	u8 header_type;
	427	int i;
	428	struct resource *r;
	429
	430	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
	431
	432	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	433	old_cmd = cmd;
	434	if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
	435	/*
	436	* For bridges, we enable both memory and I/O decoding
	437	* in call cases.
	438	*/
	439	cmd \|= PCI_COMMAND_IO;
	440	cmd \|= PCI_COMMAND_MEMORY;
	441	} else {
	442	/*
	443	* For endpoints, we enable memory and/or I/O decoding
	444	* only if they have a memory resource of that type.
	445	*/
	446	for (i = 0; i < 6; i++) {
	447	r = &dev->resource[i];
	448	if (r->flags & IORESOURCE_UNSET) {
	449	pr_err("PCI: Device %s not available "
	450	"because of resource collisions\n",
	451	pci_name(dev));
	452	return -EINVAL;
	453	}
	454	if (r->flags & IORESOURCE_IO)
	455	cmd \|= PCI_COMMAND_IO;
	456	if (r->flags & IORESOURCE_MEM)
	457	cmd \|= PCI_COMMAND_MEMORY;
	458	}
	459	}
	460
	461	/*
	462	* We only write the command if it changed.
	463	*/
	464	if (cmd != old_cmd)
	465	pci_write_config_word(dev, PCI_COMMAND, cmd);
	466	return 0;
	467	}
	468
	469	void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long max)
	470	{
	471	unsigned long start = pci_resource_start(dev, bar);
	472	unsigned long len = pci_resource_len(dev, bar);
	473	unsigned long flags = pci_resource_flags(dev, bar);
	474
	475	if (!len)
476	return NULL;
477	if (max && len > max)
478	len = max;
479
480	if (!(flags & IORESOURCE_MEM)) {
481	pr_info("PCI: Trying to map invalid resource %#lx\n", flags);
482	start = 0;
483	}
484
485	return (void __iomem *)start;
486	}
487	EXPORT_SYMBOL(pci_iomap);
488
489
490	/****************************************************************
491	*
492	* Tile PCI config space read/write routines
493	*
494	****************************************************************/
495
496	/*
497	* These are the normal read and write ops
498	* These are expanded with macros from pci_bus_read_config_byte() etc.
499	*
500	* devfn is the combined PCI slot & function.
501	*
502	* offset is in bytes, from the start of config space for the
503	* specified bus & slot.
504	*/
505
506	static int __devinit tile_cfg_read(struct pci_bus *bus,
507	unsigned int devfn,
508	int offset,
509	int size,
510	u32 *val)
511	{
512	struct pci_controller *controller = bus->sysdata;
513	int busnum = bus->number & 0xff;
514	int slot = (devfn >> 3) & 0x1f;
515	int function = devfn & 0x7;
516	u32 addr;
517	int config_mode = 1;
518
519	/*
520	* There is no bridge between the Tile and bus 0, so we
521	* use config0 to talk to bus 0.
522	*
523	* If we're talking to a bus other than zero then we
524	* must have found a bridge.
525	*/
526	if (busnum == 0) {
527	/*
528	* We fake an empty slot for (busnum == 0) && (slot > 0),
529	* since there is only one slot on bus 0.
530	*/
531	if (slot) {
532	*val = 0xFFFFFFFF;
533	return 0;
534	}
535	config_mode = 0;
536	}
537
538	addr = busnum << 20; /* Bus in 27:20 */
539	addr \|= slot << 15; /* Slot (device) in 19:15 */
540	addr \|= function << 12; /* Function is in 14:12 */
541	addr \|= (offset & 0xFFF); /* byte address in 0:11 */
542
543	return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
544	(HV_VirtAddr)(val), size, addr);
545	}
546
547
548	/*
25985edc	549	* See tile_cfg_read() for relevant comments.
f02cbbe6 CM	550	* Note that "val" is the value to write, not a pointer to that value.
	551	*/
	552	static int __devinit tile_cfg_write(struct pci_bus *bus,
	553	unsigned int devfn,
	554	int offset,
	555	int size,
	556	u32 val)
	557	{
	558	struct pci_controller *controller = bus->sysdata;
	559	int busnum = bus->number & 0xff;
	560	int slot = (devfn >> 3) & 0x1f;
	561	int function = devfn & 0x7;
	562	u32 addr;
	563	int config_mode = 1;
	564	HV_VirtAddr valp = (HV_VirtAddr)&val;
	565
	566	/*
	567	* For bus 0 slot 0 we use config 0 accesses.
	568	*/
	569	if (busnum == 0) {
	570	/*
	571	* We fake an empty slot for (busnum == 0) && (slot > 0),
	572	* since there is only one slot on bus 0.
	573	*/
	574	if (slot)
	575	return 0;
	576	config_mode = 0;
	577	}
	578
	579	addr = busnum << 20; /* Bus in 27:20 */
	580	addr \|= slot << 15; /* Slot (device) in 19:15 */
	581	addr \|= function << 12; /* Function is in 14:12 */
	582	addr \|= (offset & 0xFFF); /* byte address in 0:11 */
	583
	584	#ifdef __BIG_ENDIAN
	585	/* Point to the correct part of the 32-bit "val". */
	586	valp += 4 - size;
	587	#endif
	588
	589	return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
	590	valp, size, addr);
	591	}
	592
	593
	594	static struct pci_ops tile_cfg_ops = {
	595	.read = tile_cfg_read,
	596	.write = tile_cfg_write,
	597	};
	598
	599
	600	/*
	601	* In the following, each PCI controller's mem_resources[1]
	602	* represents its (non-prefetchable) PCI memory resource.
	603	* mem_resources[0] and mem_resources[2] refer to its PCI I/O and
	604	* prefetchable PCI memory resources, respectively.
	605	* For more details, see pci_setup_bridge() in setup-bus.c.
	606	* By comparing the target PCI memory address against the
	607	* end address of controller 0, we can determine the controller
	608	* that should accept the PCI memory access.
	609	*/
	610	#define TILE_READ(size, type) \
	611	type _tile_read##size(unsigned long addr) \
	612	{ \
	613	type val; \
614	int idx = 0; \
615	if (addr > controllers[0].mem_resources[1].end && \
616	addr > controllers[0].mem_resources[2].end) \
617	idx = 1; \
618	if (hv_dev_pread(controllers[idx].hv_mem_fd, 0, \
619	(HV_VirtAddr)(&val), sizeof(type), addr)) \
620	pr_err("PCI: read %zd bytes at 0x%lX failed\n", \
621	sizeof(type), addr); \
622	return val; \
623	} \
624	EXPORT_SYMBOL(_tile_read##size)
625
626	TILE_READ(b, u8);
627	TILE_READ(w, u16);
628	TILE_READ(l, u32);
629	TILE_READ(q, u64);
630
631	#define TILE_WRITE(size, type) \
632	void _tile_write##size(type val, unsigned long addr) \
633	{ \
634	int idx = 0; \
635	if (addr > controllers[0].mem_resources[1].end && \
636	addr > controllers[0].mem_resources[2].end) \
637	idx = 1; \
638	if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0, \
639	(HV_VirtAddr)(&val), sizeof(type), addr)) \
640	pr_err("PCI: write %zd bytes at 0x%lX failed\n", \
641	sizeof(type), addr); \
642	} \
643	EXPORT_SYMBOL(_tile_write##size)
644
645	TILE_WRITE(b, u8);
646	TILE_WRITE(w, u16);
647	TILE_WRITE(l, u32);
648	TILE_WRITE(q, u64);