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12962267 CM |
1 | /* |
2 | * Copyright 2012 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/mmzone.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/capability.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/msi.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/uaccess.h> | |
28 | #include <linux/ctype.h> | |
29 | ||
30 | #include <asm/processor.h> | |
31 | #include <asm/sections.h> | |
32 | #include <asm/byteorder.h> | |
33 | ||
34 | #include <gxio/iorpc_globals.h> | |
35 | #include <gxio/kiorpc.h> | |
36 | #include <gxio/trio.h> | |
37 | #include <gxio/iorpc_trio.h> | |
38 | #include <hv/drv_trio_intf.h> | |
39 | ||
40 | #include <arch/sim.h> | |
41 | ||
42 | /* | |
41bb38fc | 43 | * This file containes the routines to search for PCI buses, |
12962267 | 44 | * enumerate the buses, and configure any attached devices. |
12962267 CM |
45 | */ |
46 | ||
47 | #define DEBUG_PCI_CFG 0 | |
48 | ||
49 | #if DEBUG_PCI_CFG | |
50 | #define TRACE_CFG_WR(size, val, bus, dev, func, offset) \ | |
51 | pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \ | |
52 | size, val, bus, dev, func, offset & 0xFFF); | |
53 | #define TRACE_CFG_RD(size, val, bus, dev, func, offset) \ | |
54 | pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \ | |
55 | size, val, bus, dev, func, offset & 0xFFF); | |
56 | #else | |
57 | #define TRACE_CFG_WR(...) | |
58 | #define TRACE_CFG_RD(...) | |
59 | #endif | |
60 | ||
61 | static int __devinitdata pci_probe = 1; | |
62 | ||
63 | /* Information on the PCIe RC ports configuration. */ | |
64 | static int __devinitdata pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; | |
65 | ||
66 | /* | |
67 | * On some platforms with one or more Gx endpoint ports, we need to | |
68 | * delay the PCIe RC port probe for a few seconds to work around | |
69 | * a HW PCIe link-training bug. The exact delay is specified with | |
70 | * a kernel boot argument in the form of "pcie_rc_delay=T,P,S", | |
71 | * where T is the TRIO instance number, P is the port number and S is | |
72 | * the delay in seconds. If the delay is not provided, the value | |
73 | * will be DEFAULT_RC_DELAY. | |
74 | */ | |
75 | static int __devinitdata rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; | |
76 | ||
77 | /* Default number of seconds that the PCIe RC port probe can be delayed. */ | |
78 | #define DEFAULT_RC_DELAY 10 | |
79 | ||
80 | /* Max number of seconds that the PCIe RC port probe can be delayed. */ | |
81 | #define MAX_RC_DELAY 20 | |
82 | ||
83 | /* Array of the PCIe ports configuration info obtained from the BIB. */ | |
84 | struct pcie_port_property pcie_ports[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; | |
85 | ||
86 | /* All drivers share the TRIO contexts defined here. */ | |
87 | gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; | |
88 | ||
89 | /* Pointer to an array of PCIe RC controllers. */ | |
90 | struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES]; | |
91 | int num_rc_controllers; | |
92 | static int num_ep_controllers; | |
93 | ||
94 | static struct pci_ops tile_cfg_ops; | |
95 | ||
96 | /* Mask of CPUs that should receive PCIe interrupts. */ | |
97 | static struct cpumask intr_cpus_map; | |
98 | ||
99 | /* | |
100 | * We don't need to worry about the alignment of resources. | |
101 | */ | |
102 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, | |
103 | resource_size_t size, resource_size_t align) | |
104 | { | |
105 | return res->start; | |
106 | } | |
107 | EXPORT_SYMBOL(pcibios_align_resource); | |
108 | ||
109 | ||
110 | /* | |
111 | * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #. | |
112 | * For now, we simply send interrupts to non-dataplane CPUs. | |
113 | * We may implement methods to allow user to specify the target CPUs, | |
114 | * e.g. via boot arguments. | |
115 | */ | |
116 | static int tile_irq_cpu(int irq) | |
117 | { | |
118 | unsigned int count; | |
119 | int i = 0; | |
120 | int cpu; | |
121 | ||
122 | count = cpumask_weight(&intr_cpus_map); | |
123 | if (unlikely(count == 0)) { | |
124 | pr_warning("intr_cpus_map empty, interrupts will be" | |
125 | " delievered to dataplane tiles\n"); | |
126 | return irq % (smp_height * smp_width); | |
127 | } | |
128 | ||
129 | count = irq % count; | |
130 | for_each_cpu(cpu, &intr_cpus_map) { | |
131 | if (i++ == count) | |
132 | break; | |
133 | } | |
134 | return cpu; | |
135 | } | |
136 | ||
137 | /* | |
138 | * Open a file descriptor to the TRIO shim. | |
139 | */ | |
140 | static int __devinit tile_pcie_open(int trio_index) | |
141 | { | |
142 | gxio_trio_context_t *context = &trio_contexts[trio_index]; | |
143 | int ret; | |
144 | ||
145 | /* | |
146 | * This opens a file descriptor to the TRIO shim. | |
147 | */ | |
148 | ret = gxio_trio_init(context, trio_index); | |
149 | if (ret < 0) | |
150 | return ret; | |
151 | ||
152 | /* | |
153 | * Allocate an ASID for the kernel. | |
154 | */ | |
155 | ret = gxio_trio_alloc_asids(context, 1, 0, 0); | |
156 | if (ret < 0) { | |
157 | pr_err("PCI: ASID alloc failure on TRIO %d, give up\n", | |
158 | trio_index); | |
159 | goto asid_alloc_failure; | |
160 | } | |
161 | ||
162 | context->asid = ret; | |
163 | ||
164 | #ifdef USE_SHARED_PCIE_CONFIG_REGION | |
165 | /* | |
166 | * Alloc a PIO region for config access, shared by all MACs per TRIO. | |
167 | * This shouldn't fail since the kernel is supposed to the first | |
168 | * client of the TRIO's PIO regions. | |
169 | */ | |
170 | ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0); | |
171 | if (ret < 0) { | |
172 | pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n", | |
173 | trio_index); | |
174 | goto pio_alloc_failure; | |
175 | } | |
176 | ||
177 | context->pio_cfg_index = ret; | |
178 | ||
179 | /* | |
180 | * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter | |
181 | * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR. | |
182 | */ | |
183 | ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index, | |
184 | 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE); | |
185 | if (ret < 0) { | |
186 | pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n", | |
187 | trio_index); | |
188 | goto pio_alloc_failure; | |
189 | } | |
190 | #endif | |
191 | ||
192 | return ret; | |
193 | ||
194 | asid_alloc_failure: | |
195 | #ifdef USE_SHARED_PCIE_CONFIG_REGION | |
196 | pio_alloc_failure: | |
197 | #endif | |
198 | hv_dev_close(context->fd); | |
199 | ||
200 | return ret; | |
201 | } | |
202 | ||
203 | static void | |
204 | tilegx_legacy_irq_ack(struct irq_data *d) | |
205 | { | |
206 | __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq); | |
207 | } | |
208 | ||
209 | static void | |
210 | tilegx_legacy_irq_mask(struct irq_data *d) | |
211 | { | |
212 | __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq); | |
213 | } | |
214 | ||
215 | static void | |
216 | tilegx_legacy_irq_unmask(struct irq_data *d) | |
217 | { | |
218 | __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq); | |
219 | } | |
220 | ||
221 | static struct irq_chip tilegx_legacy_irq_chip = { | |
222 | .name = "tilegx_legacy_irq", | |
223 | .irq_ack = tilegx_legacy_irq_ack, | |
224 | .irq_mask = tilegx_legacy_irq_mask, | |
225 | .irq_unmask = tilegx_legacy_irq_unmask, | |
226 | ||
227 | /* TBD: support set_affinity. */ | |
228 | }; | |
229 | ||
230 | /* | |
231 | * This is a wrapper function of the kernel level-trigger interrupt | |
232 | * handler handle_level_irq() for PCI legacy interrupts. The TRIO | |
233 | * is configured such that only INTx Assert interrupts are proxied | |
234 | * to Linux which just calls handle_level_irq() after clearing the | |
235 | * MAC INTx Assert status bit associated with this interrupt. | |
236 | */ | |
237 | static void | |
238 | trio_handle_level_irq(unsigned int irq, struct irq_desc *desc) | |
239 | { | |
240 | struct pci_controller *controller = irq_desc_get_handler_data(desc); | |
241 | gxio_trio_context_t *trio_context = controller->trio; | |
242 | uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc); | |
243 | int mac = controller->mac; | |
244 | unsigned int reg_offset; | |
245 | uint64_t level_mask; | |
246 | ||
247 | handle_level_irq(irq, desc); | |
248 | ||
249 | /* | |
250 | * Clear the INTx Level status, otherwise future interrupts are | |
251 | * not sent. | |
252 | */ | |
253 | reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS << | |
254 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
255 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
256 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
257 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
258 | ||
259 | level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx; | |
260 | ||
261 | __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask); | |
262 | } | |
263 | ||
264 | /* | |
265 | * Create kernel irqs and set up the handlers for the legacy interrupts. | |
266 | * Also some minimum initialization for the MSI support. | |
267 | */ | |
268 | static int __devinit tile_init_irqs(struct pci_controller *controller) | |
269 | { | |
270 | int i; | |
271 | int j; | |
272 | int irq; | |
273 | int result; | |
274 | ||
275 | cpumask_copy(&intr_cpus_map, cpu_online_mask); | |
276 | ||
277 | ||
278 | for (i = 0; i < 4; i++) { | |
279 | gxio_trio_context_t *context = controller->trio; | |
280 | int cpu; | |
281 | ||
282 | /* Ask the kernel to allocate an IRQ. */ | |
283 | irq = create_irq(); | |
284 | if (irq < 0) { | |
285 | pr_err("PCI: no free irq vectors, failed for %d\n", i); | |
286 | ||
287 | goto free_irqs; | |
288 | } | |
289 | controller->irq_intx_table[i] = irq; | |
290 | ||
291 | /* Distribute the 4 IRQs to different tiles. */ | |
292 | cpu = tile_irq_cpu(irq); | |
293 | ||
294 | /* Configure the TRIO intr binding for this IRQ. */ | |
295 | result = gxio_trio_config_legacy_intr(context, cpu_x(cpu), | |
296 | cpu_y(cpu), KERNEL_PL, | |
297 | irq, controller->mac, i); | |
298 | if (result < 0) { | |
299 | pr_err("PCI: MAC intx config failed for %d\n", i); | |
300 | ||
301 | goto free_irqs; | |
302 | } | |
303 | ||
304 | /* | |
305 | * Register the IRQ handler with the kernel. | |
306 | */ | |
307 | irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip, | |
308 | trio_handle_level_irq); | |
309 | irq_set_chip_data(irq, (void *)(uint64_t)i); | |
310 | irq_set_handler_data(irq, controller); | |
311 | } | |
312 | ||
313 | return 0; | |
314 | ||
315 | free_irqs: | |
316 | for (j = 0; j < i; j++) | |
317 | destroy_irq(controller->irq_intx_table[j]); | |
318 | ||
319 | return -1; | |
320 | } | |
321 | ||
322 | /* | |
12962267 CM |
323 | * Find valid controllers and fill in pci_controller structs for each |
324 | * of them. | |
325 | * | |
326 | * Returns the number of controllers discovered. | |
327 | */ | |
328 | int __init tile_pci_init(void) | |
329 | { | |
330 | int num_trio_shims = 0; | |
331 | int ctl_index = 0; | |
332 | int i, j; | |
333 | ||
334 | if (!pci_probe) { | |
335 | pr_info("PCI: disabled by boot argument\n"); | |
336 | return 0; | |
337 | } | |
338 | ||
339 | pr_info("PCI: Searching for controllers...\n"); | |
340 | ||
341 | /* | |
342 | * We loop over all the TRIO shims. | |
343 | */ | |
344 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { | |
345 | int ret; | |
346 | ||
347 | ret = tile_pcie_open(i); | |
348 | if (ret < 0) | |
349 | continue; | |
350 | ||
351 | num_trio_shims++; | |
352 | } | |
353 | ||
354 | if (num_trio_shims == 0 || sim_is_simulator()) | |
355 | return 0; | |
356 | ||
357 | /* | |
358 | * Now determine which PCIe ports are configured to operate in RC mode. | |
359 | * We look at the Board Information Block first and then see if there | |
360 | * are any overriding configuration by the HW strapping pin. | |
361 | */ | |
362 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { | |
363 | gxio_trio_context_t *context = &trio_contexts[i]; | |
364 | int ret; | |
365 | ||
366 | if (context->fd < 0) | |
367 | continue; | |
368 | ||
369 | ret = hv_dev_pread(context->fd, 0, | |
370 | (HV_VirtAddr)&pcie_ports[i][0], | |
371 | sizeof(struct pcie_port_property) * TILEGX_TRIO_PCIES, | |
372 | GXIO_TRIO_OP_GET_PORT_PROPERTY); | |
373 | if (ret < 0) { | |
374 | pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d," | |
375 | " on TRIO %d\n", ret, i); | |
376 | continue; | |
377 | } | |
378 | ||
379 | for (j = 0; j < TILEGX_TRIO_PCIES; j++) { | |
380 | if (pcie_ports[i][j].allow_rc) { | |
381 | pcie_rc[i][j] = 1; | |
382 | num_rc_controllers++; | |
383 | } | |
384 | else if (pcie_ports[i][j].allow_ep) { | |
385 | num_ep_controllers++; | |
386 | } | |
387 | } | |
388 | } | |
389 | ||
390 | /* | |
391 | * Return if no PCIe ports are configured to operate in RC mode. | |
392 | */ | |
393 | if (num_rc_controllers == 0) | |
394 | return 0; | |
395 | ||
396 | /* | |
397 | * Set the TRIO pointer and MAC index for each PCIe RC port. | |
398 | */ | |
399 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { | |
400 | for (j = 0; j < TILEGX_TRIO_PCIES; j++) { | |
401 | if (pcie_rc[i][j]) { | |
402 | pci_controllers[ctl_index].trio = | |
403 | &trio_contexts[i]; | |
404 | pci_controllers[ctl_index].mac = j; | |
405 | pci_controllers[ctl_index].trio_index = i; | |
406 | ctl_index++; | |
407 | if (ctl_index == num_rc_controllers) | |
408 | goto out; | |
409 | } | |
410 | } | |
411 | } | |
412 | ||
413 | out: | |
414 | /* | |
415 | * Configure each PCIe RC port. | |
416 | */ | |
417 | for (i = 0; i < num_rc_controllers; i++) { | |
418 | /* | |
419 | * Configure the PCIe MAC to run in RC mode. | |
420 | */ | |
421 | ||
422 | struct pci_controller *controller = &pci_controllers[i]; | |
423 | ||
424 | controller->index = i; | |
12962267 CM |
425 | controller->ops = &tile_cfg_ops; |
426 | ||
f6d2ce00 CM |
427 | /* |
428 | * The PCI memory resource is located above the PA space. | |
429 | * For every host bridge, the BAR window or the MMIO aperture | |
430 | * is in range [3GB, 4GB - 1] of a 4GB space beyond the | |
431 | * PA space. | |
432 | */ | |
433 | ||
434 | controller->mem_offset = TILE_PCI_MEM_START + | |
435 | (i * TILE_PCI_BAR_WINDOW_TOP); | |
436 | controller->mem_space.start = controller->mem_offset + | |
437 | TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE; | |
438 | controller->mem_space.end = controller->mem_offset + | |
439 | TILE_PCI_BAR_WINDOW_TOP - 1; | |
440 | controller->mem_space.flags = IORESOURCE_MEM; | |
441 | snprintf(controller->mem_space_name, | |
442 | sizeof(controller->mem_space_name), | |
443 | "PCI mem domain %d", i); | |
444 | controller->mem_space.name = controller->mem_space_name; | |
12962267 CM |
445 | } |
446 | ||
447 | return num_rc_controllers; | |
448 | } | |
449 | ||
450 | /* | |
451 | * (pin - 1) converts from the PCI standard's [1:4] convention to | |
452 | * a normal [0:3] range. | |
453 | */ | |
454 | static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin) | |
455 | { | |
456 | struct pci_controller *controller = | |
457 | (struct pci_controller *)dev->sysdata; | |
458 | return controller->irq_intx_table[pin - 1]; | |
459 | } | |
460 | ||
461 | ||
462 | static void __devinit fixup_read_and_payload_sizes(struct pci_controller * | |
463 | controller) | |
464 | { | |
465 | gxio_trio_context_t *trio_context = controller->trio; | |
466 | struct pci_bus *root_bus = controller->root_bus; | |
467 | TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control; | |
468 | TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap; | |
469 | unsigned int reg_offset; | |
470 | struct pci_bus *child; | |
471 | int mac; | |
472 | int err; | |
473 | ||
474 | mac = controller->mac; | |
475 | ||
476 | /* | |
477 | * Set our max read request size to be 4KB. | |
478 | */ | |
479 | reg_offset = | |
480 | (TRIO_PCIE_RC_DEVICE_CONTROL << | |
481 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
482 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
483 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
484 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
485 | ||
486 | dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac + | |
487 | reg_offset); | |
488 | dev_control.max_read_req_sz = 5; | |
489 | __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, | |
490 | dev_control.word); | |
491 | ||
492 | /* | |
493 | * Set the max payload size supported by this Gx PCIe MAC. | |
494 | * Though Gx PCIe supports Max Payload Size of up to 1024 bytes, | |
495 | * experiments have shown that setting MPS to 256 yields the | |
496 | * best performance. | |
497 | */ | |
498 | reg_offset = | |
499 | (TRIO_PCIE_RC_DEVICE_CAP << | |
500 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
501 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
502 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
503 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
504 | ||
505 | rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac + | |
506 | reg_offset); | |
507 | rc_dev_cap.mps_sup = 1; | |
508 | __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, | |
509 | rc_dev_cap.word); | |
510 | ||
511 | /* Configure PCI Express MPS setting. */ | |
512 | list_for_each_entry(child, &root_bus->children, node) { | |
513 | struct pci_dev *self = child->self; | |
514 | if (!self) | |
515 | continue; | |
516 | ||
517 | pcie_bus_configure_settings(child, self->pcie_mpss); | |
518 | } | |
519 | ||
520 | /* | |
521 | * Set the mac_config register in trio based on the MPS/MRS of the link. | |
522 | */ | |
523 | reg_offset = | |
524 | (TRIO_PCIE_RC_DEVICE_CONTROL << | |
525 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
526 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
527 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
528 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
529 | ||
530 | dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac + | |
531 | reg_offset); | |
532 | ||
533 | err = gxio_trio_set_mps_mrs(trio_context, | |
534 | dev_control.max_payload_size, | |
535 | dev_control.max_read_req_sz, | |
536 | mac); | |
537 | if (err < 0) { | |
538 | pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, " | |
539 | "MAC %d on TRIO %d\n", | |
540 | mac, controller->trio_index); | |
541 | } | |
542 | } | |
543 | ||
544 | static int __devinit setup_pcie_rc_delay(char *str) | |
545 | { | |
546 | unsigned long delay = 0; | |
547 | unsigned long trio_index; | |
548 | unsigned long mac; | |
549 | ||
550 | if (str == NULL || !isdigit(*str)) | |
551 | return -EINVAL; | |
552 | trio_index = simple_strtoul(str, (char **)&str, 10); | |
553 | if (trio_index >= TILEGX_NUM_TRIO) | |
554 | return -EINVAL; | |
555 | ||
556 | if (*str != ',') | |
557 | return -EINVAL; | |
558 | ||
559 | str++; | |
560 | if (!isdigit(*str)) | |
561 | return -EINVAL; | |
562 | mac = simple_strtoul(str, (char **)&str, 10); | |
563 | if (mac >= TILEGX_TRIO_PCIES) | |
564 | return -EINVAL; | |
565 | ||
566 | if (*str != '\0') { | |
567 | if (*str != ',') | |
568 | return -EINVAL; | |
569 | ||
570 | str++; | |
571 | if (!isdigit(*str)) | |
572 | return -EINVAL; | |
573 | delay = simple_strtoul(str, (char **)&str, 10); | |
574 | if (delay > MAX_RC_DELAY) | |
575 | return -EINVAL; | |
576 | } | |
577 | ||
578 | rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY; | |
579 | pr_info("Delaying PCIe RC link training for %u sec" | |
580 | " on MAC %lu on TRIO %lu\n", rc_delay[trio_index][mac], | |
581 | mac, trio_index); | |
582 | return 0; | |
583 | } | |
584 | early_param("pcie_rc_delay", setup_pcie_rc_delay); | |
585 | ||
586 | /* | |
41bb38fc | 587 | * PCI initialization entry point, called by subsys_initcall. |
12962267 CM |
588 | */ |
589 | int __init pcibios_init(void) | |
590 | { | |
591 | resource_size_t offset; | |
592 | LIST_HEAD(resources); | |
f6d2ce00 | 593 | int next_busno; |
12962267 CM |
594 | int i; |
595 | ||
41bb38fc CM |
596 | tile_pci_init(); |
597 | ||
12962267 CM |
598 | if (num_rc_controllers == 0 && num_ep_controllers == 0) |
599 | return 0; | |
600 | ||
12962267 CM |
601 | /* |
602 | * We loop over all the TRIO shims and set up the MMIO mappings. | |
12962267 CM |
603 | */ |
604 | for (i = 0; i < TILEGX_NUM_TRIO; i++) { | |
605 | gxio_trio_context_t *context = &trio_contexts[i]; | |
606 | ||
607 | if (context->fd < 0) | |
608 | continue; | |
609 | ||
610 | /* | |
611 | * Map in the MMIO space for the MAC. | |
612 | */ | |
613 | offset = 0; | |
614 | context->mmio_base_mac = | |
615 | iorpc_ioremap(context->fd, offset, | |
616 | HV_TRIO_CONFIG_IOREMAP_SIZE); | |
617 | if (context->mmio_base_mac == NULL) { | |
618 | pr_err("PCI: MAC map failure on TRIO %d\n", i); | |
619 | ||
620 | hv_dev_close(context->fd); | |
621 | context->fd = -1; | |
622 | continue; | |
623 | } | |
624 | } | |
625 | ||
626 | /* | |
627 | * Delay a bit in case devices aren't ready. Some devices are | |
628 | * known to require at least 20ms here, but we use a more | |
629 | * conservative value. | |
630 | */ | |
631 | msleep(250); | |
632 | ||
633 | /* Scan all of the recorded PCI controllers. */ | |
f6d2ce00 | 634 | for (next_busno = 0, i = 0; i < num_rc_controllers; i++) { |
12962267 CM |
635 | struct pci_controller *controller = &pci_controllers[i]; |
636 | gxio_trio_context_t *trio_context = controller->trio; | |
637 | TRIO_PCIE_INTFC_PORT_CONFIG_t port_config; | |
638 | TRIO_PCIE_INTFC_PORT_STATUS_t port_status; | |
639 | TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl; | |
640 | struct pci_bus *bus; | |
641 | unsigned int reg_offset; | |
642 | unsigned int class_code_revision; | |
643 | int trio_index; | |
644 | int mac; | |
12962267 | 645 | int ret; |
12962267 CM |
646 | |
647 | if (trio_context->fd < 0) | |
648 | continue; | |
649 | ||
650 | trio_index = controller->trio_index; | |
651 | mac = controller->mac; | |
652 | ||
653 | /* | |
654 | * Check the port strap state which will override the BIB | |
655 | * setting. | |
656 | */ | |
657 | ||
658 | reg_offset = | |
659 | (TRIO_PCIE_INTFC_PORT_CONFIG << | |
660 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
661 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
662 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
663 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
664 | ||
665 | port_config.word = | |
666 | __gxio_mmio_read(trio_context->mmio_base_mac + | |
667 | reg_offset); | |
668 | ||
669 | if ((port_config.strap_state != | |
670 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC) && | |
671 | (port_config.strap_state != | |
672 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1)) { | |
673 | /* | |
674 | * If this is really intended to be an EP port, | |
675 | * record it so that the endpoint driver will know about it. | |
676 | */ | |
677 | if (port_config.strap_state == | |
678 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT || | |
679 | port_config.strap_state == | |
680 | TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1) | |
681 | pcie_ports[trio_index][mac].allow_ep = 1; | |
682 | ||
683 | continue; | |
684 | } | |
685 | ||
686 | /* | |
687 | * Delay the RC link training if needed. | |
688 | */ | |
689 | if (rc_delay[trio_index][mac]) | |
690 | msleep(rc_delay[trio_index][mac] * 1000); | |
691 | ||
692 | ret = gxio_trio_force_rc_link_up(trio_context, mac); | |
693 | if (ret < 0) | |
694 | pr_err("PCI: PCIE_FORCE_LINK_UP failure, " | |
695 | "MAC %d on TRIO %d\n", mac, trio_index); | |
696 | ||
697 | pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i, | |
698 | trio_index, controller->mac); | |
699 | ||
700 | /* | |
701 | * Wait a bit here because some EP devices take longer | |
702 | * to come up. | |
703 | */ | |
704 | msleep(1000); | |
705 | ||
706 | /* | |
707 | * Check for PCIe link-up status. | |
708 | */ | |
709 | ||
710 | reg_offset = | |
711 | (TRIO_PCIE_INTFC_PORT_STATUS << | |
712 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
713 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
714 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
715 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
716 | ||
717 | port_status.word = | |
718 | __gxio_mmio_read(trio_context->mmio_base_mac + | |
719 | reg_offset); | |
720 | if (!port_status.dl_up) { | |
721 | pr_err("PCI: link is down, MAC %d on TRIO %d\n", | |
722 | mac, trio_index); | |
723 | continue; | |
724 | } | |
725 | ||
726 | /* | |
727 | * Ensure that the link can come out of L1 power down state. | |
728 | * Strictly speaking, this is needed only in the case of | |
729 | * heavy RC-initiated DMAs. | |
730 | */ | |
731 | reg_offset = | |
732 | (TRIO_PCIE_INTFC_TX_FIFO_CTL << | |
733 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
734 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << | |
735 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
736 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
737 | tx_fifo_ctl.word = | |
738 | __gxio_mmio_read(trio_context->mmio_base_mac + | |
739 | reg_offset); | |
740 | tx_fifo_ctl.min_p_credits = 0; | |
741 | __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, | |
742 | tx_fifo_ctl.word); | |
743 | ||
744 | /* | |
745 | * Change the device ID so that Linux bus crawl doesn't confuse | |
746 | * the internal bridge with any Tilera endpoints. | |
747 | */ | |
748 | ||
749 | reg_offset = | |
750 | (TRIO_PCIE_RC_DEVICE_ID_VEN_ID << | |
751 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
752 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
753 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
754 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
755 | ||
756 | __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, | |
757 | (TILERA_GX36_RC_DEV_ID << | |
758 | TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) | | |
759 | TILERA_VENDOR_ID); | |
760 | ||
761 | /* | |
762 | * Set the internal P2P bridge class code. | |
763 | */ | |
764 | ||
765 | reg_offset = | |
766 | (TRIO_PCIE_RC_REVISION_ID << | |
767 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
768 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << | |
769 | TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
770 | (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
771 | ||
772 | class_code_revision = | |
773 | __gxio_mmio_read32(trio_context->mmio_base_mac + | |
774 | reg_offset); | |
775 | class_code_revision = (class_code_revision & 0xff ) | | |
776 | (PCI_CLASS_BRIDGE_PCI << 16); | |
777 | ||
778 | __gxio_mmio_write32(trio_context->mmio_base_mac + | |
779 | reg_offset, class_code_revision); | |
780 | ||
781 | #ifdef USE_SHARED_PCIE_CONFIG_REGION | |
782 | ||
783 | /* | |
784 | * Map in the MMIO space for the PIO region. | |
785 | */ | |
786 | offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) | | |
787 | (((unsigned long long)mac) << | |
788 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT); | |
789 | ||
790 | #else | |
791 | ||
792 | /* | |
793 | * Alloc a PIO region for PCI config access per MAC. | |
794 | */ | |
795 | ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); | |
796 | if (ret < 0) { | |
797 | pr_err("PCI: PCI CFG PIO alloc failure for mac %d " | |
798 | "on TRIO %d, give up\n", mac, trio_index); | |
799 | ||
12962267 CM |
800 | continue; |
801 | } | |
802 | ||
803 | trio_context->pio_cfg_index[mac] = ret; | |
804 | ||
805 | /* | |
806 | * For PIO CFG, the bus_address_hi parameter is 0. | |
807 | */ | |
808 | ret = gxio_trio_init_pio_region_aux(trio_context, | |
809 | trio_context->pio_cfg_index[mac], | |
810 | mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE); | |
811 | if (ret < 0) { | |
812 | pr_err("PCI: PCI CFG PIO init failure for mac %d " | |
813 | "on TRIO %d, give up\n", mac, trio_index); | |
814 | ||
12962267 CM |
815 | continue; |
816 | } | |
817 | ||
818 | offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) | | |
819 | (((unsigned long long)mac) << | |
820 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT); | |
821 | ||
822 | #endif | |
823 | ||
824 | trio_context->mmio_base_pio_cfg[mac] = | |
825 | iorpc_ioremap(trio_context->fd, offset, | |
826 | (1 << TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT)); | |
827 | if (trio_context->mmio_base_pio_cfg[mac] == NULL) { | |
828 | pr_err("PCI: PIO map failure for mac %d on TRIO %d\n", | |
829 | mac, trio_index); | |
830 | ||
12962267 CM |
831 | continue; |
832 | } | |
833 | ||
834 | /* | |
835 | * Initialize the PCIe interrupts. | |
836 | */ | |
837 | if (tile_init_irqs(controller)) { | |
838 | pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n", | |
839 | mac, trio_index); | |
840 | ||
841 | continue; | |
842 | } | |
843 | ||
41bb38fc CM |
844 | /* |
845 | * The PCI memory resource is located above the PA space. | |
846 | * The memory range for the PCI root bus should not overlap | |
847 | * with the physical RAM | |
848 | */ | |
f6d2ce00 CM |
849 | pci_add_resource_offset(&resources, &controller->mem_space, |
850 | controller->mem_offset); | |
41bb38fc | 851 | |
f6d2ce00 CM |
852 | controller->first_busno = next_busno; |
853 | bus = pci_scan_root_bus(NULL, next_busno, controller->ops, | |
12962267 CM |
854 | controller, &resources); |
855 | controller->root_bus = bus; | |
d41ca6df | 856 | next_busno = bus->busn_res.end + 1; |
12962267 CM |
857 | |
858 | } | |
859 | ||
860 | /* Do machine dependent PCI interrupt routing */ | |
861 | pci_fixup_irqs(pci_common_swizzle, tile_map_irq); | |
862 | ||
863 | /* | |
864 | * This comes from the generic Linux PCI driver. | |
865 | * | |
866 | * It allocates all of the resources (I/O memory, etc) | |
867 | * associated with the devices read in above. | |
868 | */ | |
869 | ||
870 | pci_assign_unassigned_resources(); | |
871 | ||
872 | /* Record the I/O resources in the PCI controller structure. */ | |
873 | for (i = 0; i < num_rc_controllers; i++) { | |
874 | struct pci_controller *controller = &pci_controllers[i]; | |
875 | gxio_trio_context_t *trio_context = controller->trio; | |
876 | struct pci_bus *root_bus = pci_controllers[i].root_bus; | |
877 | struct pci_bus *next_bus; | |
878 | uint32_t bus_address_hi; | |
879 | struct pci_dev *dev; | |
880 | int ret; | |
881 | int j; | |
882 | ||
883 | /* | |
884 | * Skip controllers that are not properly initialized or | |
885 | * have down links. | |
886 | */ | |
887 | if (root_bus == NULL) | |
888 | continue; | |
889 | ||
890 | /* Configure the max_payload_size values for this domain. */ | |
891 | fixup_read_and_payload_sizes(controller); | |
892 | ||
893 | list_for_each_entry(dev, &root_bus->devices, bus_list) { | |
894 | /* Find the PCI host controller, ie. the 1st bridge. */ | |
895 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && | |
896 | (PCI_SLOT(dev->devfn) == 0)) { | |
897 | next_bus = dev->subordinate; | |
898 | pci_controllers[i].mem_resources[0] = | |
899 | *next_bus->resource[0]; | |
900 | pci_controllers[i].mem_resources[1] = | |
901 | *next_bus->resource[1]; | |
902 | pci_controllers[i].mem_resources[2] = | |
903 | *next_bus->resource[2]; | |
904 | ||
905 | break; | |
906 | } | |
907 | } | |
908 | ||
909 | if (pci_controllers[i].mem_resources[1].flags & IORESOURCE_MEM) | |
910 | bus_address_hi = | |
911 | pci_controllers[i].mem_resources[1].start >> 32; | |
912 | else if (pci_controllers[i].mem_resources[2].flags & IORESOURCE_PREFETCH) | |
913 | bus_address_hi = | |
914 | pci_controllers[i].mem_resources[2].start >> 32; | |
915 | else { | |
916 | /* This is unlikely. */ | |
917 | pr_err("PCI: no memory resources on TRIO %d mac %d\n", | |
918 | controller->trio_index, controller->mac); | |
919 | continue; | |
920 | } | |
921 | ||
12962267 CM |
922 | /* |
923 | * Alloc a PIO region for PCI memory access for each RC port. | |
924 | */ | |
925 | ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); | |
926 | if (ret < 0) { | |
927 | pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, " | |
928 | "give up\n", controller->trio_index, | |
929 | controller->mac); | |
930 | ||
12962267 CM |
931 | continue; |
932 | } | |
933 | ||
934 | controller->pio_mem_index = ret; | |
935 | ||
936 | /* | |
937 | * For PIO MEM, the bus_address_hi parameter is hard-coded 0 | |
938 | * because we always assign 32-bit PCI bus BAR ranges. | |
939 | */ | |
940 | ret = gxio_trio_init_pio_region_aux(trio_context, | |
941 | controller->pio_mem_index, | |
942 | controller->mac, | |
41bb38fc | 943 | 0, |
12962267 CM |
944 | 0); |
945 | if (ret < 0) { | |
946 | pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, " | |
947 | "give up\n", controller->trio_index, | |
948 | controller->mac); | |
949 | ||
12962267 CM |
950 | continue; |
951 | } | |
952 | ||
953 | /* | |
954 | * Configure a Mem-Map region for each memory controller so | |
955 | * that Linux can map all of its PA space to the PCI bus. | |
956 | * Use the IOMMU to handle hash-for-home memory. | |
957 | */ | |
958 | for_each_online_node(j) { | |
959 | unsigned long start_pfn = node_start_pfn[j]; | |
960 | unsigned long end_pfn = node_end_pfn[j]; | |
961 | unsigned long nr_pages = end_pfn - start_pfn; | |
962 | ||
963 | ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0, | |
964 | 0); | |
965 | if (ret < 0) { | |
966 | pr_err("PCI: Mem-Map alloc failure on TRIO %d " | |
967 | "mac %d for MC %d, give up\n", | |
968 | controller->trio_index, | |
969 | controller->mac, j); | |
970 | ||
12962267 CM |
971 | goto alloc_mem_map_failed; |
972 | } | |
973 | ||
974 | controller->mem_maps[j] = ret; | |
975 | ||
976 | /* | |
977 | * Initialize the Mem-Map and the I/O MMU so that all | |
978 | * the physical memory can be accessed by the endpoint | |
979 | * devices. The base bus address is set to the base CPA | |
41bb38fc CM |
980 | * of this memory controller plus an offset (see pci.h). |
981 | * The region's base VA is set to the base CPA. The | |
12962267 | 982 | * I/O MMU table essentially translates the CPA to |
41bb38fc CM |
983 | * the real PA. Implicitly, for node 0, we create |
984 | * a separate Mem-Map region that serves as the inbound | |
985 | * window for legacy 32-bit devices. This is a direct | |
986 | * map of the low 4GB CPA space. | |
12962267 CM |
987 | */ |
988 | ret = gxio_trio_init_memory_map_mmu_aux(trio_context, | |
989 | controller->mem_maps[j], | |
990 | start_pfn << PAGE_SHIFT, | |
991 | nr_pages << PAGE_SHIFT, | |
992 | trio_context->asid, | |
993 | controller->mac, | |
41bb38fc CM |
994 | (start_pfn << PAGE_SHIFT) + |
995 | TILE_PCI_MEM_MAP_BASE_OFFSET, | |
12962267 CM |
996 | j, |
997 | GXIO_TRIO_ORDER_MODE_UNORDERED); | |
998 | if (ret < 0) { | |
999 | pr_err("PCI: Mem-Map init failure on TRIO %d " | |
1000 | "mac %d for MC %d, give up\n", | |
1001 | controller->trio_index, | |
1002 | controller->mac, j); | |
1003 | ||
12962267 CM |
1004 | goto alloc_mem_map_failed; |
1005 | } | |
12962267 CM |
1006 | continue; |
1007 | ||
1008 | alloc_mem_map_failed: | |
1009 | break; | |
1010 | } | |
1011 | ||
1012 | } | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | subsys_initcall(pcibios_init); | |
1017 | ||
f6d2ce00 | 1018 | /* Note: to be deleted after Linux 3.6 merge. */ |
12962267 CM |
1019 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1020 | { | |
12962267 CM |
1021 | } |
1022 | ||
1023 | /* | |
1024 | * This can be called from the generic PCI layer, but doesn't need to | |
1025 | * do anything. | |
1026 | */ | |
1027 | char __devinit *pcibios_setup(char *str) | |
1028 | { | |
1029 | if (!strcmp(str, "off")) { | |
1030 | pci_probe = 0; | |
1031 | return NULL; | |
1032 | } | |
1033 | return str; | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * This is called from the generic Linux layer. | |
1038 | */ | |
1039 | void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) | |
1040 | { | |
1041 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
1042 | } | |
1043 | ||
1044 | /* | |
1045 | * Enable memory address decoding, as appropriate, for the | |
1046 | * device described by the 'dev' struct. The I/O decoding | |
1047 | * is disabled, though the TILE-Gx supports I/O addressing. | |
1048 | * | |
1049 | * This is called from the generic PCI layer, and can be called | |
1050 | * for bridges or endpoints. | |
1051 | */ | |
1052 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
1053 | { | |
1054 | return pci_enable_resources(dev, mask); | |
1055 | } | |
1056 | ||
41bb38fc CM |
1057 | /* Called for each device after PCI setup is done. */ |
1058 | static void __init | |
1059 | pcibios_fixup_final(struct pci_dev *pdev) | |
1060 | { | |
1061 | set_dma_ops(&pdev->dev, gx_pci_dma_map_ops); | |
1062 | set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET); | |
1063 | pdev->dev.archdata.max_direct_dma_addr = | |
1064 | TILE_PCI_MAX_DIRECT_DMA_ADDRESS; | |
1065 | } | |
1066 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final); | |
1067 | ||
12962267 CM |
1068 | /* Map a PCI MMIO bus address into VA space. */ |
1069 | void __iomem *ioremap(resource_size_t phys_addr, unsigned long size) | |
1070 | { | |
1071 | struct pci_controller *controller = NULL; | |
1072 | resource_size_t bar_start; | |
1073 | resource_size_t bar_end; | |
1074 | resource_size_t offset; | |
1075 | resource_size_t start; | |
1076 | resource_size_t end; | |
1077 | int trio_fd; | |
1078 | int i, j; | |
1079 | ||
1080 | start = phys_addr; | |
1081 | end = phys_addr + size - 1; | |
1082 | ||
1083 | /* | |
1084 | * In the following, each PCI controller's mem_resources[1] | |
1085 | * represents its (non-prefetchable) PCI memory resource and | |
1086 | * mem_resources[2] refers to its prefetchable PCI memory resource. | |
1087 | * By searching phys_addr in each controller's mem_resources[], we can | |
1088 | * determine the controller that should accept the PCI memory access. | |
1089 | */ | |
1090 | ||
1091 | for (i = 0; i < num_rc_controllers; i++) { | |
1092 | /* | |
1093 | * Skip controllers that are not properly initialized or | |
1094 | * have down links. | |
1095 | */ | |
1096 | if (pci_controllers[i].root_bus == NULL) | |
1097 | continue; | |
1098 | ||
1099 | for (j = 1; j < 3; j++) { | |
1100 | bar_start = | |
1101 | pci_controllers[i].mem_resources[j].start; | |
1102 | bar_end = | |
1103 | pci_controllers[i].mem_resources[j].end; | |
1104 | ||
1105 | if ((start >= bar_start) && (end <= bar_end)) { | |
1106 | ||
1107 | controller = &pci_controllers[i]; | |
1108 | ||
1109 | goto got_it; | |
1110 | } | |
1111 | } | |
1112 | } | |
1113 | ||
1114 | if (controller == NULL) | |
1115 | return NULL; | |
1116 | ||
1117 | got_it: | |
1118 | trio_fd = controller->trio->fd; | |
1119 | ||
f6d2ce00 CM |
1120 | /* Convert the resource start to the bus address offset. */ |
1121 | start = phys_addr - controller->mem_offset; | |
1122 | ||
1123 | offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start; | |
12962267 CM |
1124 | |
1125 | /* | |
1126 | * We need to keep the PCI bus address's in-page offset in the VA. | |
1127 | */ | |
1128 | return iorpc_ioremap(trio_fd, offset, size) + | |
41bb38fc | 1129 | (phys_addr & (PAGE_SIZE - 1)); |
12962267 CM |
1130 | } |
1131 | EXPORT_SYMBOL(ioremap); | |
1132 | ||
1133 | void pci_iounmap(struct pci_dev *dev, void __iomem *addr) | |
1134 | { | |
1135 | iounmap(addr); | |
1136 | } | |
1137 | EXPORT_SYMBOL(pci_iounmap); | |
1138 | ||
1139 | /**************************************************************** | |
1140 | * | |
1141 | * Tile PCI config space read/write routines | |
1142 | * | |
1143 | ****************************************************************/ | |
1144 | ||
1145 | /* | |
1146 | * These are the normal read and write ops | |
1147 | * These are expanded with macros from pci_bus_read_config_byte() etc. | |
1148 | * | |
1149 | * devfn is the combined PCI device & function. | |
1150 | * | |
1151 | * offset is in bytes, from the start of config space for the | |
1152 | * specified bus & device. | |
1153 | */ | |
1154 | ||
1155 | static int __devinit tile_cfg_read(struct pci_bus *bus, | |
1156 | unsigned int devfn, | |
1157 | int offset, | |
1158 | int size, | |
1159 | u32 *val) | |
1160 | { | |
1161 | struct pci_controller *controller = bus->sysdata; | |
1162 | gxio_trio_context_t *trio_context = controller->trio; | |
1163 | int busnum = bus->number & 0xff; | |
1164 | int device = PCI_SLOT(devfn); | |
1165 | int function = PCI_FUNC(devfn); | |
1166 | int config_type = 1; | |
1167 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr; | |
1168 | void *mmio_addr; | |
1169 | ||
1170 | /* | |
f6d2ce00 | 1171 | * Map all accesses to the local device on root bus into the |
12962267 CM |
1172 | * MMIO space of the MAC. Accesses to the downstream devices |
1173 | * go to the PIO space. | |
1174 | */ | |
f6d2ce00 | 1175 | if (pci_is_root_bus(bus)) { |
12962267 CM |
1176 | if (device == 0) { |
1177 | /* | |
1178 | * This is the internal downstream P2P bridge, | |
1179 | * access directly. | |
1180 | */ | |
1181 | unsigned int reg_offset; | |
1182 | ||
1183 | reg_offset = ((offset & 0xFFF) << | |
1184 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
1185 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED | |
1186 | << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
1187 | (controller->mac << | |
1188 | TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
1189 | ||
1190 | mmio_addr = trio_context->mmio_base_mac + reg_offset; | |
1191 | ||
1192 | goto valid_device; | |
1193 | ||
1194 | } else { | |
1195 | /* | |
1196 | * We fake an empty device for (device > 0), | |
1197 | * since there is only one device on bus 0. | |
1198 | */ | |
1199 | goto invalid_device; | |
1200 | } | |
1201 | } | |
1202 | ||
1203 | /* | |
f6d2ce00 | 1204 | * Accesses to the directly attached device have to be |
12962267 CM |
1205 | * sent as type-0 configs. |
1206 | */ | |
1207 | ||
f6d2ce00 | 1208 | if (busnum == (controller->first_busno + 1)) { |
12962267 CM |
1209 | /* |
1210 | * There is only one device off of our built-in P2P bridge. | |
1211 | */ | |
1212 | if (device != 0) | |
1213 | goto invalid_device; | |
1214 | ||
1215 | config_type = 0; | |
1216 | } | |
1217 | ||
1218 | cfg_addr.word = 0; | |
1219 | cfg_addr.reg_addr = (offset & 0xFFF); | |
1220 | cfg_addr.fn = function; | |
1221 | cfg_addr.dev = device; | |
1222 | cfg_addr.bus = busnum; | |
1223 | cfg_addr.type = config_type; | |
1224 | ||
1225 | /* | |
1226 | * Note that we don't set the mac field in cfg_addr because the | |
1227 | * mapping is per port. | |
1228 | */ | |
1229 | ||
1230 | mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] + | |
1231 | cfg_addr.word; | |
1232 | ||
1233 | valid_device: | |
1234 | ||
1235 | switch (size) { | |
1236 | case 4: | |
1237 | *val = __gxio_mmio_read32(mmio_addr); | |
1238 | break; | |
1239 | ||
1240 | case 2: | |
1241 | *val = __gxio_mmio_read16(mmio_addr); | |
1242 | break; | |
1243 | ||
1244 | case 1: | |
1245 | *val = __gxio_mmio_read8(mmio_addr); | |
1246 | break; | |
1247 | ||
1248 | default: | |
1249 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
1250 | } | |
1251 | ||
1252 | TRACE_CFG_RD(size, *val, busnum, device, function, offset); | |
1253 | ||
1254 | return 0; | |
1255 | ||
1256 | invalid_device: | |
1257 | ||
1258 | switch (size) { | |
1259 | case 4: | |
1260 | *val = 0xFFFFFFFF; | |
1261 | break; | |
1262 | ||
1263 | case 2: | |
1264 | *val = 0xFFFF; | |
1265 | break; | |
1266 | ||
1267 | case 1: | |
1268 | *val = 0xFF; | |
1269 | break; | |
1270 | ||
1271 | default: | |
1272 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
1273 | } | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | ||
1279 | /* | |
1280 | * See tile_cfg_read() for relevent comments. | |
1281 | * Note that "val" is the value to write, not a pointer to that value. | |
1282 | */ | |
1283 | static int __devinit tile_cfg_write(struct pci_bus *bus, | |
1284 | unsigned int devfn, | |
1285 | int offset, | |
1286 | int size, | |
1287 | u32 val) | |
1288 | { | |
1289 | struct pci_controller *controller = bus->sysdata; | |
1290 | gxio_trio_context_t *trio_context = controller->trio; | |
1291 | int busnum = bus->number & 0xff; | |
1292 | int device = PCI_SLOT(devfn); | |
1293 | int function = PCI_FUNC(devfn); | |
1294 | int config_type = 1; | |
1295 | TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr; | |
1296 | void *mmio_addr; | |
1297 | u32 val_32 = (u32)val; | |
1298 | u16 val_16 = (u16)val; | |
1299 | u8 val_8 = (u8)val; | |
1300 | ||
1301 | /* | |
f6d2ce00 | 1302 | * Map all accesses to the local device on root bus into the |
12962267 CM |
1303 | * MMIO space of the MAC. Accesses to the downstream devices |
1304 | * go to the PIO space. | |
1305 | */ | |
f6d2ce00 | 1306 | if (pci_is_root_bus(bus)) { |
12962267 CM |
1307 | if (device == 0) { |
1308 | /* | |
1309 | * This is the internal downstream P2P bridge, | |
1310 | * access directly. | |
1311 | */ | |
1312 | unsigned int reg_offset; | |
1313 | ||
1314 | reg_offset = ((offset & 0xFFF) << | |
1315 | TRIO_CFG_REGION_ADDR__REG_SHIFT) | | |
1316 | (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED | |
1317 | << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | | |
1318 | (controller->mac << | |
1319 | TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); | |
1320 | ||
1321 | mmio_addr = trio_context->mmio_base_mac + reg_offset; | |
1322 | ||
1323 | goto valid_device; | |
1324 | ||
1325 | } else { | |
1326 | /* | |
1327 | * We fake an empty device for (device > 0), | |
1328 | * since there is only one device on bus 0. | |
1329 | */ | |
1330 | goto invalid_device; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | /* | |
f6d2ce00 | 1335 | * Accesses to the directly attached device have to be |
12962267 CM |
1336 | * sent as type-0 configs. |
1337 | */ | |
1338 | ||
f6d2ce00 | 1339 | if (busnum == (controller->first_busno + 1)) { |
12962267 CM |
1340 | /* |
1341 | * There is only one device off of our built-in P2P bridge. | |
1342 | */ | |
1343 | if (device != 0) | |
1344 | goto invalid_device; | |
1345 | ||
1346 | config_type = 0; | |
1347 | } | |
1348 | ||
1349 | cfg_addr.word = 0; | |
1350 | cfg_addr.reg_addr = (offset & 0xFFF); | |
1351 | cfg_addr.fn = function; | |
1352 | cfg_addr.dev = device; | |
1353 | cfg_addr.bus = busnum; | |
1354 | cfg_addr.type = config_type; | |
1355 | ||
1356 | /* | |
1357 | * Note that we don't set the mac field in cfg_addr because the | |
1358 | * mapping is per port. | |
1359 | */ | |
1360 | ||
1361 | mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] + | |
1362 | cfg_addr.word; | |
1363 | ||
1364 | valid_device: | |
1365 | ||
1366 | switch (size) { | |
1367 | case 4: | |
1368 | __gxio_mmio_write32(mmio_addr, val_32); | |
1369 | TRACE_CFG_WR(size, val_32, busnum, device, function, offset); | |
1370 | break; | |
1371 | ||
1372 | case 2: | |
1373 | __gxio_mmio_write16(mmio_addr, val_16); | |
1374 | TRACE_CFG_WR(size, val_16, busnum, device, function, offset); | |
1375 | break; | |
1376 | ||
1377 | case 1: | |
1378 | __gxio_mmio_write8(mmio_addr, val_8); | |
1379 | TRACE_CFG_WR(size, val_8, busnum, device, function, offset); | |
1380 | break; | |
1381 | ||
1382 | default: | |
1383 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
1384 | } | |
1385 | ||
1386 | invalid_device: | |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | ||
1392 | static struct pci_ops tile_cfg_ops = { | |
1393 | .read = tile_cfg_read, | |
1394 | .write = tile_cfg_write, | |
1395 | }; | |
1396 | ||
1397 | ||
1398 | /* | |
1399 | * MSI support starts here. | |
1400 | */ | |
1401 | static unsigned int | |
1402 | tilegx_msi_startup(struct irq_data *d) | |
1403 | { | |
1404 | if (d->msi_desc) | |
1405 | unmask_msi_irq(d); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | static void | |
1411 | tilegx_msi_ack(struct irq_data *d) | |
1412 | { | |
1413 | __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq); | |
1414 | } | |
1415 | ||
1416 | static void | |
1417 | tilegx_msi_mask(struct irq_data *d) | |
1418 | { | |
1419 | mask_msi_irq(d); | |
1420 | __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq); | |
1421 | } | |
1422 | ||
1423 | static void | |
1424 | tilegx_msi_unmask(struct irq_data *d) | |
1425 | { | |
1426 | __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq); | |
1427 | unmask_msi_irq(d); | |
1428 | } | |
1429 | ||
1430 | static struct irq_chip tilegx_msi_chip = { | |
1431 | .name = "tilegx_msi", | |
1432 | .irq_startup = tilegx_msi_startup, | |
1433 | .irq_ack = tilegx_msi_ack, | |
1434 | .irq_mask = tilegx_msi_mask, | |
1435 | .irq_unmask = tilegx_msi_unmask, | |
1436 | ||
1437 | /* TBD: support set_affinity. */ | |
1438 | }; | |
1439 | ||
1440 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1441 | { | |
1442 | struct pci_controller *controller; | |
1443 | gxio_trio_context_t *trio_context; | |
1444 | struct msi_msg msg; | |
1445 | int default_irq; | |
1446 | uint64_t mem_map_base; | |
1447 | uint64_t mem_map_limit; | |
1448 | u64 msi_addr; | |
1449 | int mem_map; | |
1450 | int cpu; | |
1451 | int irq; | |
1452 | int ret; | |
1453 | ||
1454 | irq = create_irq(); | |
1455 | if (irq < 0) | |
1456 | return irq; | |
1457 | ||
1458 | /* | |
1459 | * Since we use a 64-bit Mem-Map to accept the MSI write, we fail | |
1460 | * devices that are not capable of generating a 64-bit message address. | |
1461 | * These devices will fall back to using the legacy interrupts. | |
1462 | * Most PCIe endpoint devices do support 64-bit message addressing. | |
1463 | */ | |
1464 | if (desc->msi_attrib.is_64 == 0) { | |
1465 | dev_printk(KERN_INFO, &pdev->dev, | |
1466 | "64-bit MSI message address not supported, " | |
1467 | "falling back to legacy interrupts.\n"); | |
1468 | ||
1469 | ret = -ENOMEM; | |
1470 | goto is_64_failure; | |
1471 | } | |
1472 | ||
1473 | default_irq = desc->msi_attrib.default_irq; | |
1474 | controller = irq_get_handler_data(default_irq); | |
1475 | ||
1476 | BUG_ON(!controller); | |
1477 | ||
1478 | trio_context = controller->trio; | |
1479 | ||
1480 | /* | |
1481 | * Allocate the Mem-Map that will accept the MSI write and | |
1482 | * trigger the TILE-side interrupts. | |
1483 | */ | |
1484 | mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0); | |
1485 | if (mem_map < 0) { | |
1486 | dev_printk(KERN_INFO, &pdev->dev, | |
1487 | "%s Mem-Map alloc failure. " | |
1488 | "Failed to initialize MSI interrupts. " | |
1489 | "Falling back to legacy interrupts.\n", | |
1490 | desc->msi_attrib.is_msix ? "MSI-X" : "MSI"); | |
1491 | ||
1492 | ret = -ENOMEM; | |
1493 | goto msi_mem_map_alloc_failure; | |
1494 | } | |
1495 | ||
1496 | /* We try to distribute different IRQs to different tiles. */ | |
1497 | cpu = tile_irq_cpu(irq); | |
1498 | ||
1499 | /* | |
1500 | * Now call up to the HV to configure the Mem-Map interrupt and | |
1501 | * set up the IPI binding. | |
1502 | */ | |
1503 | mem_map_base = MEM_MAP_INTR_REGIONS_BASE + | |
1504 | mem_map * MEM_MAP_INTR_REGION_SIZE; | |
1505 | mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1; | |
1506 | ||
1507 | ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu), | |
1508 | KERNEL_PL, irq, controller->mac, | |
1509 | mem_map, mem_map_base, mem_map_limit, | |
1510 | trio_context->asid); | |
1511 | if (ret < 0) { | |
1512 | dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n"); | |
1513 | ||
1514 | goto hv_msi_config_failure; | |
1515 | } | |
1516 | ||
1517 | irq_set_msi_desc(irq, desc); | |
1518 | ||
1519 | msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 - TRIO_MAP_MEM_REG_INT0; | |
1520 | ||
1521 | msg.address_hi = msi_addr >> 32; | |
1522 | msg.address_lo = msi_addr & 0xffffffff; | |
1523 | ||
1524 | msg.data = mem_map; | |
1525 | ||
1526 | write_msi_msg(irq, &msg); | |
1527 | irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq); | |
1528 | irq_set_handler_data(irq, controller); | |
1529 | ||
1530 | return 0; | |
1531 | ||
1532 | hv_msi_config_failure: | |
1533 | /* Free mem-map */ | |
1534 | msi_mem_map_alloc_failure: | |
1535 | is_64_failure: | |
1536 | destroy_irq(irq); | |
1537 | return ret; | |
1538 | } | |
1539 | ||
1540 | void arch_teardown_msi_irq(unsigned int irq) | |
1541 | { | |
1542 | destroy_irq(irq); | |
1543 | } |