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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
96d55b88 | 2 | # Put here option for CPU selection and depending optimization |
96d55b88 PBG |
3 | choice |
4 | prompt "Processor family" | |
1032c0ba SR |
5 | default M686 if X86_32 |
6 | default GENERIC_CPU if X86_64 | |
96d55b88 | 7 | ---help--- |
eb068e78 PA |
8 | This is the processor type of your CPU. This information is |
9 | used for optimizing purposes. In order to compile a kernel | |
10 | that can run on all supported x86 CPU types (albeit not | |
11 | optimally fast), you can specify "486" here. | |
12 | ||
13 | Note that the 386 is no longer supported, this includes | |
14 | AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2, | |
11af32b6 | 15 | UMC 486SX-S and the NexGen Nx586. |
96d55b88 PBG |
16 | |
17 | The kernel will not necessarily run on earlier architectures than | |
18 | the one you have chosen, e.g. a Pentium optimized kernel will run on | |
19 | a PPro, but not necessarily on a i486. | |
20 | ||
21 | Here are the settings recommended for greatest speed: | |
96d55b88 | 22 | - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or |
221836e9 | 23 | SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. |
96d55b88 | 24 | - "586" for generic Pentium CPUs lacking the TSC |
221836e9 | 25 | (time stamp counter) register. |
96d55b88 PBG |
26 | - "Pentium-Classic" for the Intel Pentium. |
27 | - "Pentium-MMX" for the Intel Pentium MMX. | |
28 | - "Pentium-Pro" for the Intel Pentium Pro. | |
29 | - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. | |
30 | - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. | |
31 | - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. | |
32 | - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). | |
33 | - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). | |
221836e9 | 34 | - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs. |
96d55b88 PBG |
35 | - "Crusoe" for the Transmeta Crusoe series. |
36 | - "Efficeon" for the Transmeta Efficeon series. | |
37 | - "Winchip-C6" for original IDT Winchip. | |
69d45dd1 | 38 | - "Winchip-2" for IDT Winchips with 3dNow! capabilities. |
221836e9 | 39 | - "AMD Elan" for the 32-bit AMD Elan embedded CPU. |
96d55b88 | 40 | - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). |
f90b8116 | 41 | - "Geode GX/LX" For AMD Geode GX and LX processors. |
96d55b88 | 42 | - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. |
48a1204c | 43 | - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). |
0949be35 | 44 | - "VIA C7" for VIA C7. |
221836e9 BP |
45 | - "Intel P4" for the Pentium 4/Netburst microarchitecture. |
46 | - "Core 2/newer Xeon" for all core2 and newer Intel CPUs. | |
47 | - "Intel Atom" for the Atom-microarchitecture CPUs. | |
48 | - "Generic-x86-64" for a kernel which runs on any x86-64 CPU. | |
49 | ||
50 | See each option's help text for additional details. If you don't know | |
51 | what to do, choose "486". | |
96d55b88 | 52 | |
221836e9 BP |
53 | config M486 |
54 | bool "486" | |
55 | depends on X86_32 | |
56 | ---help--- | |
57 | Select this for an 486-class CPU such as AMD/Cyrix/IBM/Intel | |
58 | 486DX/DX2/DX4 or SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. | |
96d55b88 PBG |
59 | |
60 | config M586 | |
61 | bool "586/K5/5x86/6x86/6x86MX" | |
1032c0ba | 62 | depends on X86_32 |
8f9ca475 | 63 | ---help--- |
96d55b88 PBG |
64 | Select this for an 586 or 686 series processor such as the AMD K5, |
65 | the Cyrix 5x86, 6x86 and 6x86MX. This choice does not | |
66 | assume the RDTSC (Read Time Stamp Counter) instruction. | |
67 | ||
68 | config M586TSC | |
69 | bool "Pentium-Classic" | |
1032c0ba | 70 | depends on X86_32 |
8f9ca475 | 71 | ---help--- |
96d55b88 PBG |
72 | Select this for a Pentium Classic processor with the RDTSC (Read |
73 | Time Stamp Counter) instruction for benchmarking. | |
74 | ||
75 | config M586MMX | |
76 | bool "Pentium-MMX" | |
1032c0ba | 77 | depends on X86_32 |
8f9ca475 | 78 | ---help--- |
96d55b88 PBG |
79 | Select this for a Pentium with the MMX graphics/multimedia |
80 | extended instructions. | |
81 | ||
82 | config M686 | |
83 | bool "Pentium-Pro" | |
1032c0ba | 84 | depends on X86_32 |
8f9ca475 | 85 | ---help--- |
96d55b88 PBG |
86 | Select this for Intel Pentium Pro chips. This enables the use of |
87 | Pentium Pro extended instructions, and disables the init-time guard | |
88 | against the f00f bug found in earlier Pentiums. | |
89 | ||
90 | config MPENTIUMII | |
91 | bool "Pentium-II/Celeron(pre-Coppermine)" | |
1032c0ba | 92 | depends on X86_32 |
8f9ca475 | 93 | ---help--- |
96d55b88 PBG |
94 | Select this for Intel chips based on the Pentium-II and |
95 | pre-Coppermine Celeron core. This option enables an unaligned | |
96 | copy optimization, compiles the kernel with optimization flags | |
97 | tailored for the chip, and applies any applicable Pentium Pro | |
98 | optimizations. | |
99 | ||
100 | config MPENTIUMIII | |
101 | bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" | |
1032c0ba | 102 | depends on X86_32 |
8f9ca475 | 103 | ---help--- |
96d55b88 PBG |
104 | Select this for Intel chips based on the Pentium-III and |
105 | Celeron-Coppermine core. This option enables use of some | |
106 | extended prefetch instructions in addition to the Pentium II | |
107 | extensions. | |
108 | ||
109 | config MPENTIUMM | |
110 | bool "Pentium M" | |
1032c0ba | 111 | depends on X86_32 |
8f9ca475 | 112 | ---help--- |
96d55b88 PBG |
113 | Select this for Intel Pentium M (not Pentium-4 M) |
114 | notebook chips. | |
115 | ||
116 | config MPENTIUM4 | |
c55d92d1 | 117 | bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
1032c0ba | 118 | depends on X86_32 |
8f9ca475 | 119 | ---help--- |
96d55b88 | 120 | Select this for Intel Pentium 4 chips. This includes the |
75e3808b OP |
121 | Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
122 | Pentium-4 M (not Pentium M) chips. This option enables compile | |
123 | flags optimized for the chip, uses the correct cache line size, and | |
124 | applies any applicable optimizations. | |
125 | ||
126 | CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 ) | |
127 | ||
128 | Select this for: | |
129 | Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename: | |
130 | -Willamette | |
131 | -Northwood | |
132 | -Mobile Pentium 4 | |
133 | -Mobile Pentium 4 M | |
134 | -Extreme Edition (Gallatin) | |
135 | -Prescott | |
136 | -Prescott 2M | |
137 | -Cedar Mill | |
138 | -Presler | |
139 | -Smithfiled | |
140 | Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: | |
141 | -Foster | |
142 | -Prestonia | |
143 | -Gallatin | |
144 | -Nocona | |
145 | -Irwindale | |
146 | -Cranford | |
147 | -Potomac | |
148 | -Paxville | |
149 | -Dempsey | |
150 | ||
96d55b88 PBG |
151 | |
152 | config MK6 | |
153 | bool "K6/K6-II/K6-III" | |
1032c0ba | 154 | depends on X86_32 |
8f9ca475 | 155 | ---help--- |
96d55b88 PBG |
156 | Select this for an AMD K6-family processor. Enables use of |
157 | some extended instructions, and passes appropriate optimization | |
158 | flags to GCC. | |
159 | ||
160 | config MK7 | |
161 | bool "Athlon/Duron/K7" | |
1032c0ba | 162 | depends on X86_32 |
8f9ca475 | 163 | ---help--- |
96d55b88 PBG |
164 | Select this for an AMD Athlon K7-family processor. Enables use of |
165 | some extended instructions, and passes appropriate optimization | |
166 | flags to GCC. | |
167 | ||
168 | config MK8 | |
169 | bool "Opteron/Athlon64/Hammer/K8" | |
8f9ca475 | 170 | ---help--- |
36723bfe BP |
171 | Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
172 | Enables use of some extended instructions, and passes appropriate | |
173 | optimization flags to GCC. | |
96d55b88 PBG |
174 | |
175 | config MCRUSOE | |
176 | bool "Crusoe" | |
1032c0ba | 177 | depends on X86_32 |
8f9ca475 | 178 | ---help--- |
96d55b88 PBG |
179 | Select this for a Transmeta Crusoe processor. Treats the processor |
180 | like a 586 with TSC, and sets some GCC optimization flags (like a | |
181 | Pentium Pro with no alignment requirements). | |
182 | ||
183 | config MEFFICEON | |
184 | bool "Efficeon" | |
1032c0ba | 185 | depends on X86_32 |
8f9ca475 | 186 | ---help--- |
96d55b88 PBG |
187 | Select this for a Transmeta Efficeon processor. |
188 | ||
189 | config MWINCHIPC6 | |
190 | bool "Winchip-C6" | |
1032c0ba | 191 | depends on X86_32 |
8f9ca475 | 192 | ---help--- |
96d55b88 PBG |
193 | Select this for an IDT Winchip C6 chip. Linux and GCC |
194 | treat this chip as a 586TSC with some extended instructions | |
195 | and alignment requirements. | |
196 | ||
96d55b88 | 197 | config MWINCHIP3D |
69d45dd1 | 198 | bool "Winchip-2/Winchip-2A/Winchip-3" |
1032c0ba | 199 | depends on X86_32 |
8f9ca475 | 200 | ---help--- |
69d45dd1 | 201 | Select this for an IDT Winchip-2, 2A or 3. Linux and GCC |
96d55b88 | 202 | treat this chip as a 586TSC with some extended instructions |
3dde6ad8 | 203 | and alignment requirements. Also enable out of order memory |
96d55b88 PBG |
204 | stores for this CPU, which can increase performance of some |
205 | operations. | |
206 | ||
ce9c99af IC |
207 | config MELAN |
208 | bool "AMD Elan" | |
209 | depends on X86_32 | |
210 | ---help--- | |
211 | Select this for an AMD Elan processor. | |
212 | ||
213 | Do not use this option for K6/Athlon/Opteron processors! | |
214 | ||
96d55b88 PBG |
215 | config MGEODEGX1 |
216 | bool "GeodeGX1" | |
1032c0ba | 217 | depends on X86_32 |
8f9ca475 | 218 | ---help--- |
96d55b88 PBG |
219 | Select this for a Geode GX1 (Cyrix MediaGX) chip. |
220 | ||
f90b8116 | 221 | config MGEODE_LX |
96daa8cd | 222 | bool "Geode GX/LX" |
1032c0ba | 223 | depends on X86_32 |
8f9ca475 | 224 | ---help--- |
96daa8cd | 225 | Select this for AMD Geode GX and LX processors. |
f90b8116 | 226 | |
96d55b88 PBG |
227 | config MCYRIXIII |
228 | bool "CyrixIII/VIA-C3" | |
1032c0ba | 229 | depends on X86_32 |
8f9ca475 | 230 | ---help--- |
96d55b88 PBG |
231 | Select this for a Cyrix III or C3 chip. Presently Linux and GCC |
232 | treat this chip as a generic 586. Whilst the CPU is 686 class, | |
233 | it lacks the cmov extension which gcc assumes is present when | |
234 | generating 686 code. | |
235 | Note that Nehemiah (Model 9) and above will not boot with this | |
236 | kernel due to them lacking the 3DNow! instructions used in earlier | |
237 | incarnations of the CPU. | |
238 | ||
239 | config MVIAC3_2 | |
240 | bool "VIA C3-2 (Nehemiah)" | |
1032c0ba | 241 | depends on X86_32 |
8f9ca475 | 242 | ---help--- |
96d55b88 PBG |
243 | Select this for a VIA C3 "Nehemiah". Selecting this enables usage |
244 | of SSE and tells gcc to treat the CPU as a 686. | |
245 | Note, this kernel will not boot on older (pre model 9) C3s. | |
246 | ||
0949be35 SA |
247 | config MVIAC7 |
248 | bool "VIA C7" | |
1032c0ba | 249 | depends on X86_32 |
8f9ca475 | 250 | ---help--- |
0949be35 SA |
251 | Select this for a VIA C7. Selecting this uses the correct cache |
252 | shift and tells gcc to treat the CPU as a 686. | |
253 | ||
1032c0ba SR |
254 | config MPSC |
255 | bool "Intel P4 / older Netburst based Xeon" | |
256 | depends on X86_64 | |
8f9ca475 | 257 | ---help--- |
1032c0ba SR |
258 | Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
259 | Xeon CPUs with Intel 64bit which is compatible with x86-64. | |
260 | Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the | |
96daa8cd | 261 | Netburst core and shouldn't use this option. You can distinguish them |
1032c0ba SR |
262 | using the cpu family field |
263 | in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. | |
264 | ||
265 | config MCORE2 | |
266 | bool "Core 2/newer Xeon" | |
8f9ca475 | 267 | ---help--- |
36723bfe BP |
268 | |
269 | Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and | |
270 | 53xx) CPUs. You can distinguish newer from older Xeons by the CPU | |
271 | family in /proc/cpuinfo. Newer ones have 6 and older ones 15 | |
272 | (not a typo) | |
1032c0ba | 273 | |
366d19e1 TD |
274 | config MATOM |
275 | bool "Intel Atom" | |
276 | ---help--- | |
277 | ||
278 | Select this for the Intel Atom platform. Intel Atom CPUs have an | |
279 | in-order pipelining architecture and thus can benefit from | |
280 | accordingly optimized code. Use a recent GCC with specific Atom | |
281 | support in order to fully benefit from selecting this option. | |
282 | ||
1032c0ba SR |
283 | config GENERIC_CPU |
284 | bool "Generic-x86-64" | |
285 | depends on X86_64 | |
8f9ca475 | 286 | ---help--- |
1032c0ba SR |
287 | Generic x86-64 CPU. |
288 | Run equally well on all x86-64 CPUs. | |
289 | ||
96d55b88 PBG |
290 | endchoice |
291 | ||
292 | config X86_GENERIC | |
1032c0ba SR |
293 | bool "Generic x86 support" |
294 | depends on X86_32 | |
8f9ca475 | 295 | ---help--- |
96d55b88 PBG |
296 | Instead of just including optimizations for the selected |
297 | x86 variant (e.g. PII, Crusoe or Athlon), include some more | |
298 | generic optimizations as well. This will make the kernel | |
299 | perform better on x86 CPUs other than that selected. | |
300 | ||
301 | This is really intended for distributors who need more | |
302 | generic optimizations. | |
303 | ||
96d55b88 PBG |
304 | # |
305 | # Define implied options from the CPU selection here | |
350f8f56 | 306 | config X86_INTERNODE_CACHE_SHIFT |
1032c0ba | 307 | int |
350f8f56 | 308 | default "12" if X86_VSMP |
350f8f56 | 309 | default X86_L1_CACHE_SHIFT |
1032c0ba | 310 | |
96d55b88 PBG |
311 | config X86_L1_CACHE_SHIFT |
312 | int | |
0a2a18b7 | 313 | default "7" if MPENTIUM4 || MPSC |
350f8f56 | 314 | default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
eb068e78 | 315 | default "4" if MELAN || M486 || MGEODEGX1 |
69d45dd1 | 316 | default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
96d55b88 | 317 | |
96d55b88 | 318 | config X86_F00F_BUG |
96daa8cd | 319 | def_bool y |
eb068e78 | 320 | depends on M586MMX || M586TSC || M586 || M486 |
96d55b88 | 321 | |
40d2e763 BG |
322 | config X86_INVD_BUG |
323 | def_bool y | |
eb068e78 | 324 | depends on M486 |
40d2e763 | 325 | |
96d55b88 | 326 | config X86_ALIGNMENT_16 |
96daa8cd | 327 | def_bool y |
ce9c99af | 328 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 |
96d55b88 | 329 | |
96d55b88 | 330 | config X86_INTEL_USERCOPY |
96daa8cd | 331 | def_bool y |
c55d92d1 | 332 | depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
96d55b88 PBG |
333 | |
334 | config X86_USE_PPRO_CHECKSUM | |
96daa8cd | 335 | def_bool y |
1eda75c1 | 336 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
96d55b88 PBG |
337 | |
338 | config X86_USE_3DNOW | |
96daa8cd | 339 | def_bool y |
1b4ad242 | 340 | depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
96d55b88 | 341 | |
959b3be6 PA |
342 | # |
343 | # P6_NOPs are a relatively minor optimization that require a family >= | |
344 | # 6 processor, except that it is broken on certain VIA chips. | |
345 | # Furthermore, AMD chips prefer a totally different sequence of NOPs | |
14469a8d LT |
346 | # (which work on all CPUs). In addition, it looks like Virtual PC |
347 | # does not understand them. | |
348 | # | |
349 | # As a result, disallow these if we're not compiling for X86_64 (these | |
350 | # NOPs do work on all x86-64 capable chips); the list of processors in | |
351 | # the right-hand clause are the cores that benefit from this optimization. | |
959b3be6 | 352 | # |
7343b3b3 PA |
353 | config X86_P6_NOP |
354 | def_bool y | |
14469a8d LT |
355 | depends on X86_64 |
356 | depends on (MCORE2 || MPENTIUM4 || MPSC) | |
7343b3b3 | 357 | |
96d55b88 | 358 | config X86_TSC |
96daa8cd | 359 | def_bool y |
b5660ba7 | 360 | depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 |
c7f81c94 | 361 | |
f8096f92 JB |
362 | config X86_CMPXCHG64 |
363 | def_bool y | |
f960cfd1 | 364 | depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 |
f8096f92 | 365 | |
c7f81c94 AK |
366 | # this should be set for all -march=.. options where the compiler |
367 | # generates cmov. | |
368 | config X86_CMOV | |
96daa8cd | 369 | def_bool y |
98059e34 | 370 | depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) |
c7f81c94 | 371 | |
de32e041 | 372 | config X86_MINIMUM_CPU_FAMILY |
c7f81c94 | 373 | int |
1032c0ba | 374 | default "64" if X86_64 |
25d76ac8 | 375 | default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8) |
982d007a | 376 | default "5" if X86_32 && X86_CMPXCHG64 |
eb068e78 | 377 | default "4" |
c7f81c94 | 378 | |
0a049bb0 | 379 | config X86_DEBUGCTLMSR |
96daa8cd | 380 | def_bool y |
eb068e78 | 381 | depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486) && !UML |
8d02c211 TP |
382 | |
383 | menuconfig PROCESSOR_SELECT | |
6a108a14 | 384 | bool "Supported processor vendors" if EXPERT |
8f9ca475 | 385 | ---help--- |
8d02c211 TP |
386 | This lets you choose what x86 vendor support code your kernel |
387 | will include. | |
388 | ||
879d792b | 389 | config CPU_SUP_INTEL |
8d02c211 TP |
390 | default y |
391 | bool "Support Intel processors" if PROCESSOR_SELECT | |
8f9ca475 | 392 | ---help--- |
b7b3a425 IM |
393 | This enables detection, tunings and quirks for Intel processors |
394 | ||
395 | You need this enabled if you want your kernel to run on an | |
396 | Intel CPU. Disabling this option on other types of CPUs | |
397 | makes the kernel a tiny bit smaller. Disabling it on an Intel | |
398 | CPU might render the kernel unbootable. | |
399 | ||
400 | If unsure, say N. | |
8d02c211 TP |
401 | |
402 | config CPU_SUP_CYRIX_32 | |
403 | default y | |
404 | bool "Support Cyrix processors" if PROCESSOR_SELECT | |
eb068e78 | 405 | depends on M486 || M586 || M586TSC || M586MMX || (EXPERT && !64BIT) |
8f9ca475 | 406 | ---help--- |
b7b3a425 IM |
407 | This enables detection, tunings and quirks for Cyrix processors |
408 | ||
409 | You need this enabled if you want your kernel to run on a | |
410 | Cyrix CPU. Disabling this option on other types of CPUs | |
411 | makes the kernel a tiny bit smaller. Disabling it on a Cyrix | |
412 | CPU might render the kernel unbootable. | |
413 | ||
414 | If unsure, say N. | |
8d02c211 | 415 | |
ff73152c | 416 | config CPU_SUP_AMD |
8d02c211 TP |
417 | default y |
418 | bool "Support AMD processors" if PROCESSOR_SELECT | |
8f9ca475 | 419 | ---help--- |
b7b3a425 IM |
420 | This enables detection, tunings and quirks for AMD processors |
421 | ||
422 | You need this enabled if you want your kernel to run on an | |
423 | AMD CPU. Disabling this option on other types of CPUs | |
424 | makes the kernel a tiny bit smaller. Disabling it on an AMD | |
425 | CPU might render the kernel unbootable. | |
426 | ||
427 | If unsure, say N. | |
8d02c211 | 428 | |
c9661c1e PW |
429 | config CPU_SUP_HYGON |
430 | default y | |
431 | bool "Support Hygon processors" if PROCESSOR_SELECT | |
432 | select CPU_SUP_AMD | |
433 | help | |
434 | This enables detection, tunings and quirks for Hygon processors | |
435 | ||
436 | You need this enabled if you want your kernel to run on an | |
437 | Hygon CPU. Disabling this option on other types of CPUs | |
438 | makes the kernel a tiny bit smaller. Disabling it on an Hygon | |
439 | CPU might render the kernel unbootable. | |
440 | ||
441 | If unsure, say N. | |
442 | ||
48f4c485 | 443 | config CPU_SUP_CENTAUR |
8d02c211 TP |
444 | default y |
445 | bool "Support Centaur processors" if PROCESSOR_SELECT | |
8f9ca475 | 446 | ---help--- |
b7b3a425 IM |
447 | This enables detection, tunings and quirks for Centaur processors |
448 | ||
449 | You need this enabled if you want your kernel to run on a | |
450 | Centaur CPU. Disabling this option on other types of CPUs | |
451 | makes the kernel a tiny bit smaller. Disabling it on a Centaur | |
452 | CPU might render the kernel unbootable. | |
453 | ||
454 | If unsure, say N. | |
8d02c211 TP |
455 | |
456 | config CPU_SUP_TRANSMETA_32 | |
457 | default y | |
458 | bool "Support Transmeta processors" if PROCESSOR_SELECT | |
459 | depends on !64BIT | |
8f9ca475 | 460 | ---help--- |
b7b3a425 IM |
461 | This enables detection, tunings and quirks for Transmeta processors |
462 | ||
463 | You need this enabled if you want your kernel to run on a | |
464 | Transmeta CPU. Disabling this option on other types of CPUs | |
465 | makes the kernel a tiny bit smaller. Disabling it on a Transmeta | |
466 | CPU might render the kernel unbootable. | |
467 | ||
468 | If unsure, say N. | |
8d02c211 TP |
469 | |
470 | config CPU_SUP_UMC_32 | |
471 | default y | |
472 | bool "Support UMC processors" if PROCESSOR_SELECT | |
eb068e78 | 473 | depends on M486 || (EXPERT && !64BIT) |
8f9ca475 | 474 | ---help--- |
b7b3a425 IM |
475 | This enables detection, tunings and quirks for UMC processors |
476 | ||
477 | You need this enabled if you want your kernel to run on a | |
478 | UMC CPU. Disabling this option on other types of CPUs | |
479 | makes the kernel a tiny bit smaller. Disabling it on a UMC | |
480 | CPU might render the kernel unbootable. | |
481 | ||
482 | If unsure, say N. | |
761fdd5e TW |
483 | |
484 | config CPU_SUP_ZHAOXIN | |
485 | default y | |
486 | bool "Support Zhaoxin processors" if PROCESSOR_SELECT | |
487 | help | |
488 | This enables detection, tunings and quirks for Zhaoxin processors | |
489 | ||
490 | You need this enabled if you want your kernel to run on a | |
491 | Zhaoxin CPU. Disabling this option on other types of CPUs | |
492 | makes the kernel a tiny bit smaller. Disabling it on a Zhaoxin | |
493 | CPU might render the kernel unbootable. | |
494 | ||
495 | If unsure, say N. |