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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
478dc89c | 2 | #include <linux/jump_label.h> |
8c1f7558 | 3 | #include <asm/unwind_hints.h> |
8a09317b DH |
4 | #include <asm/cpufeatures.h> |
5 | #include <asm/page_types.h> | |
6fd166aa PZ |
6 | #include <asm/percpu.h> |
7 | #include <asm/asm-offsets.h> | |
8 | #include <asm/processor-flags.h> | |
478dc89c | 9 | |
0c2bd5a5 | 10 | /* |
063f8913 IM |
11 | |
12 | x86 function call convention, 64-bit: | |
13 | ------------------------------------- | |
14 | arguments | callee-saved | extra caller-saved | return | |
15 | [callee-clobbered] | | [callee-clobbered] | | |
16 | --------------------------------------------------------------------------- | |
17 | rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**] | |
18 | ||
19 | ( rsp is obviously invariant across normal function calls. (gcc can 'merge' | |
20 | functions when it sees tail-call optimization possibilities) rflags is | |
21 | clobbered. Leftover arguments are passed over the stack frame.) | |
22 | ||
23 | [*] In the frame-pointers case rbp is fixed to the stack frame. | |
24 | ||
25 | [**] for struct return values wider than 64 bits the return convention is a | |
26 | bit more complex: up to 128 bits width we return small structures | |
27 | straight in rax, rdx. For structures larger than that (3 words or | |
28 | larger) the caller puts a pointer to an on-stack return struct | |
29 | [allocated in the caller's stack frame] into the first argument - i.e. | |
30 | into rdi. All other arguments shift up by one in this case. | |
31 | Fortunately this case is rare in the kernel. | |
32 | ||
33 | For 32-bit we have the following conventions - kernel is built with | |
34 | -mregparm=3 and -freg-struct-return: | |
35 | ||
36 | x86 function calling convention, 32-bit: | |
37 | ---------------------------------------- | |
38 | arguments | callee-saved | extra caller-saved | return | |
39 | [callee-clobbered] | | [callee-clobbered] | | |
40 | ------------------------------------------------------------------------- | |
41 | eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**] | |
42 | ||
43 | ( here too esp is obviously invariant across normal function calls. eflags | |
44 | is clobbered. Leftover arguments are passed over the stack frame. ) | |
45 | ||
46 | [*] In the frame-pointers case ebp is fixed to the stack frame. | |
47 | ||
48 | [**] We build with -freg-struct-return, which on 32-bit means similar | |
49 | semantics as on 64-bit: edx can be used for a second return value | |
50 | (i.e. covering integer and structure sizes up to 64 bits) - after that | |
51 | it gets more complex and more expensive: 3-word or larger struct returns | |
52 | get done in the caller's frame and the pointer to the return struct goes | |
53 | into regparm0, i.e. eax - the other arguments shift up and the | |
54 | function's register parameters degenerate to regparm=2 in essence. | |
55 | ||
56 | */ | |
57 | ||
1a338ac3 PZ |
58 | #ifdef CONFIG_X86_64 |
59 | ||
063f8913 | 60 | /* |
1b2b23d8 TG |
61 | * 64-bit system call stack frame layout defines and helpers, |
62 | * for assembly code: | |
0c2bd5a5 | 63 | */ |
1da177e4 | 64 | |
76f5df43 DV |
65 | /* The layout forms the "struct pt_regs" on the stack: */ |
66 | /* | |
67 | * C ABI says these regs are callee-preserved. They aren't saved on kernel entry | |
68 | * unless syscall needs a complete, fully filled "struct pt_regs". | |
69 | */ | |
70 | #define R15 0*8 | |
71 | #define R14 1*8 | |
72 | #define R13 2*8 | |
73 | #define R12 3*8 | |
74 | #define RBP 4*8 | |
75 | #define RBX 5*8 | |
76 | /* These regs are callee-clobbered. Always saved on kernel entry. */ | |
77 | #define R11 6*8 | |
78 | #define R10 7*8 | |
79 | #define R9 8*8 | |
80 | #define R8 9*8 | |
81 | #define RAX 10*8 | |
82 | #define RCX 11*8 | |
83 | #define RDX 12*8 | |
84 | #define RSI 13*8 | |
85 | #define RDI 14*8 | |
86 | /* | |
87 | * On syscall entry, this is syscall#. On CPU exception, this is error code. | |
88 | * On hw interrupt, it's IRQ number: | |
89 | */ | |
90 | #define ORIG_RAX 15*8 | |
91 | /* Return frame for iretq */ | |
92 | #define RIP 16*8 | |
93 | #define CS 17*8 | |
94 | #define EFLAGS 18*8 | |
95 | #define RSP 19*8 | |
96 | #define SS 20*8 | |
97 | ||
911d2bb5 DV |
98 | #define SIZEOF_PTREGS 21*8 |
99 | ||
59df2268 AK |
100 | .macro ALLOC_PT_GPREGS_ON_STACK |
101 | addq $-(15*8), %rsp | |
76f5df43 | 102 | .endm |
a268fcfa | 103 | |
29722cd4 DV |
104 | .macro SAVE_C_REGS_HELPER offset=0 rax=1 rcx=1 r8910=1 r11=1 |
105 | .if \r11 | |
131484c8 | 106 | movq %r11, 6*8+\offset(%rsp) |
29722cd4 DV |
107 | .endif |
108 | .if \r8910 | |
131484c8 IM |
109 | movq %r10, 7*8+\offset(%rsp) |
110 | movq %r9, 8*8+\offset(%rsp) | |
111 | movq %r8, 9*8+\offset(%rsp) | |
54eea995 | 112 | .endif |
76f5df43 | 113 | .if \rax |
131484c8 | 114 | movq %rax, 10*8+\offset(%rsp) |
76f5df43 DV |
115 | .endif |
116 | .if \rcx | |
131484c8 | 117 | movq %rcx, 11*8+\offset(%rsp) |
1da177e4 | 118 | .endif |
131484c8 IM |
119 | movq %rdx, 12*8+\offset(%rsp) |
120 | movq %rsi, 13*8+\offset(%rsp) | |
121 | movq %rdi, 14*8+\offset(%rsp) | |
8c1f7558 | 122 | UNWIND_HINT_REGS offset=\offset extra=0 |
76f5df43 DV |
123 | .endm |
124 | .macro SAVE_C_REGS offset=0 | |
29722cd4 | 125 | SAVE_C_REGS_HELPER \offset, 1, 1, 1, 1 |
76f5df43 DV |
126 | .endm |
127 | .macro SAVE_C_REGS_EXCEPT_RAX_RCX offset=0 | |
29722cd4 | 128 | SAVE_C_REGS_HELPER \offset, 0, 0, 1, 1 |
76f5df43 DV |
129 | .endm |
130 | .macro SAVE_C_REGS_EXCEPT_R891011 | |
29722cd4 | 131 | SAVE_C_REGS_HELPER 0, 1, 1, 0, 0 |
76f5df43 DV |
132 | .endm |
133 | .macro SAVE_C_REGS_EXCEPT_RCX_R891011 | |
29722cd4 DV |
134 | SAVE_C_REGS_HELPER 0, 1, 0, 0, 0 |
135 | .endm | |
136 | .macro SAVE_C_REGS_EXCEPT_RAX_RCX_R11 | |
137 | SAVE_C_REGS_HELPER 0, 0, 0, 1, 0 | |
76f5df43 | 138 | .endm |
a268fcfa | 139 | |
76f5df43 | 140 | .macro SAVE_EXTRA_REGS offset=0 |
131484c8 IM |
141 | movq %r15, 0*8+\offset(%rsp) |
142 | movq %r14, 1*8+\offset(%rsp) | |
143 | movq %r13, 2*8+\offset(%rsp) | |
144 | movq %r12, 3*8+\offset(%rsp) | |
145 | movq %rbp, 4*8+\offset(%rsp) | |
146 | movq %rbx, 5*8+\offset(%rsp) | |
8c1f7558 | 147 | UNWIND_HINT_REGS offset=\offset |
76f5df43 | 148 | .endm |
1da177e4 | 149 | |
e872045b AL |
150 | .macro POP_EXTRA_REGS |
151 | popq %r15 | |
152 | popq %r14 | |
153 | popq %r13 | |
154 | popq %r12 | |
155 | popq %rbp | |
156 | popq %rbx | |
157 | .endm | |
158 | ||
159 | .macro POP_C_REGS | |
160 | popq %r11 | |
161 | popq %r10 | |
162 | popq %r9 | |
163 | popq %r8 | |
164 | popq %rax | |
165 | popq %rcx | |
166 | popq %rdx | |
167 | popq %rsi | |
168 | popq %rdi | |
1da177e4 LT |
169 | .endm |
170 | ||
171 | .macro icebp | |
172 | .byte 0xf1 | |
173 | .endm | |
1a338ac3 | 174 | |
946c1911 JP |
175 | /* |
176 | * This is a sneaky trick to help the unwinder find pt_regs on the stack. The | |
177 | * frame pointer is replaced with an encoded pointer to pt_regs. The encoding | |
178 | * is just setting the LSB, which makes it an invalid stack address and is also | |
179 | * a signal to the unwinder that it's a pt_regs pointer in disguise. | |
180 | * | |
181 | * NOTE: This macro must be used *after* SAVE_EXTRA_REGS because it corrupts | |
182 | * the original rbp. | |
183 | */ | |
184 | .macro ENCODE_FRAME_POINTER ptregs_offset=0 | |
185 | #ifdef CONFIG_FRAME_POINTER | |
186 | .if \ptregs_offset | |
187 | leaq \ptregs_offset(%rsp), %rbp | |
188 | .else | |
189 | mov %rsp, %rbp | |
190 | .endif | |
191 | orq $0x1, %rbp | |
192 | #endif | |
193 | .endm | |
194 | ||
8a09317b DH |
195 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
196 | ||
6fd166aa PZ |
197 | /* |
198 | * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two | |
199 | * halves: | |
200 | */ | |
f10ee3dc TG |
201 | #define PTI_USER_PGTABLE_BIT PAGE_SHIFT |
202 | #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT) | |
203 | #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT | |
204 | #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT) | |
205 | #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK) | |
8a09317b | 206 | |
6fd166aa PZ |
207 | .macro SET_NOFLUSH_BIT reg:req |
208 | bts $X86_CR3_PCID_NOFLUSH_BIT, \reg | |
8a09317b DH |
209 | .endm |
210 | ||
6fd166aa PZ |
211 | .macro ADJUST_KERNEL_CR3 reg:req |
212 | ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID | |
213 | /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */ | |
f10ee3dc | 214 | andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg |
8a09317b DH |
215 | .endm |
216 | ||
217 | .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req | |
aa8c6248 | 218 | ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI |
8a09317b DH |
219 | mov %cr3, \scratch_reg |
220 | ADJUST_KERNEL_CR3 \scratch_reg | |
221 | mov \scratch_reg, %cr3 | |
aa8c6248 | 222 | .Lend_\@: |
8a09317b DH |
223 | .endm |
224 | ||
6fd166aa PZ |
225 | #define THIS_CPU_user_pcid_flush_mask \ |
226 | PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask | |
227 | ||
228 | .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req | |
aa8c6248 | 229 | ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI |
8a09317b | 230 | mov %cr3, \scratch_reg |
6fd166aa PZ |
231 | |
232 | ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID | |
233 | ||
234 | /* | |
235 | * Test if the ASID needs a flush. | |
236 | */ | |
237 | movq \scratch_reg, \scratch_reg2 | |
238 | andq $(0x7FF), \scratch_reg /* mask ASID */ | |
239 | bt \scratch_reg, THIS_CPU_user_pcid_flush_mask | |
240 | jnc .Lnoflush_\@ | |
241 | ||
242 | /* Flush needed, clear the bit */ | |
243 | btr \scratch_reg, THIS_CPU_user_pcid_flush_mask | |
244 | movq \scratch_reg2, \scratch_reg | |
f10ee3dc | 245 | jmp .Lwrcr3_pcid_\@ |
6fd166aa PZ |
246 | |
247 | .Lnoflush_\@: | |
248 | movq \scratch_reg2, \scratch_reg | |
249 | SET_NOFLUSH_BIT \scratch_reg | |
250 | ||
f10ee3dc TG |
251 | .Lwrcr3_pcid_\@: |
252 | /* Flip the ASID to the user version */ | |
253 | orq $(PTI_USER_PCID_MASK), \scratch_reg | |
254 | ||
6fd166aa | 255 | .Lwrcr3_\@: |
f10ee3dc TG |
256 | /* Flip the PGD to the user version */ |
257 | orq $(PTI_USER_PGTABLE_MASK), \scratch_reg | |
8a09317b | 258 | mov \scratch_reg, %cr3 |
aa8c6248 | 259 | .Lend_\@: |
8a09317b DH |
260 | .endm |
261 | ||
6fd166aa PZ |
262 | .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req |
263 | pushq %rax | |
264 | SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax | |
265 | popq %rax | |
266 | .endm | |
267 | ||
8a09317b | 268 | .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req |
aa8c6248 | 269 | ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI |
8a09317b DH |
270 | movq %cr3, \scratch_reg |
271 | movq \scratch_reg, \save_reg | |
272 | /* | |
f10ee3dc TG |
273 | * Test the user pagetable bit. If set, then the user page tables |
274 | * are active. If clear CR3 already has the kernel page table | |
275 | * active. | |
8a09317b | 276 | */ |
f10ee3dc TG |
277 | bt $PTI_USER_PGTABLE_BIT, \scratch_reg |
278 | jnc .Ldone_\@ | |
8a09317b DH |
279 | |
280 | ADJUST_KERNEL_CR3 \scratch_reg | |
281 | movq \scratch_reg, %cr3 | |
282 | ||
283 | .Ldone_\@: | |
284 | .endm | |
285 | ||
21e94459 | 286 | .macro RESTORE_CR3 scratch_reg:req save_reg:req |
aa8c6248 | 287 | ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI |
21e94459 PZ |
288 | |
289 | ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID | |
290 | ||
291 | /* | |
292 | * KERNEL pages can always resume with NOFLUSH as we do | |
293 | * explicit flushes. | |
294 | */ | |
f10ee3dc | 295 | bt $PTI_USER_PGTABLE_BIT, \save_reg |
21e94459 PZ |
296 | jnc .Lnoflush_\@ |
297 | ||
298 | /* | |
299 | * Check if there's a pending flush for the user ASID we're | |
300 | * about to set. | |
301 | */ | |
302 | movq \save_reg, \scratch_reg | |
303 | andq $(0x7FF), \scratch_reg | |
304 | bt \scratch_reg, THIS_CPU_user_pcid_flush_mask | |
305 | jnc .Lnoflush_\@ | |
306 | ||
307 | btr \scratch_reg, THIS_CPU_user_pcid_flush_mask | |
308 | jmp .Lwrcr3_\@ | |
309 | ||
310 | .Lnoflush_\@: | |
311 | SET_NOFLUSH_BIT \save_reg | |
312 | ||
313 | .Lwrcr3_\@: | |
8a09317b DH |
314 | /* |
315 | * The CR3 write could be avoided when not changing its value, | |
316 | * but would require a CR3 read *and* a scratch register. | |
317 | */ | |
318 | movq \save_reg, %cr3 | |
aa8c6248 | 319 | .Lend_\@: |
8a09317b DH |
320 | .endm |
321 | ||
322 | #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */ | |
323 | ||
324 | .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req | |
325 | .endm | |
6fd166aa PZ |
326 | .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req |
327 | .endm | |
328 | .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req | |
8a09317b DH |
329 | .endm |
330 | .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req | |
331 | .endm | |
21e94459 | 332 | .macro RESTORE_CR3 scratch_reg:req save_reg:req |
8a09317b DH |
333 | .endm |
334 | ||
335 | #endif | |
336 | ||
1a338ac3 PZ |
337 | #endif /* CONFIG_X86_64 */ |
338 | ||
478dc89c AL |
339 | /* |
340 | * This does 'call enter_from_user_mode' unless we can avoid it based on | |
341 | * kernel config or using the static jump infrastructure. | |
342 | */ | |
343 | .macro CALL_enter_from_user_mode | |
344 | #ifdef CONFIG_CONTEXT_TRACKING | |
345 | #ifdef HAVE_JUMP_LABEL | |
346 | STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0 | |
347 | #endif | |
348 | call enter_from_user_mode | |
349 | .Lafter_call_\@: | |
350 | #endif | |
351 | .endm |