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Commit | Line | Data |
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1da177e4 | 1 | /* |
a49976d1 | 2 | * Copyright (C) 1991,1992 Linus Torvalds |
1da177e4 | 3 | * |
a49976d1 | 4 | * entry_32.S contains the system-call and low-level fault and trap handling routines. |
1da177e4 | 5 | * |
39e8701f | 6 | * Stack layout while running C code: |
a49976d1 IM |
7 | * ptrace needs to have all registers on the stack. |
8 | * If the order here is changed, it needs to be | |
9 | * updated in fork.c:copy_process(), signal.c:do_signal(), | |
1da177e4 LT |
10 | * ptrace.c and ptrace.h |
11 | * | |
12 | * 0(%esp) - %ebx | |
13 | * 4(%esp) - %ecx | |
14 | * 8(%esp) - %edx | |
9b47feb7 | 15 | * C(%esp) - %esi |
1da177e4 LT |
16 | * 10(%esp) - %edi |
17 | * 14(%esp) - %ebp | |
18 | * 18(%esp) - %eax | |
19 | * 1C(%esp) - %ds | |
20 | * 20(%esp) - %es | |
464d1a78 | 21 | * 24(%esp) - %fs |
ccbeed3a TH |
22 | * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS |
23 | * 2C(%esp) - orig_eax | |
24 | * 30(%esp) - %eip | |
25 | * 34(%esp) - %cs | |
26 | * 38(%esp) - %eflags | |
27 | * 3C(%esp) - %oldesp | |
28 | * 40(%esp) - %oldss | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 | 31 | #include <linux/linkage.h> |
d7e7528b | 32 | #include <linux/err.h> |
1da177e4 | 33 | #include <asm/thread_info.h> |
55f327fa | 34 | #include <asm/irqflags.h> |
1da177e4 LT |
35 | #include <asm/errno.h> |
36 | #include <asm/segment.h> | |
37 | #include <asm/smp.h> | |
0341c14d | 38 | #include <asm/page_types.h> |
be44d2aa | 39 | #include <asm/percpu.h> |
ab68ed98 | 40 | #include <asm/processor-flags.h> |
395a59d0 | 41 | #include <asm/ftrace.h> |
9b7dc567 | 42 | #include <asm/irq_vectors.h> |
cd4d09ec | 43 | #include <asm/cpufeatures.h> |
b4ca46e4 | 44 | #include <asm/alternative-asm.h> |
6837a54d | 45 | #include <asm/asm.h> |
e59d1b0a | 46 | #include <asm/smap.h> |
1da177e4 | 47 | |
ea714547 JO |
48 | .section .entry.text, "ax" |
49 | ||
139ec7c4 RR |
50 | /* |
51 | * We use macros for low-level operations which need to be overridden | |
52 | * for paravirtualization. The following will never clobber any registers: | |
53 | * INTERRUPT_RETURN (aka. "iret") | |
54 | * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax") | |
d75cd22f | 55 | * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit"). |
139ec7c4 RR |
56 | * |
57 | * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must | |
58 | * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY). | |
59 | * Allowing a register to be clobbered can shrink the paravirt replacement | |
60 | * enough to patch inline, increasing performance. | |
61 | */ | |
62 | ||
1da177e4 | 63 | #ifdef CONFIG_PREEMPT |
a49976d1 | 64 | # define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF |
1da177e4 | 65 | #else |
a49976d1 IM |
66 | # define preempt_stop(clobbers) |
67 | # define resume_kernel restore_all | |
1da177e4 LT |
68 | #endif |
69 | ||
55f327fa IM |
70 | .macro TRACE_IRQS_IRET |
71 | #ifdef CONFIG_TRACE_IRQFLAGS | |
a49976d1 IM |
72 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off? |
73 | jz 1f | |
55f327fa IM |
74 | TRACE_IRQS_ON |
75 | 1: | |
76 | #endif | |
77 | .endm | |
78 | ||
ccbeed3a TH |
79 | /* |
80 | * User gs save/restore | |
81 | * | |
82 | * %gs is used for userland TLS and kernel only uses it for stack | |
83 | * canary which is required to be at %gs:20 by gcc. Read the comment | |
84 | * at the top of stackprotector.h for more info. | |
85 | * | |
86 | * Local labels 98 and 99 are used. | |
87 | */ | |
88 | #ifdef CONFIG_X86_32_LAZY_GS | |
89 | ||
90 | /* unfortunately push/pop can't be no-op */ | |
91 | .macro PUSH_GS | |
a49976d1 | 92 | pushl $0 |
ccbeed3a TH |
93 | .endm |
94 | .macro POP_GS pop=0 | |
a49976d1 | 95 | addl $(4 + \pop), %esp |
ccbeed3a TH |
96 | .endm |
97 | .macro POP_GS_EX | |
98 | .endm | |
99 | ||
100 | /* all the rest are no-op */ | |
101 | .macro PTGS_TO_GS | |
102 | .endm | |
103 | .macro PTGS_TO_GS_EX | |
104 | .endm | |
105 | .macro GS_TO_REG reg | |
106 | .endm | |
107 | .macro REG_TO_PTGS reg | |
108 | .endm | |
109 | .macro SET_KERNEL_GS reg | |
110 | .endm | |
111 | ||
112 | #else /* CONFIG_X86_32_LAZY_GS */ | |
113 | ||
114 | .macro PUSH_GS | |
a49976d1 | 115 | pushl %gs |
ccbeed3a TH |
116 | .endm |
117 | ||
118 | .macro POP_GS pop=0 | |
a49976d1 | 119 | 98: popl %gs |
ccbeed3a | 120 | .if \pop <> 0 |
9b47feb7 | 121 | add $\pop, %esp |
ccbeed3a TH |
122 | .endif |
123 | .endm | |
124 | .macro POP_GS_EX | |
125 | .pushsection .fixup, "ax" | |
a49976d1 IM |
126 | 99: movl $0, (%esp) |
127 | jmp 98b | |
ccbeed3a | 128 | .popsection |
a49976d1 | 129 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
130 | .endm |
131 | ||
132 | .macro PTGS_TO_GS | |
a49976d1 | 133 | 98: mov PT_GS(%esp), %gs |
ccbeed3a TH |
134 | .endm |
135 | .macro PTGS_TO_GS_EX | |
136 | .pushsection .fixup, "ax" | |
a49976d1 IM |
137 | 99: movl $0, PT_GS(%esp) |
138 | jmp 98b | |
ccbeed3a | 139 | .popsection |
a49976d1 | 140 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
141 | .endm |
142 | ||
143 | .macro GS_TO_REG reg | |
a49976d1 | 144 | movl %gs, \reg |
ccbeed3a TH |
145 | .endm |
146 | .macro REG_TO_PTGS reg | |
a49976d1 | 147 | movl \reg, PT_GS(%esp) |
ccbeed3a TH |
148 | .endm |
149 | .macro SET_KERNEL_GS reg | |
a49976d1 IM |
150 | movl $(__KERNEL_STACK_CANARY), \reg |
151 | movl \reg, %gs | |
ccbeed3a TH |
152 | .endm |
153 | ||
a49976d1 | 154 | #endif /* CONFIG_X86_32_LAZY_GS */ |
ccbeed3a | 155 | |
150ac78d | 156 | .macro SAVE_ALL pt_regs_ax=%eax |
f0d96110 | 157 | cld |
ccbeed3a | 158 | PUSH_GS |
a49976d1 IM |
159 | pushl %fs |
160 | pushl %es | |
161 | pushl %ds | |
150ac78d | 162 | pushl \pt_regs_ax |
a49976d1 IM |
163 | pushl %ebp |
164 | pushl %edi | |
165 | pushl %esi | |
166 | pushl %edx | |
167 | pushl %ecx | |
168 | pushl %ebx | |
169 | movl $(__USER_DS), %edx | |
170 | movl %edx, %ds | |
171 | movl %edx, %es | |
172 | movl $(__KERNEL_PERCPU), %edx | |
173 | movl %edx, %fs | |
ccbeed3a | 174 | SET_KERNEL_GS %edx |
f0d96110 | 175 | .endm |
1da177e4 | 176 | |
f0d96110 | 177 | .macro RESTORE_INT_REGS |
a49976d1 IM |
178 | popl %ebx |
179 | popl %ecx | |
180 | popl %edx | |
181 | popl %esi | |
182 | popl %edi | |
183 | popl %ebp | |
184 | popl %eax | |
f0d96110 | 185 | .endm |
1da177e4 | 186 | |
ccbeed3a | 187 | .macro RESTORE_REGS pop=0 |
f0d96110 | 188 | RESTORE_INT_REGS |
a49976d1 IM |
189 | 1: popl %ds |
190 | 2: popl %es | |
191 | 3: popl %fs | |
ccbeed3a | 192 | POP_GS \pop |
f0d96110 | 193 | .pushsection .fixup, "ax" |
a49976d1 IM |
194 | 4: movl $0, (%esp) |
195 | jmp 1b | |
196 | 5: movl $0, (%esp) | |
197 | jmp 2b | |
198 | 6: movl $0, (%esp) | |
199 | jmp 3b | |
f95d47ca | 200 | .popsection |
a49976d1 IM |
201 | _ASM_EXTABLE(1b, 4b) |
202 | _ASM_EXTABLE(2b, 5b) | |
203 | _ASM_EXTABLE(3b, 6b) | |
ccbeed3a | 204 | POP_GS_EX |
f0d96110 | 205 | .endm |
1da177e4 | 206 | |
0100301b BG |
207 | /* |
208 | * %eax: prev task | |
209 | * %edx: next task | |
210 | */ | |
211 | ENTRY(__switch_to_asm) | |
212 | /* | |
213 | * Save callee-saved registers | |
214 | * This must match the order in struct inactive_task_frame | |
215 | */ | |
216 | pushl %ebp | |
217 | pushl %ebx | |
218 | pushl %edi | |
219 | pushl %esi | |
220 | ||
221 | /* switch stack */ | |
222 | movl %esp, TASK_threadsp(%eax) | |
223 | movl TASK_threadsp(%edx), %esp | |
224 | ||
225 | #ifdef CONFIG_CC_STACKPROTECTOR | |
226 | movl TASK_stack_canary(%edx), %ebx | |
227 | movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset | |
228 | #endif | |
229 | ||
230 | /* restore callee-saved registers */ | |
231 | popl %esi | |
232 | popl %edi | |
233 | popl %ebx | |
234 | popl %ebp | |
235 | ||
236 | jmp __switch_to | |
237 | END(__switch_to_asm) | |
238 | ||
239 | /* | |
240 | * A newly forked process directly context switches into this address. | |
241 | * | |
242 | * eax: prev task we switched from | |
616d2483 BG |
243 | * ebx: kernel thread func (NULL for user thread) |
244 | * edi: kernel thread arg | |
0100301b | 245 | */ |
1da177e4 | 246 | ENTRY(ret_from_fork) |
a49976d1 IM |
247 | pushl %eax |
248 | call schedule_tail | |
a49976d1 | 249 | popl %eax |
39e8701f | 250 | |
616d2483 BG |
251 | testl %ebx, %ebx |
252 | jnz 1f /* kernel threads are uncommon */ | |
253 | ||
254 | 2: | |
39e8701f AL |
255 | /* When we fork, we trace the syscall return in the child, too. */ |
256 | movl %esp, %eax | |
257 | call syscall_return_slowpath | |
258 | jmp restore_all | |
39e8701f | 259 | |
616d2483 BG |
260 | /* kernel thread */ |
261 | 1: movl %edi, %eax | |
262 | call *%ebx | |
39e8701f | 263 | /* |
616d2483 BG |
264 | * A kernel thread is allowed to return here after successfully |
265 | * calling do_execve(). Exit to userspace to complete the execve() | |
266 | * syscall. | |
39e8701f | 267 | */ |
616d2483 BG |
268 | movl $0, PT_EAX(%esp) |
269 | jmp 2b | |
270 | END(ret_from_fork) | |
6783eaa2 | 271 | |
1da177e4 LT |
272 | /* |
273 | * Return to user mode is not as complex as all this looks, | |
274 | * but we want the default path for a system call return to | |
275 | * go as quickly as possible which is why some of this is | |
276 | * less clear than it otherwise should be. | |
277 | */ | |
278 | ||
279 | # userspace resumption stub bypassing syscall exit tracing | |
280 | ALIGN | |
281 | ret_from_exception: | |
139ec7c4 | 282 | preempt_stop(CLBR_ANY) |
1da177e4 | 283 | ret_from_intr: |
29a2e283 | 284 | #ifdef CONFIG_VM86 |
a49976d1 IM |
285 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS |
286 | movb PT_CS(%esp), %al | |
287 | andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax | |
29a2e283 DA |
288 | #else |
289 | /* | |
6783eaa2 | 290 | * We can be coming here from child spawned by kernel_thread(). |
29a2e283 | 291 | */ |
a49976d1 IM |
292 | movl PT_CS(%esp), %eax |
293 | andl $SEGMENT_RPL_MASK, %eax | |
29a2e283 | 294 | #endif |
a49976d1 IM |
295 | cmpl $USER_RPL, %eax |
296 | jb resume_kernel # not returning to v8086 or userspace | |
f95d47ca | 297 | |
1da177e4 | 298 | ENTRY(resume_userspace) |
5d73fc70 | 299 | DISABLE_INTERRUPTS(CLBR_ANY) |
e32e58a9 | 300 | TRACE_IRQS_OFF |
5d73fc70 AL |
301 | movl %esp, %eax |
302 | call prepare_exit_to_usermode | |
a49976d1 | 303 | jmp restore_all |
47a55cd7 | 304 | END(ret_from_exception) |
1da177e4 LT |
305 | |
306 | #ifdef CONFIG_PREEMPT | |
307 | ENTRY(resume_kernel) | |
139ec7c4 | 308 | DISABLE_INTERRUPTS(CLBR_ANY) |
1da177e4 | 309 | need_resched: |
a49976d1 IM |
310 | cmpl $0, PER_CPU_VAR(__preempt_count) |
311 | jnz restore_all | |
312 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ? | |
313 | jz restore_all | |
314 | call preempt_schedule_irq | |
315 | jmp need_resched | |
47a55cd7 | 316 | END(resume_kernel) |
1da177e4 LT |
317 | #endif |
318 | ||
f2b37575 AL |
319 | GLOBAL(__begin_SYSENTER_singlestep_region) |
320 | /* | |
321 | * All code from here through __end_SYSENTER_singlestep_region is subject | |
322 | * to being single-stepped if a user program sets TF and executes SYSENTER. | |
323 | * There is absolutely nothing that we can do to prevent this from happening | |
324 | * (thanks Intel!). To keep our handling of this situation as simple as | |
325 | * possible, we handle TF just like AC and NT, except that our #DB handler | |
326 | * will ignore all of the single-step traps generated in this range. | |
327 | */ | |
328 | ||
329 | #ifdef CONFIG_XEN | |
330 | /* | |
331 | * Xen doesn't set %esp to be precisely what the normal SYSENTER | |
332 | * entry point expects, so fix it up before using the normal path. | |
333 | */ | |
334 | ENTRY(xen_sysenter_target) | |
335 | addl $5*4, %esp /* remove xen-provided frame */ | |
336 | jmp sysenter_past_esp | |
337 | #endif | |
338 | ||
fda57b22 AL |
339 | /* |
340 | * 32-bit SYSENTER entry. | |
341 | * | |
342 | * 32-bit system calls through the vDSO's __kernel_vsyscall enter here | |
343 | * if X86_FEATURE_SEP is available. This is the preferred system call | |
344 | * entry on 32-bit systems. | |
345 | * | |
346 | * The SYSENTER instruction, in principle, should *only* occur in the | |
347 | * vDSO. In practice, a small number of Android devices were shipped | |
348 | * with a copy of Bionic that inlined a SYSENTER instruction. This | |
349 | * never happened in any of Google's Bionic versions -- it only happened | |
350 | * in a narrow range of Intel-provided versions. | |
351 | * | |
352 | * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs. | |
353 | * IF and VM in RFLAGS are cleared (IOW: interrupts are off). | |
354 | * SYSENTER does not save anything on the stack, | |
355 | * and does not save old EIP (!!!), ESP, or EFLAGS. | |
356 | * | |
357 | * To avoid losing track of EFLAGS.VM (and thus potentially corrupting | |
358 | * user and/or vm86 state), we explicitly disable the SYSENTER | |
359 | * instruction in vm86 mode by reprogramming the MSRs. | |
360 | * | |
361 | * Arguments: | |
362 | * eax system call number | |
363 | * ebx arg1 | |
364 | * ecx arg2 | |
365 | * edx arg3 | |
366 | * esi arg4 | |
367 | * edi arg5 | |
368 | * ebp user stack | |
369 | * 0(%ebp) arg6 | |
370 | */ | |
4c8cd0c5 | 371 | ENTRY(entry_SYSENTER_32) |
a49976d1 | 372 | movl TSS_sysenter_sp0(%esp), %esp |
1da177e4 | 373 | sysenter_past_esp: |
5f310f73 | 374 | pushl $__USER_DS /* pt_regs->ss */ |
30bfa7b3 | 375 | pushl %ebp /* pt_regs->sp (stashed in bp) */ |
5f310f73 AL |
376 | pushfl /* pt_regs->flags (except IF = 0) */ |
377 | orl $X86_EFLAGS_IF, (%esp) /* Fix IF */ | |
378 | pushl $__USER_CS /* pt_regs->cs */ | |
379 | pushl $0 /* pt_regs->ip = 0 (placeholder) */ | |
380 | pushl %eax /* pt_regs->orig_ax */ | |
381 | SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest */ | |
382 | ||
67f590e8 | 383 | /* |
f2b37575 AL |
384 | * SYSENTER doesn't filter flags, so we need to clear NT, AC |
385 | * and TF ourselves. To save a few cycles, we can check whether | |
67f590e8 AL |
386 | * either was set instead of doing an unconditional popfq. |
387 | * This needs to happen before enabling interrupts so that | |
388 | * we don't get preempted with NT set. | |
389 | * | |
f2b37575 AL |
390 | * If TF is set, we will single-step all the way to here -- do_debug |
391 | * will ignore all the traps. (Yes, this is slow, but so is | |
392 | * single-stepping in general. This allows us to avoid having | |
393 | * a more complicated code to handle the case where a user program | |
394 | * forces us to single-step through the SYSENTER entry code.) | |
395 | * | |
67f590e8 AL |
396 | * NB.: .Lsysenter_fix_flags is a label with the code under it moved |
397 | * out-of-line as an optimization: NT is unlikely to be set in the | |
398 | * majority of the cases and instead of polluting the I$ unnecessarily, | |
399 | * we're keeping that code behind a branch which will predict as | |
400 | * not-taken and therefore its instructions won't be fetched. | |
401 | */ | |
f2b37575 | 402 | testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp) |
67f590e8 AL |
403 | jnz .Lsysenter_fix_flags |
404 | .Lsysenter_flags_fixed: | |
405 | ||
55f327fa | 406 | /* |
5f310f73 AL |
407 | * User mode is traced as though IRQs are on, and SYSENTER |
408 | * turned them off. | |
e6e5494c | 409 | */ |
55f327fa | 410 | TRACE_IRQS_OFF |
5f310f73 AL |
411 | |
412 | movl %esp, %eax | |
413 | call do_fast_syscall_32 | |
91e2eea9 BO |
414 | /* XEN PV guests always use IRET path */ |
415 | ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \ | |
416 | "jmp .Lsyscall_32_done", X86_FEATURE_XENPV | |
5f310f73 AL |
417 | |
418 | /* Opportunistic SYSEXIT */ | |
419 | TRACE_IRQS_ON /* User mode traces as IRQs on. */ | |
420 | movl PT_EIP(%esp), %edx /* pt_regs->ip */ | |
421 | movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */ | |
3bd29515 AL |
422 | 1: mov PT_FS(%esp), %fs |
423 | PTGS_TO_GS | |
5f310f73 AL |
424 | popl %ebx /* pt_regs->bx */ |
425 | addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */ | |
426 | popl %esi /* pt_regs->si */ | |
427 | popl %edi /* pt_regs->di */ | |
428 | popl %ebp /* pt_regs->bp */ | |
429 | popl %eax /* pt_regs->ax */ | |
5f310f73 | 430 | |
c2c9b52f AL |
431 | /* |
432 | * Restore all flags except IF. (We restore IF separately because | |
433 | * STI gives a one-instruction window in which we won't be interrupted, | |
434 | * whereas POPF does not.) | |
435 | */ | |
436 | addl $PT_EFLAGS-PT_DS, %esp /* point esp at pt_regs->flags */ | |
437 | btr $X86_EFLAGS_IF_BIT, (%esp) | |
438 | popfl | |
439 | ||
5f310f73 AL |
440 | /* |
441 | * Return back to the vDSO, which will pop ecx and edx. | |
442 | * Don't bother with DS and ES (they already contain __USER_DS). | |
443 | */ | |
88c15ec9 BO |
444 | sti |
445 | sysexit | |
af0575bb | 446 | |
a49976d1 IM |
447 | .pushsection .fixup, "ax" |
448 | 2: movl $0, PT_FS(%esp) | |
449 | jmp 1b | |
f95d47ca | 450 | .popsection |
a49976d1 | 451 | _ASM_EXTABLE(1b, 2b) |
ccbeed3a | 452 | PTGS_TO_GS_EX |
67f590e8 AL |
453 | |
454 | .Lsysenter_fix_flags: | |
455 | pushl $X86_EFLAGS_FIXED | |
456 | popfl | |
457 | jmp .Lsysenter_flags_fixed | |
f2b37575 | 458 | GLOBAL(__end_SYSENTER_singlestep_region) |
4c8cd0c5 | 459 | ENDPROC(entry_SYSENTER_32) |
1da177e4 | 460 | |
fda57b22 AL |
461 | /* |
462 | * 32-bit legacy system call entry. | |
463 | * | |
464 | * 32-bit x86 Linux system calls traditionally used the INT $0x80 | |
465 | * instruction. INT $0x80 lands here. | |
466 | * | |
467 | * This entry point can be used by any 32-bit perform system calls. | |
468 | * Instances of INT $0x80 can be found inline in various programs and | |
469 | * libraries. It is also used by the vDSO's __kernel_vsyscall | |
470 | * fallback for hardware that doesn't support a faster entry method. | |
471 | * Restarted 32-bit system calls also fall back to INT $0x80 | |
472 | * regardless of what instruction was originally used to do the system | |
473 | * call. (64-bit programs can use INT $0x80 as well, but they can | |
474 | * only run on 64-bit kernels and therefore land in | |
475 | * entry_INT80_compat.) | |
476 | * | |
477 | * This is considered a slow path. It is not used by most libc | |
478 | * implementations on modern hardware except during process startup. | |
479 | * | |
480 | * Arguments: | |
481 | * eax system call number | |
482 | * ebx arg1 | |
483 | * ecx arg2 | |
484 | * edx arg3 | |
485 | * esi arg4 | |
486 | * edi arg5 | |
487 | * ebp arg6 | |
488 | */ | |
b2502b41 | 489 | ENTRY(entry_INT80_32) |
e59d1b0a | 490 | ASM_CLAC |
150ac78d | 491 | pushl %eax /* pt_regs->orig_ax */ |
5f310f73 | 492 | SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest */ |
150ac78d AL |
493 | |
494 | /* | |
a798f091 AL |
495 | * User mode is traced as though IRQs are on, and the interrupt gate |
496 | * turned them off. | |
150ac78d | 497 | */ |
a798f091 | 498 | TRACE_IRQS_OFF |
150ac78d AL |
499 | |
500 | movl %esp, %eax | |
a798f091 | 501 | call do_int80_syscall_32 |
5f310f73 | 502 | .Lsyscall_32_done: |
1da177e4 LT |
503 | |
504 | restore_all: | |
2e04bc76 AH |
505 | TRACE_IRQS_IRET |
506 | restore_all_notrace: | |
34273f41 | 507 | #ifdef CONFIG_X86_ESPFIX32 |
58a5aac5 AL |
508 | ALTERNATIVE "jmp restore_nocheck", "", X86_BUG_ESPFIX |
509 | ||
a49976d1 IM |
510 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS |
511 | /* | |
512 | * Warning: PT_OLDSS(%esp) contains the wrong/random values if we | |
513 | * are returning to the kernel. | |
514 | * See comments in process.c:copy_thread() for details. | |
515 | */ | |
516 | movb PT_OLDSS(%esp), %ah | |
517 | movb PT_CS(%esp), %al | |
518 | andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax | |
519 | cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax | |
520 | je ldt_ss # returning to user-space with LDT SS | |
34273f41 | 521 | #endif |
1da177e4 | 522 | restore_nocheck: |
a49976d1 | 523 | RESTORE_REGS 4 # skip orig_eax/error_code |
f7f3d791 | 524 | irq_return: |
3701d863 | 525 | INTERRUPT_RETURN |
a49976d1 IM |
526 | .section .fixup, "ax" |
527 | ENTRY(iret_exc ) | |
528 | pushl $0 # no error code | |
529 | pushl $do_iret_error | |
530 | jmp error_code | |
1da177e4 | 531 | .previous |
a49976d1 | 532 | _ASM_EXTABLE(irq_return, iret_exc) |
1da177e4 | 533 | |
34273f41 | 534 | #ifdef CONFIG_X86_ESPFIX32 |
1da177e4 | 535 | ldt_ss: |
dc4c2a0a AH |
536 | /* |
537 | * Setup and switch to ESPFIX stack | |
538 | * | |
539 | * We're returning to userspace with a 16 bit stack. The CPU will not | |
540 | * restore the high word of ESP for us on executing iret... This is an | |
541 | * "official" bug of all the x86-compatible CPUs, which we can work | |
542 | * around to make dosemu and wine happy. We do this by preloading the | |
543 | * high word of ESP with the high word of the userspace ESP while | |
544 | * compensating for the offset by changing to the ESPFIX segment with | |
545 | * a base address that matches for the difference. | |
546 | */ | |
72c511dd | 547 | #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8) |
a49976d1 IM |
548 | mov %esp, %edx /* load kernel esp */ |
549 | mov PT_OLDESP(%esp), %eax /* load userspace esp */ | |
550 | mov %dx, %ax /* eax: new kernel esp */ | |
9b47feb7 DV |
551 | sub %eax, %edx /* offset (low word is 0) */ |
552 | shr $16, %edx | |
a49976d1 IM |
553 | mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */ |
554 | mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */ | |
555 | pushl $__ESPFIX_SS | |
556 | pushl %eax /* new kernel esp */ | |
557 | /* | |
558 | * Disable interrupts, but do not irqtrace this section: we | |
2e04bc76 | 559 | * will soon execute iret and the tracer was already set to |
a49976d1 IM |
560 | * the irqstate after the IRET: |
561 | */ | |
139ec7c4 | 562 | DISABLE_INTERRUPTS(CLBR_EAX) |
a49976d1 IM |
563 | lss (%esp), %esp /* switch to espfix segment */ |
564 | jmp restore_nocheck | |
34273f41 | 565 | #endif |
b2502b41 | 566 | ENDPROC(entry_INT80_32) |
1da177e4 | 567 | |
f0d96110 | 568 | .macro FIXUP_ESPFIX_STACK |
dc4c2a0a AH |
569 | /* |
570 | * Switch back for ESPFIX stack to the normal zerobased stack | |
571 | * | |
572 | * We can't call C functions using the ESPFIX stack. This code reads | |
573 | * the high word of the segment base from the GDT and swiches to the | |
574 | * normal stack and adjusts ESP with the matching offset. | |
575 | */ | |
34273f41 | 576 | #ifdef CONFIG_X86_ESPFIX32 |
dc4c2a0a | 577 | /* fixup the stack */ |
a49976d1 IM |
578 | mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */ |
579 | mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */ | |
9b47feb7 | 580 | shl $16, %eax |
a49976d1 IM |
581 | addl %esp, %eax /* the adjusted stack pointer */ |
582 | pushl $__KERNEL_DS | |
583 | pushl %eax | |
584 | lss (%esp), %esp /* switch to the normal stack segment */ | |
34273f41 | 585 | #endif |
f0d96110 TH |
586 | .endm |
587 | .macro UNWIND_ESPFIX_STACK | |
34273f41 | 588 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 | 589 | movl %ss, %eax |
f0d96110 | 590 | /* see if on espfix stack */ |
a49976d1 IM |
591 | cmpw $__ESPFIX_SS, %ax |
592 | jne 27f | |
593 | movl $__KERNEL_DS, %eax | |
594 | movl %eax, %ds | |
595 | movl %eax, %es | |
f0d96110 TH |
596 | /* switch to normal stack */ |
597 | FIXUP_ESPFIX_STACK | |
598 | 27: | |
34273f41 | 599 | #endif |
f0d96110 | 600 | .endm |
1da177e4 LT |
601 | |
602 | /* | |
3304c9c3 DV |
603 | * Build the entry stubs with some assembler magic. |
604 | * We pack 1 stub into every 8-byte block. | |
1da177e4 | 605 | */ |
3304c9c3 | 606 | .align 8 |
1da177e4 | 607 | ENTRY(irq_entries_start) |
3304c9c3 DV |
608 | vector=FIRST_EXTERNAL_VECTOR |
609 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
a49976d1 | 610 | pushl $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
611 | vector=vector+1 |
612 | jmp common_interrupt | |
3304c9c3 DV |
613 | .align 8 |
614 | .endr | |
47a55cd7 JB |
615 | END(irq_entries_start) |
616 | ||
55f327fa IM |
617 | /* |
618 | * the CPU automatically disables interrupts when executing an IRQ vector, | |
619 | * so IRQ-flags tracing has to follow that: | |
620 | */ | |
b7c6244f | 621 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
1da177e4 | 622 | common_interrupt: |
e59d1b0a | 623 | ASM_CLAC |
a49976d1 | 624 | addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */ |
1da177e4 | 625 | SAVE_ALL |
55f327fa | 626 | TRACE_IRQS_OFF |
a49976d1 IM |
627 | movl %esp, %eax |
628 | call do_IRQ | |
629 | jmp ret_from_intr | |
47a55cd7 | 630 | ENDPROC(common_interrupt) |
1da177e4 | 631 | |
02cf94c3 | 632 | #define BUILD_INTERRUPT3(name, nr, fn) \ |
1da177e4 | 633 | ENTRY(name) \ |
e59d1b0a | 634 | ASM_CLAC; \ |
a49976d1 | 635 | pushl $~(nr); \ |
fe7cacc1 | 636 | SAVE_ALL; \ |
55f327fa | 637 | TRACE_IRQS_OFF \ |
a49976d1 IM |
638 | movl %esp, %eax; \ |
639 | call fn; \ | |
640 | jmp ret_from_intr; \ | |
47a55cd7 | 641 | ENDPROC(name) |
1da177e4 | 642 | |
cf910e83 SA |
643 | |
644 | #ifdef CONFIG_TRACING | |
a49976d1 | 645 | # define TRACE_BUILD_INTERRUPT(name, nr) BUILD_INTERRUPT3(trace_##name, nr, smp_trace_##name) |
cf910e83 | 646 | #else |
a49976d1 | 647 | # define TRACE_BUILD_INTERRUPT(name, nr) |
cf910e83 SA |
648 | #endif |
649 | ||
a49976d1 IM |
650 | #define BUILD_INTERRUPT(name, nr) \ |
651 | BUILD_INTERRUPT3(name, nr, smp_##name); \ | |
cf910e83 | 652 | TRACE_BUILD_INTERRUPT(name, nr) |
02cf94c3 | 653 | |
1da177e4 | 654 | /* The include is where all of the SMP etc. interrupts come from */ |
1164dd00 | 655 | #include <asm/entry_arch.h> |
1da177e4 | 656 | |
1da177e4 | 657 | ENTRY(coprocessor_error) |
e59d1b0a | 658 | ASM_CLAC |
a49976d1 IM |
659 | pushl $0 |
660 | pushl $do_coprocessor_error | |
661 | jmp error_code | |
47a55cd7 | 662 | END(coprocessor_error) |
1da177e4 LT |
663 | |
664 | ENTRY(simd_coprocessor_error) | |
e59d1b0a | 665 | ASM_CLAC |
a49976d1 | 666 | pushl $0 |
40d2e763 BG |
667 | #ifdef CONFIG_X86_INVD_BUG |
668 | /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */ | |
a49976d1 IM |
669 | ALTERNATIVE "pushl $do_general_protection", \ |
670 | "pushl $do_simd_coprocessor_error", \ | |
8e65f6e0 | 671 | X86_FEATURE_XMM |
40d2e763 | 672 | #else |
a49976d1 | 673 | pushl $do_simd_coprocessor_error |
40d2e763 | 674 | #endif |
a49976d1 | 675 | jmp error_code |
47a55cd7 | 676 | END(simd_coprocessor_error) |
1da177e4 LT |
677 | |
678 | ENTRY(device_not_available) | |
e59d1b0a | 679 | ASM_CLAC |
a49976d1 IM |
680 | pushl $-1 # mark this as an int |
681 | pushl $do_device_not_available | |
682 | jmp error_code | |
47a55cd7 | 683 | END(device_not_available) |
1da177e4 | 684 | |
d3561b7f RR |
685 | #ifdef CONFIG_PARAVIRT |
686 | ENTRY(native_iret) | |
3701d863 | 687 | iret |
6837a54d | 688 | _ASM_EXTABLE(native_iret, iret_exc) |
47a55cd7 | 689 | END(native_iret) |
d3561b7f RR |
690 | #endif |
691 | ||
1da177e4 | 692 | ENTRY(overflow) |
e59d1b0a | 693 | ASM_CLAC |
a49976d1 IM |
694 | pushl $0 |
695 | pushl $do_overflow | |
696 | jmp error_code | |
47a55cd7 | 697 | END(overflow) |
1da177e4 LT |
698 | |
699 | ENTRY(bounds) | |
e59d1b0a | 700 | ASM_CLAC |
a49976d1 IM |
701 | pushl $0 |
702 | pushl $do_bounds | |
703 | jmp error_code | |
47a55cd7 | 704 | END(bounds) |
1da177e4 LT |
705 | |
706 | ENTRY(invalid_op) | |
e59d1b0a | 707 | ASM_CLAC |
a49976d1 IM |
708 | pushl $0 |
709 | pushl $do_invalid_op | |
710 | jmp error_code | |
47a55cd7 | 711 | END(invalid_op) |
1da177e4 LT |
712 | |
713 | ENTRY(coprocessor_segment_overrun) | |
e59d1b0a | 714 | ASM_CLAC |
a49976d1 IM |
715 | pushl $0 |
716 | pushl $do_coprocessor_segment_overrun | |
717 | jmp error_code | |
47a55cd7 | 718 | END(coprocessor_segment_overrun) |
1da177e4 LT |
719 | |
720 | ENTRY(invalid_TSS) | |
e59d1b0a | 721 | ASM_CLAC |
a49976d1 IM |
722 | pushl $do_invalid_TSS |
723 | jmp error_code | |
47a55cd7 | 724 | END(invalid_TSS) |
1da177e4 LT |
725 | |
726 | ENTRY(segment_not_present) | |
e59d1b0a | 727 | ASM_CLAC |
a49976d1 IM |
728 | pushl $do_segment_not_present |
729 | jmp error_code | |
47a55cd7 | 730 | END(segment_not_present) |
1da177e4 LT |
731 | |
732 | ENTRY(stack_segment) | |
e59d1b0a | 733 | ASM_CLAC |
a49976d1 IM |
734 | pushl $do_stack_segment |
735 | jmp error_code | |
47a55cd7 | 736 | END(stack_segment) |
1da177e4 | 737 | |
1da177e4 | 738 | ENTRY(alignment_check) |
e59d1b0a | 739 | ASM_CLAC |
a49976d1 IM |
740 | pushl $do_alignment_check |
741 | jmp error_code | |
47a55cd7 | 742 | END(alignment_check) |
1da177e4 | 743 | |
d28c4393 | 744 | ENTRY(divide_error) |
e59d1b0a | 745 | ASM_CLAC |
a49976d1 IM |
746 | pushl $0 # no error code |
747 | pushl $do_divide_error | |
748 | jmp error_code | |
47a55cd7 | 749 | END(divide_error) |
1da177e4 LT |
750 | |
751 | #ifdef CONFIG_X86_MCE | |
752 | ENTRY(machine_check) | |
e59d1b0a | 753 | ASM_CLAC |
a49976d1 IM |
754 | pushl $0 |
755 | pushl machine_check_vector | |
756 | jmp error_code | |
47a55cd7 | 757 | END(machine_check) |
1da177e4 LT |
758 | #endif |
759 | ||
760 | ENTRY(spurious_interrupt_bug) | |
e59d1b0a | 761 | ASM_CLAC |
a49976d1 IM |
762 | pushl $0 |
763 | pushl $do_spurious_interrupt_bug | |
764 | jmp error_code | |
47a55cd7 | 765 | END(spurious_interrupt_bug) |
1da177e4 | 766 | |
5ead97c8 JF |
767 | #ifdef CONFIG_XEN |
768 | ENTRY(xen_hypervisor_callback) | |
a49976d1 | 769 | pushl $-1 /* orig_ax = -1 => not a system call */ |
5ead97c8 JF |
770 | SAVE_ALL |
771 | TRACE_IRQS_OFF | |
9ec2b804 | 772 | |
a49976d1 IM |
773 | /* |
774 | * Check to see if we got the event in the critical | |
775 | * region in xen_iret_direct, after we've reenabled | |
776 | * events and checked for pending events. This simulates | |
777 | * iret instruction's behaviour where it delivers a | |
778 | * pending interrupt when enabling interrupts: | |
779 | */ | |
780 | movl PT_EIP(%esp), %eax | |
781 | cmpl $xen_iret_start_crit, %eax | |
782 | jb 1f | |
783 | cmpl $xen_iret_end_crit, %eax | |
784 | jae 1f | |
9ec2b804 | 785 | |
a49976d1 | 786 | jmp xen_iret_crit_fixup |
e2a81baf | 787 | |
e2a81baf | 788 | ENTRY(xen_do_upcall) |
a49976d1 IM |
789 | 1: mov %esp, %eax |
790 | call xen_evtchn_do_upcall | |
fdfd811d | 791 | #ifndef CONFIG_PREEMPT |
a49976d1 | 792 | call xen_maybe_preempt_hcall |
fdfd811d | 793 | #endif |
a49976d1 | 794 | jmp ret_from_intr |
5ead97c8 JF |
795 | ENDPROC(xen_hypervisor_callback) |
796 | ||
a49976d1 IM |
797 | /* |
798 | * Hypervisor uses this for application faults while it executes. | |
799 | * We get here for two reasons: | |
800 | * 1. Fault while reloading DS, ES, FS or GS | |
801 | * 2. Fault while executing IRET | |
802 | * Category 1 we fix up by reattempting the load, and zeroing the segment | |
803 | * register if the load fails. | |
804 | * Category 2 we fix up by jumping to do_iret_error. We cannot use the | |
805 | * normal Linux return path in this case because if we use the IRET hypercall | |
806 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
807 | * We distinguish between categories by maintaining a status value in EAX. | |
808 | */ | |
5ead97c8 | 809 | ENTRY(xen_failsafe_callback) |
a49976d1 IM |
810 | pushl %eax |
811 | movl $1, %eax | |
812 | 1: mov 4(%esp), %ds | |
813 | 2: mov 8(%esp), %es | |
814 | 3: mov 12(%esp), %fs | |
815 | 4: mov 16(%esp), %gs | |
a349e23d DV |
816 | /* EAX == 0 => Category 1 (Bad segment) |
817 | EAX != 0 => Category 2 (Bad IRET) */ | |
a49976d1 IM |
818 | testl %eax, %eax |
819 | popl %eax | |
820 | lea 16(%esp), %esp | |
821 | jz 5f | |
822 | jmp iret_exc | |
823 | 5: pushl $-1 /* orig_ax = -1 => not a system call */ | |
5ead97c8 | 824 | SAVE_ALL |
a49976d1 IM |
825 | jmp ret_from_exception |
826 | ||
827 | .section .fixup, "ax" | |
828 | 6: xorl %eax, %eax | |
829 | movl %eax, 4(%esp) | |
830 | jmp 1b | |
831 | 7: xorl %eax, %eax | |
832 | movl %eax, 8(%esp) | |
833 | jmp 2b | |
834 | 8: xorl %eax, %eax | |
835 | movl %eax, 12(%esp) | |
836 | jmp 3b | |
837 | 9: xorl %eax, %eax | |
838 | movl %eax, 16(%esp) | |
839 | jmp 4b | |
5ead97c8 | 840 | .previous |
a49976d1 IM |
841 | _ASM_EXTABLE(1b, 6b) |
842 | _ASM_EXTABLE(2b, 7b) | |
843 | _ASM_EXTABLE(3b, 8b) | |
844 | _ASM_EXTABLE(4b, 9b) | |
5ead97c8 JF |
845 | ENDPROC(xen_failsafe_callback) |
846 | ||
bc2b0331 | 847 | BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR, |
38e20b07 SY |
848 | xen_evtchn_do_upcall) |
849 | ||
a49976d1 | 850 | #endif /* CONFIG_XEN */ |
bc2b0331 S |
851 | |
852 | #if IS_ENABLED(CONFIG_HYPERV) | |
853 | ||
854 | BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR, | |
855 | hyperv_vector_handler) | |
856 | ||
857 | #endif /* CONFIG_HYPERV */ | |
5ead97c8 | 858 | |
606576ce | 859 | #ifdef CONFIG_FUNCTION_TRACER |
d61f82d0 SR |
860 | #ifdef CONFIG_DYNAMIC_FTRACE |
861 | ||
862 | ENTRY(mcount) | |
d61f82d0 SR |
863 | ret |
864 | END(mcount) | |
865 | ||
866 | ENTRY(ftrace_caller) | |
a49976d1 IM |
867 | pushl %eax |
868 | pushl %ecx | |
869 | pushl %edx | |
870 | pushl $0 /* Pass NULL as regs pointer */ | |
871 | movl 4*4(%esp), %eax | |
872 | movl 0x4(%ebp), %edx | |
873 | movl function_trace_op, %ecx | |
874 | subl $MCOUNT_INSN_SIZE, %eax | |
d61f82d0 SR |
875 | |
876 | .globl ftrace_call | |
877 | ftrace_call: | |
a49976d1 | 878 | call ftrace_stub |
d61f82d0 | 879 | |
a49976d1 IM |
880 | addl $4, %esp /* skip NULL pointer */ |
881 | popl %edx | |
882 | popl %ecx | |
883 | popl %eax | |
4de72395 | 884 | ftrace_ret: |
5a45cfe1 SR |
885 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
886 | .globl ftrace_graph_call | |
887 | ftrace_graph_call: | |
a49976d1 | 888 | jmp ftrace_stub |
5a45cfe1 | 889 | #endif |
d61f82d0 SR |
890 | |
891 | .globl ftrace_stub | |
892 | ftrace_stub: | |
893 | ret | |
894 | END(ftrace_caller) | |
895 | ||
4de72395 SR |
896 | ENTRY(ftrace_regs_caller) |
897 | pushf /* push flags before compare (in cs location) */ | |
4de72395 SR |
898 | |
899 | /* | |
900 | * i386 does not save SS and ESP when coming from kernel. | |
901 | * Instead, to get sp, ®s->sp is used (see ptrace.h). | |
902 | * Unfortunately, that means eflags must be at the same location | |
903 | * as the current return ip is. We move the return ip into the | |
904 | * ip location, and move flags into the return ip location. | |
905 | */ | |
a49976d1 IM |
906 | pushl 4(%esp) /* save return ip into ip slot */ |
907 | ||
908 | pushl $0 /* Load 0 into orig_ax */ | |
909 | pushl %gs | |
910 | pushl %fs | |
911 | pushl %es | |
912 | pushl %ds | |
913 | pushl %eax | |
914 | pushl %ebp | |
915 | pushl %edi | |
916 | pushl %esi | |
917 | pushl %edx | |
918 | pushl %ecx | |
919 | pushl %ebx | |
920 | ||
921 | movl 13*4(%esp), %eax /* Get the saved flags */ | |
922 | movl %eax, 14*4(%esp) /* Move saved flags into regs->flags location */ | |
923 | /* clobbering return ip */ | |
924 | movl $__KERNEL_CS, 13*4(%esp) | |
925 | ||
926 | movl 12*4(%esp), %eax /* Load ip (1st parameter) */ | |
927 | subl $MCOUNT_INSN_SIZE, %eax /* Adjust ip */ | |
928 | movl 0x4(%ebp), %edx /* Load parent ip (2nd parameter) */ | |
929 | movl function_trace_op, %ecx /* Save ftrace_pos in 3rd parameter */ | |
930 | pushl %esp /* Save pt_regs as 4th parameter */ | |
4de72395 SR |
931 | |
932 | GLOBAL(ftrace_regs_call) | |
a49976d1 IM |
933 | call ftrace_stub |
934 | ||
935 | addl $4, %esp /* Skip pt_regs */ | |
936 | movl 14*4(%esp), %eax /* Move flags back into cs */ | |
937 | movl %eax, 13*4(%esp) /* Needed to keep addl from modifying flags */ | |
938 | movl 12*4(%esp), %eax /* Get return ip from regs->ip */ | |
939 | movl %eax, 14*4(%esp) /* Put return ip back for ret */ | |
940 | ||
941 | popl %ebx | |
942 | popl %ecx | |
943 | popl %edx | |
944 | popl %esi | |
945 | popl %edi | |
946 | popl %ebp | |
947 | popl %eax | |
948 | popl %ds | |
949 | popl %es | |
950 | popl %fs | |
951 | popl %gs | |
952 | addl $8, %esp /* Skip orig_ax and ip */ | |
953 | popf /* Pop flags at end (no addl to corrupt flags) */ | |
954 | jmp ftrace_ret | |
4de72395 | 955 | |
4de72395 | 956 | popf |
a49976d1 | 957 | jmp ftrace_stub |
d61f82d0 SR |
958 | #else /* ! CONFIG_DYNAMIC_FTRACE */ |
959 | ||
16444a8a | 960 | ENTRY(mcount) |
a49976d1 IM |
961 | cmpl $__PAGE_OFFSET, %esp |
962 | jb ftrace_stub /* Paging not enabled yet? */ | |
af058ab0 | 963 | |
a49976d1 IM |
964 | cmpl $ftrace_stub, ftrace_trace_function |
965 | jnz trace | |
fb52607a | 966 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
a49976d1 IM |
967 | cmpl $ftrace_stub, ftrace_graph_return |
968 | jnz ftrace_graph_caller | |
e49dc19c | 969 | |
a49976d1 IM |
970 | cmpl $ftrace_graph_entry_stub, ftrace_graph_entry |
971 | jnz ftrace_graph_caller | |
caf4b323 | 972 | #endif |
16444a8a ACM |
973 | .globl ftrace_stub |
974 | ftrace_stub: | |
975 | ret | |
976 | ||
977 | /* taken from glibc */ | |
978 | trace: | |
a49976d1 IM |
979 | pushl %eax |
980 | pushl %ecx | |
981 | pushl %edx | |
982 | movl 0xc(%esp), %eax | |
983 | movl 0x4(%ebp), %edx | |
984 | subl $MCOUNT_INSN_SIZE, %eax | |
985 | ||
986 | call *ftrace_trace_function | |
987 | ||
988 | popl %edx | |
989 | popl %ecx | |
990 | popl %eax | |
991 | jmp ftrace_stub | |
16444a8a | 992 | END(mcount) |
d61f82d0 | 993 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
606576ce | 994 | #endif /* CONFIG_FUNCTION_TRACER */ |
16444a8a | 995 | |
fb52607a FW |
996 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
997 | ENTRY(ftrace_graph_caller) | |
a49976d1 IM |
998 | pushl %eax |
999 | pushl %ecx | |
1000 | pushl %edx | |
1001 | movl 0xc(%esp), %eax | |
1002 | lea 0x4(%ebp), %edx | |
1003 | movl (%ebp), %ecx | |
1004 | subl $MCOUNT_INSN_SIZE, %eax | |
1005 | call prepare_ftrace_return | |
1006 | popl %edx | |
1007 | popl %ecx | |
1008 | popl %eax | |
e7d3737e | 1009 | ret |
fb52607a | 1010 | END(ftrace_graph_caller) |
caf4b323 FW |
1011 | |
1012 | .globl return_to_handler | |
1013 | return_to_handler: | |
a49976d1 IM |
1014 | pushl %eax |
1015 | pushl %edx | |
1016 | movl %ebp, %eax | |
1017 | call ftrace_return_to_handler | |
1018 | movl %eax, %ecx | |
1019 | popl %edx | |
1020 | popl %eax | |
1021 | jmp *%ecx | |
e7d3737e | 1022 | #endif |
16444a8a | 1023 | |
25c74b10 SA |
1024 | #ifdef CONFIG_TRACING |
1025 | ENTRY(trace_page_fault) | |
25c74b10 | 1026 | ASM_CLAC |
a49976d1 IM |
1027 | pushl $trace_do_page_fault |
1028 | jmp error_code | |
25c74b10 SA |
1029 | END(trace_page_fault) |
1030 | #endif | |
1031 | ||
d211af05 | 1032 | ENTRY(page_fault) |
e59d1b0a | 1033 | ASM_CLAC |
a49976d1 | 1034 | pushl $do_page_fault |
d211af05 AH |
1035 | ALIGN |
1036 | error_code: | |
ccbeed3a | 1037 | /* the function address is in %gs's slot on the stack */ |
a49976d1 IM |
1038 | pushl %fs |
1039 | pushl %es | |
1040 | pushl %ds | |
1041 | pushl %eax | |
1042 | pushl %ebp | |
1043 | pushl %edi | |
1044 | pushl %esi | |
1045 | pushl %edx | |
1046 | pushl %ecx | |
1047 | pushl %ebx | |
d211af05 | 1048 | cld |
a49976d1 IM |
1049 | movl $(__KERNEL_PERCPU), %ecx |
1050 | movl %ecx, %fs | |
d211af05 | 1051 | UNWIND_ESPFIX_STACK |
ccbeed3a | 1052 | GS_TO_REG %ecx |
a49976d1 IM |
1053 | movl PT_GS(%esp), %edi # get the function address |
1054 | movl PT_ORIG_EAX(%esp), %edx # get the error code | |
1055 | movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart | |
ccbeed3a TH |
1056 | REG_TO_PTGS %ecx |
1057 | SET_KERNEL_GS %ecx | |
a49976d1 IM |
1058 | movl $(__USER_DS), %ecx |
1059 | movl %ecx, %ds | |
1060 | movl %ecx, %es | |
d211af05 | 1061 | TRACE_IRQS_OFF |
a49976d1 IM |
1062 | movl %esp, %eax # pt_regs pointer |
1063 | call *%edi | |
1064 | jmp ret_from_exception | |
d211af05 AH |
1065 | END(page_fault) |
1066 | ||
d211af05 | 1067 | ENTRY(debug) |
7536656f AL |
1068 | /* |
1069 | * #DB can happen at the first instruction of | |
1070 | * entry_SYSENTER_32 or in Xen's SYSENTER prologue. If this | |
1071 | * happens, then we will be running on a very small stack. We | |
1072 | * need to detect this condition and switch to the thread | |
1073 | * stack before calling any C code at all. | |
1074 | * | |
1075 | * If you edit this code, keep in mind that NMIs can happen in here. | |
1076 | */ | |
e59d1b0a | 1077 | ASM_CLAC |
a49976d1 | 1078 | pushl $-1 # mark this as an int |
d211af05 | 1079 | SAVE_ALL |
a49976d1 IM |
1080 | xorl %edx, %edx # error code 0 |
1081 | movl %esp, %eax # pt_regs pointer | |
7536656f AL |
1082 | |
1083 | /* Are we currently on the SYSENTER stack? */ | |
1084 | PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) | |
1085 | subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ | |
1086 | cmpl $SIZEOF_SYSENTER_stack, %ecx | |
1087 | jb .Ldebug_from_sysenter_stack | |
1088 | ||
1089 | TRACE_IRQS_OFF | |
1090 | call do_debug | |
1091 | jmp ret_from_exception | |
1092 | ||
1093 | .Ldebug_from_sysenter_stack: | |
1094 | /* We're on the SYSENTER stack. Switch off. */ | |
1095 | movl %esp, %ebp | |
1096 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esp | |
1097 | TRACE_IRQS_OFF | |
a49976d1 | 1098 | call do_debug |
7536656f | 1099 | movl %ebp, %esp |
a49976d1 | 1100 | jmp ret_from_exception |
d211af05 AH |
1101 | END(debug) |
1102 | ||
1103 | /* | |
7536656f AL |
1104 | * NMI is doubly nasty. It can happen on the first instruction of |
1105 | * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning | |
1106 | * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32 | |
1107 | * switched stacks. We handle both conditions by simply checking whether we | |
1108 | * interrupted kernel code running on the SYSENTER stack. | |
d211af05 AH |
1109 | */ |
1110 | ENTRY(nmi) | |
e59d1b0a | 1111 | ASM_CLAC |
34273f41 | 1112 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 IM |
1113 | pushl %eax |
1114 | movl %ss, %eax | |
1115 | cmpw $__ESPFIX_SS, %ax | |
1116 | popl %eax | |
1117 | je nmi_espfix_stack | |
34273f41 | 1118 | #endif |
7536656f AL |
1119 | |
1120 | pushl %eax # pt_regs->orig_ax | |
d211af05 | 1121 | SAVE_ALL |
a49976d1 IM |
1122 | xorl %edx, %edx # zero error code |
1123 | movl %esp, %eax # pt_regs pointer | |
7536656f AL |
1124 | |
1125 | /* Are we currently on the SYSENTER stack? */ | |
1126 | PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) | |
1127 | subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ | |
1128 | cmpl $SIZEOF_SYSENTER_stack, %ecx | |
1129 | jb .Lnmi_from_sysenter_stack | |
1130 | ||
1131 | /* Not on SYSENTER stack. */ | |
a49976d1 IM |
1132 | call do_nmi |
1133 | jmp restore_all_notrace | |
d211af05 | 1134 | |
7536656f AL |
1135 | .Lnmi_from_sysenter_stack: |
1136 | /* | |
1137 | * We're on the SYSENTER stack. Switch off. No one (not even debug) | |
1138 | * is using the thread stack right now, so it's safe for us to use it. | |
1139 | */ | |
1140 | movl %esp, %ebp | |
1141 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esp | |
1142 | call do_nmi | |
1143 | movl %ebp, %esp | |
1144 | jmp restore_all_notrace | |
d211af05 | 1145 | |
34273f41 | 1146 | #ifdef CONFIG_X86_ESPFIX32 |
d211af05 | 1147 | nmi_espfix_stack: |
131484c8 | 1148 | /* |
d211af05 AH |
1149 | * create the pointer to lss back |
1150 | */ | |
a49976d1 IM |
1151 | pushl %ss |
1152 | pushl %esp | |
1153 | addl $4, (%esp) | |
d211af05 AH |
1154 | /* copy the iret frame of 12 bytes */ |
1155 | .rept 3 | |
a49976d1 | 1156 | pushl 16(%esp) |
d211af05 | 1157 | .endr |
a49976d1 | 1158 | pushl %eax |
d211af05 | 1159 | SAVE_ALL |
a49976d1 IM |
1160 | FIXUP_ESPFIX_STACK # %eax == %esp |
1161 | xorl %edx, %edx # zero error code | |
1162 | call do_nmi | |
d211af05 | 1163 | RESTORE_REGS |
a49976d1 IM |
1164 | lss 12+4(%esp), %esp # back to espfix stack |
1165 | jmp irq_return | |
34273f41 | 1166 | #endif |
d211af05 AH |
1167 | END(nmi) |
1168 | ||
1169 | ENTRY(int3) | |
e59d1b0a | 1170 | ASM_CLAC |
a49976d1 | 1171 | pushl $-1 # mark this as an int |
d211af05 AH |
1172 | SAVE_ALL |
1173 | TRACE_IRQS_OFF | |
a49976d1 IM |
1174 | xorl %edx, %edx # zero error code |
1175 | movl %esp, %eax # pt_regs pointer | |
1176 | call do_int3 | |
1177 | jmp ret_from_exception | |
d211af05 AH |
1178 | END(int3) |
1179 | ||
1180 | ENTRY(general_protection) | |
a49976d1 IM |
1181 | pushl $do_general_protection |
1182 | jmp error_code | |
d211af05 AH |
1183 | END(general_protection) |
1184 | ||
631bc487 GN |
1185 | #ifdef CONFIG_KVM_GUEST |
1186 | ENTRY(async_page_fault) | |
e59d1b0a | 1187 | ASM_CLAC |
a49976d1 IM |
1188 | pushl $do_async_page_fault |
1189 | jmp error_code | |
2ae9d293 | 1190 | END(async_page_fault) |
631bc487 | 1191 | #endif |
2deb4be2 AL |
1192 | |
1193 | ENTRY(rewind_stack_do_exit) | |
1194 | /* Prevent any naive code from trying to unwind to our caller. */ | |
1195 | xorl %ebp, %ebp | |
1196 | ||
1197 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esi | |
1198 | leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp | |
1199 | ||
1200 | call do_exit | |
1201 | 1: jmp 1b | |
1202 | END(rewind_stack_do_exit) |