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Commit | Line | Data |
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1da177e4 | 1 | /* |
a49976d1 | 2 | * Copyright (C) 1991,1992 Linus Torvalds |
1da177e4 | 3 | * |
a49976d1 | 4 | * entry_32.S contains the system-call and low-level fault and trap handling routines. |
1da177e4 | 5 | * |
39e8701f | 6 | * Stack layout while running C code: |
a49976d1 IM |
7 | * ptrace needs to have all registers on the stack. |
8 | * If the order here is changed, it needs to be | |
9 | * updated in fork.c:copy_process(), signal.c:do_signal(), | |
1da177e4 LT |
10 | * ptrace.c and ptrace.h |
11 | * | |
12 | * 0(%esp) - %ebx | |
13 | * 4(%esp) - %ecx | |
14 | * 8(%esp) - %edx | |
9b47feb7 | 15 | * C(%esp) - %esi |
1da177e4 LT |
16 | * 10(%esp) - %edi |
17 | * 14(%esp) - %ebp | |
18 | * 18(%esp) - %eax | |
19 | * 1C(%esp) - %ds | |
20 | * 20(%esp) - %es | |
464d1a78 | 21 | * 24(%esp) - %fs |
ccbeed3a TH |
22 | * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS |
23 | * 2C(%esp) - orig_eax | |
24 | * 30(%esp) - %eip | |
25 | * 34(%esp) - %cs | |
26 | * 38(%esp) - %eflags | |
27 | * 3C(%esp) - %oldesp | |
28 | * 40(%esp) - %oldss | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 | 31 | #include <linux/linkage.h> |
d7e7528b | 32 | #include <linux/err.h> |
1da177e4 | 33 | #include <asm/thread_info.h> |
55f327fa | 34 | #include <asm/irqflags.h> |
1da177e4 LT |
35 | #include <asm/errno.h> |
36 | #include <asm/segment.h> | |
37 | #include <asm/smp.h> | |
0341c14d | 38 | #include <asm/page_types.h> |
be44d2aa | 39 | #include <asm/percpu.h> |
ab68ed98 | 40 | #include <asm/processor-flags.h> |
395a59d0 | 41 | #include <asm/ftrace.h> |
9b7dc567 | 42 | #include <asm/irq_vectors.h> |
cd4d09ec | 43 | #include <asm/cpufeatures.h> |
b4ca46e4 | 44 | #include <asm/alternative-asm.h> |
6837a54d | 45 | #include <asm/asm.h> |
e59d1b0a | 46 | #include <asm/smap.h> |
784d5699 | 47 | #include <asm/export.h> |
4d516f41 | 48 | #include <asm/frame.h> |
1da177e4 | 49 | |
ea714547 JO |
50 | .section .entry.text, "ax" |
51 | ||
139ec7c4 RR |
52 | /* |
53 | * We use macros for low-level operations which need to be overridden | |
54 | * for paravirtualization. The following will never clobber any registers: | |
55 | * INTERRUPT_RETURN (aka. "iret") | |
56 | * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax") | |
d75cd22f | 57 | * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit"). |
139ec7c4 RR |
58 | * |
59 | * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must | |
60 | * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY). | |
61 | * Allowing a register to be clobbered can shrink the paravirt replacement | |
62 | * enough to patch inline, increasing performance. | |
63 | */ | |
64 | ||
1da177e4 | 65 | #ifdef CONFIG_PREEMPT |
a49976d1 | 66 | # define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF |
1da177e4 | 67 | #else |
a49976d1 IM |
68 | # define preempt_stop(clobbers) |
69 | # define resume_kernel restore_all | |
1da177e4 LT |
70 | #endif |
71 | ||
55f327fa IM |
72 | .macro TRACE_IRQS_IRET |
73 | #ifdef CONFIG_TRACE_IRQFLAGS | |
a49976d1 IM |
74 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off? |
75 | jz 1f | |
55f327fa IM |
76 | TRACE_IRQS_ON |
77 | 1: | |
78 | #endif | |
79 | .endm | |
80 | ||
ccbeed3a TH |
81 | /* |
82 | * User gs save/restore | |
83 | * | |
84 | * %gs is used for userland TLS and kernel only uses it for stack | |
85 | * canary which is required to be at %gs:20 by gcc. Read the comment | |
86 | * at the top of stackprotector.h for more info. | |
87 | * | |
88 | * Local labels 98 and 99 are used. | |
89 | */ | |
90 | #ifdef CONFIG_X86_32_LAZY_GS | |
91 | ||
92 | /* unfortunately push/pop can't be no-op */ | |
93 | .macro PUSH_GS | |
a49976d1 | 94 | pushl $0 |
ccbeed3a TH |
95 | .endm |
96 | .macro POP_GS pop=0 | |
a49976d1 | 97 | addl $(4 + \pop), %esp |
ccbeed3a TH |
98 | .endm |
99 | .macro POP_GS_EX | |
100 | .endm | |
101 | ||
102 | /* all the rest are no-op */ | |
103 | .macro PTGS_TO_GS | |
104 | .endm | |
105 | .macro PTGS_TO_GS_EX | |
106 | .endm | |
107 | .macro GS_TO_REG reg | |
108 | .endm | |
109 | .macro REG_TO_PTGS reg | |
110 | .endm | |
111 | .macro SET_KERNEL_GS reg | |
112 | .endm | |
113 | ||
114 | #else /* CONFIG_X86_32_LAZY_GS */ | |
115 | ||
116 | .macro PUSH_GS | |
a49976d1 | 117 | pushl %gs |
ccbeed3a TH |
118 | .endm |
119 | ||
120 | .macro POP_GS pop=0 | |
a49976d1 | 121 | 98: popl %gs |
ccbeed3a | 122 | .if \pop <> 0 |
9b47feb7 | 123 | add $\pop, %esp |
ccbeed3a TH |
124 | .endif |
125 | .endm | |
126 | .macro POP_GS_EX | |
127 | .pushsection .fixup, "ax" | |
a49976d1 IM |
128 | 99: movl $0, (%esp) |
129 | jmp 98b | |
ccbeed3a | 130 | .popsection |
a49976d1 | 131 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
132 | .endm |
133 | ||
134 | .macro PTGS_TO_GS | |
a49976d1 | 135 | 98: mov PT_GS(%esp), %gs |
ccbeed3a TH |
136 | .endm |
137 | .macro PTGS_TO_GS_EX | |
138 | .pushsection .fixup, "ax" | |
a49976d1 IM |
139 | 99: movl $0, PT_GS(%esp) |
140 | jmp 98b | |
ccbeed3a | 141 | .popsection |
a49976d1 | 142 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
143 | .endm |
144 | ||
145 | .macro GS_TO_REG reg | |
a49976d1 | 146 | movl %gs, \reg |
ccbeed3a TH |
147 | .endm |
148 | .macro REG_TO_PTGS reg | |
a49976d1 | 149 | movl \reg, PT_GS(%esp) |
ccbeed3a TH |
150 | .endm |
151 | .macro SET_KERNEL_GS reg | |
a49976d1 IM |
152 | movl $(__KERNEL_STACK_CANARY), \reg |
153 | movl \reg, %gs | |
ccbeed3a TH |
154 | .endm |
155 | ||
a49976d1 | 156 | #endif /* CONFIG_X86_32_LAZY_GS */ |
ccbeed3a | 157 | |
150ac78d | 158 | .macro SAVE_ALL pt_regs_ax=%eax |
f0d96110 | 159 | cld |
ccbeed3a | 160 | PUSH_GS |
a49976d1 IM |
161 | pushl %fs |
162 | pushl %es | |
163 | pushl %ds | |
150ac78d | 164 | pushl \pt_regs_ax |
a49976d1 IM |
165 | pushl %ebp |
166 | pushl %edi | |
167 | pushl %esi | |
168 | pushl %edx | |
169 | pushl %ecx | |
170 | pushl %ebx | |
171 | movl $(__USER_DS), %edx | |
172 | movl %edx, %ds | |
173 | movl %edx, %es | |
174 | movl $(__KERNEL_PERCPU), %edx | |
175 | movl %edx, %fs | |
ccbeed3a | 176 | SET_KERNEL_GS %edx |
f0d96110 | 177 | .endm |
1da177e4 | 178 | |
f0d96110 | 179 | .macro RESTORE_INT_REGS |
a49976d1 IM |
180 | popl %ebx |
181 | popl %ecx | |
182 | popl %edx | |
183 | popl %esi | |
184 | popl %edi | |
185 | popl %ebp | |
186 | popl %eax | |
f0d96110 | 187 | .endm |
1da177e4 | 188 | |
ccbeed3a | 189 | .macro RESTORE_REGS pop=0 |
f0d96110 | 190 | RESTORE_INT_REGS |
a49976d1 IM |
191 | 1: popl %ds |
192 | 2: popl %es | |
193 | 3: popl %fs | |
ccbeed3a | 194 | POP_GS \pop |
f0d96110 | 195 | .pushsection .fixup, "ax" |
a49976d1 IM |
196 | 4: movl $0, (%esp) |
197 | jmp 1b | |
198 | 5: movl $0, (%esp) | |
199 | jmp 2b | |
200 | 6: movl $0, (%esp) | |
201 | jmp 3b | |
f95d47ca | 202 | .popsection |
a49976d1 IM |
203 | _ASM_EXTABLE(1b, 4b) |
204 | _ASM_EXTABLE(2b, 5b) | |
205 | _ASM_EXTABLE(3b, 6b) | |
ccbeed3a | 206 | POP_GS_EX |
f0d96110 | 207 | .endm |
1da177e4 | 208 | |
0100301b BG |
209 | /* |
210 | * %eax: prev task | |
211 | * %edx: next task | |
212 | */ | |
213 | ENTRY(__switch_to_asm) | |
214 | /* | |
215 | * Save callee-saved registers | |
216 | * This must match the order in struct inactive_task_frame | |
217 | */ | |
218 | pushl %ebp | |
219 | pushl %ebx | |
220 | pushl %edi | |
221 | pushl %esi | |
222 | ||
223 | /* switch stack */ | |
224 | movl %esp, TASK_threadsp(%eax) | |
225 | movl TASK_threadsp(%edx), %esp | |
226 | ||
227 | #ifdef CONFIG_CC_STACKPROTECTOR | |
228 | movl TASK_stack_canary(%edx), %ebx | |
229 | movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset | |
230 | #endif | |
231 | ||
232 | /* restore callee-saved registers */ | |
233 | popl %esi | |
234 | popl %edi | |
235 | popl %ebx | |
236 | popl %ebp | |
237 | ||
238 | jmp __switch_to | |
239 | END(__switch_to_asm) | |
240 | ||
4d516f41 JP |
241 | /* |
242 | * The unwinder expects the last frame on the stack to always be at the same | |
243 | * offset from the end of the page, which allows it to validate the stack. | |
244 | * Calling schedule_tail() directly would break that convention because its an | |
245 | * asmlinkage function so its argument has to be pushed on the stack. This | |
246 | * wrapper creates a proper "end of stack" frame header before the call. | |
247 | */ | |
248 | ENTRY(schedule_tail_wrapper) | |
249 | FRAME_BEGIN | |
250 | ||
251 | pushl %eax | |
252 | call schedule_tail | |
253 | popl %eax | |
254 | ||
255 | FRAME_END | |
256 | ret | |
257 | ENDPROC(schedule_tail_wrapper) | |
0100301b BG |
258 | /* |
259 | * A newly forked process directly context switches into this address. | |
260 | * | |
261 | * eax: prev task we switched from | |
616d2483 BG |
262 | * ebx: kernel thread func (NULL for user thread) |
263 | * edi: kernel thread arg | |
0100301b | 264 | */ |
1da177e4 | 265 | ENTRY(ret_from_fork) |
4d516f41 | 266 | call schedule_tail_wrapper |
39e8701f | 267 | |
616d2483 BG |
268 | testl %ebx, %ebx |
269 | jnz 1f /* kernel threads are uncommon */ | |
270 | ||
271 | 2: | |
39e8701f AL |
272 | /* When we fork, we trace the syscall return in the child, too. */ |
273 | movl %esp, %eax | |
274 | call syscall_return_slowpath | |
275 | jmp restore_all | |
39e8701f | 276 | |
616d2483 BG |
277 | /* kernel thread */ |
278 | 1: movl %edi, %eax | |
279 | call *%ebx | |
39e8701f | 280 | /* |
616d2483 BG |
281 | * A kernel thread is allowed to return here after successfully |
282 | * calling do_execve(). Exit to userspace to complete the execve() | |
283 | * syscall. | |
39e8701f | 284 | */ |
616d2483 BG |
285 | movl $0, PT_EAX(%esp) |
286 | jmp 2b | |
287 | END(ret_from_fork) | |
6783eaa2 | 288 | |
1da177e4 LT |
289 | /* |
290 | * Return to user mode is not as complex as all this looks, | |
291 | * but we want the default path for a system call return to | |
292 | * go as quickly as possible which is why some of this is | |
293 | * less clear than it otherwise should be. | |
294 | */ | |
295 | ||
296 | # userspace resumption stub bypassing syscall exit tracing | |
297 | ALIGN | |
298 | ret_from_exception: | |
139ec7c4 | 299 | preempt_stop(CLBR_ANY) |
1da177e4 | 300 | ret_from_intr: |
29a2e283 | 301 | #ifdef CONFIG_VM86 |
a49976d1 IM |
302 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS |
303 | movb PT_CS(%esp), %al | |
304 | andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax | |
29a2e283 DA |
305 | #else |
306 | /* | |
6783eaa2 | 307 | * We can be coming here from child spawned by kernel_thread(). |
29a2e283 | 308 | */ |
a49976d1 IM |
309 | movl PT_CS(%esp), %eax |
310 | andl $SEGMENT_RPL_MASK, %eax | |
29a2e283 | 311 | #endif |
a49976d1 IM |
312 | cmpl $USER_RPL, %eax |
313 | jb resume_kernel # not returning to v8086 or userspace | |
f95d47ca | 314 | |
1da177e4 | 315 | ENTRY(resume_userspace) |
5d73fc70 | 316 | DISABLE_INTERRUPTS(CLBR_ANY) |
e32e58a9 | 317 | TRACE_IRQS_OFF |
5d73fc70 AL |
318 | movl %esp, %eax |
319 | call prepare_exit_to_usermode | |
a49976d1 | 320 | jmp restore_all |
47a55cd7 | 321 | END(ret_from_exception) |
1da177e4 LT |
322 | |
323 | #ifdef CONFIG_PREEMPT | |
324 | ENTRY(resume_kernel) | |
139ec7c4 | 325 | DISABLE_INTERRUPTS(CLBR_ANY) |
1b00255f | 326 | .Lneed_resched: |
a49976d1 IM |
327 | cmpl $0, PER_CPU_VAR(__preempt_count) |
328 | jnz restore_all | |
329 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ? | |
330 | jz restore_all | |
331 | call preempt_schedule_irq | |
1b00255f | 332 | jmp .Lneed_resched |
47a55cd7 | 333 | END(resume_kernel) |
1da177e4 LT |
334 | #endif |
335 | ||
f2b37575 AL |
336 | GLOBAL(__begin_SYSENTER_singlestep_region) |
337 | /* | |
338 | * All code from here through __end_SYSENTER_singlestep_region is subject | |
339 | * to being single-stepped if a user program sets TF and executes SYSENTER. | |
340 | * There is absolutely nothing that we can do to prevent this from happening | |
341 | * (thanks Intel!). To keep our handling of this situation as simple as | |
342 | * possible, we handle TF just like AC and NT, except that our #DB handler | |
343 | * will ignore all of the single-step traps generated in this range. | |
344 | */ | |
345 | ||
346 | #ifdef CONFIG_XEN | |
347 | /* | |
348 | * Xen doesn't set %esp to be precisely what the normal SYSENTER | |
349 | * entry point expects, so fix it up before using the normal path. | |
350 | */ | |
351 | ENTRY(xen_sysenter_target) | |
352 | addl $5*4, %esp /* remove xen-provided frame */ | |
1b00255f | 353 | jmp .Lsysenter_past_esp |
f2b37575 AL |
354 | #endif |
355 | ||
fda57b22 AL |
356 | /* |
357 | * 32-bit SYSENTER entry. | |
358 | * | |
359 | * 32-bit system calls through the vDSO's __kernel_vsyscall enter here | |
360 | * if X86_FEATURE_SEP is available. This is the preferred system call | |
361 | * entry on 32-bit systems. | |
362 | * | |
363 | * The SYSENTER instruction, in principle, should *only* occur in the | |
364 | * vDSO. In practice, a small number of Android devices were shipped | |
365 | * with a copy of Bionic that inlined a SYSENTER instruction. This | |
366 | * never happened in any of Google's Bionic versions -- it only happened | |
367 | * in a narrow range of Intel-provided versions. | |
368 | * | |
369 | * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs. | |
370 | * IF and VM in RFLAGS are cleared (IOW: interrupts are off). | |
371 | * SYSENTER does not save anything on the stack, | |
372 | * and does not save old EIP (!!!), ESP, or EFLAGS. | |
373 | * | |
374 | * To avoid losing track of EFLAGS.VM (and thus potentially corrupting | |
375 | * user and/or vm86 state), we explicitly disable the SYSENTER | |
376 | * instruction in vm86 mode by reprogramming the MSRs. | |
377 | * | |
378 | * Arguments: | |
379 | * eax system call number | |
380 | * ebx arg1 | |
381 | * ecx arg2 | |
382 | * edx arg3 | |
383 | * esi arg4 | |
384 | * edi arg5 | |
385 | * ebp user stack | |
386 | * 0(%ebp) arg6 | |
387 | */ | |
4c8cd0c5 | 388 | ENTRY(entry_SYSENTER_32) |
a49976d1 | 389 | movl TSS_sysenter_sp0(%esp), %esp |
1b00255f | 390 | .Lsysenter_past_esp: |
5f310f73 | 391 | pushl $__USER_DS /* pt_regs->ss */ |
30bfa7b3 | 392 | pushl %ebp /* pt_regs->sp (stashed in bp) */ |
5f310f73 AL |
393 | pushfl /* pt_regs->flags (except IF = 0) */ |
394 | orl $X86_EFLAGS_IF, (%esp) /* Fix IF */ | |
395 | pushl $__USER_CS /* pt_regs->cs */ | |
396 | pushl $0 /* pt_regs->ip = 0 (placeholder) */ | |
397 | pushl %eax /* pt_regs->orig_ax */ | |
398 | SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest */ | |
399 | ||
67f590e8 | 400 | /* |
f2b37575 AL |
401 | * SYSENTER doesn't filter flags, so we need to clear NT, AC |
402 | * and TF ourselves. To save a few cycles, we can check whether | |
67f590e8 AL |
403 | * either was set instead of doing an unconditional popfq. |
404 | * This needs to happen before enabling interrupts so that | |
405 | * we don't get preempted with NT set. | |
406 | * | |
f2b37575 AL |
407 | * If TF is set, we will single-step all the way to here -- do_debug |
408 | * will ignore all the traps. (Yes, this is slow, but so is | |
409 | * single-stepping in general. This allows us to avoid having | |
410 | * a more complicated code to handle the case where a user program | |
411 | * forces us to single-step through the SYSENTER entry code.) | |
412 | * | |
67f590e8 AL |
413 | * NB.: .Lsysenter_fix_flags is a label with the code under it moved |
414 | * out-of-line as an optimization: NT is unlikely to be set in the | |
415 | * majority of the cases and instead of polluting the I$ unnecessarily, | |
416 | * we're keeping that code behind a branch which will predict as | |
417 | * not-taken and therefore its instructions won't be fetched. | |
418 | */ | |
f2b37575 | 419 | testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp) |
67f590e8 AL |
420 | jnz .Lsysenter_fix_flags |
421 | .Lsysenter_flags_fixed: | |
422 | ||
55f327fa | 423 | /* |
5f310f73 AL |
424 | * User mode is traced as though IRQs are on, and SYSENTER |
425 | * turned them off. | |
e6e5494c | 426 | */ |
55f327fa | 427 | TRACE_IRQS_OFF |
5f310f73 AL |
428 | |
429 | movl %esp, %eax | |
430 | call do_fast_syscall_32 | |
91e2eea9 BO |
431 | /* XEN PV guests always use IRET path */ |
432 | ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \ | |
433 | "jmp .Lsyscall_32_done", X86_FEATURE_XENPV | |
5f310f73 AL |
434 | |
435 | /* Opportunistic SYSEXIT */ | |
436 | TRACE_IRQS_ON /* User mode traces as IRQs on. */ | |
437 | movl PT_EIP(%esp), %edx /* pt_regs->ip */ | |
438 | movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */ | |
3bd29515 AL |
439 | 1: mov PT_FS(%esp), %fs |
440 | PTGS_TO_GS | |
5f310f73 AL |
441 | popl %ebx /* pt_regs->bx */ |
442 | addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */ | |
443 | popl %esi /* pt_regs->si */ | |
444 | popl %edi /* pt_regs->di */ | |
445 | popl %ebp /* pt_regs->bp */ | |
446 | popl %eax /* pt_regs->ax */ | |
5f310f73 | 447 | |
c2c9b52f AL |
448 | /* |
449 | * Restore all flags except IF. (We restore IF separately because | |
450 | * STI gives a one-instruction window in which we won't be interrupted, | |
451 | * whereas POPF does not.) | |
452 | */ | |
453 | addl $PT_EFLAGS-PT_DS, %esp /* point esp at pt_regs->flags */ | |
454 | btr $X86_EFLAGS_IF_BIT, (%esp) | |
455 | popfl | |
456 | ||
5f310f73 AL |
457 | /* |
458 | * Return back to the vDSO, which will pop ecx and edx. | |
459 | * Don't bother with DS and ES (they already contain __USER_DS). | |
460 | */ | |
88c15ec9 BO |
461 | sti |
462 | sysexit | |
af0575bb | 463 | |
a49976d1 IM |
464 | .pushsection .fixup, "ax" |
465 | 2: movl $0, PT_FS(%esp) | |
466 | jmp 1b | |
f95d47ca | 467 | .popsection |
a49976d1 | 468 | _ASM_EXTABLE(1b, 2b) |
ccbeed3a | 469 | PTGS_TO_GS_EX |
67f590e8 AL |
470 | |
471 | .Lsysenter_fix_flags: | |
472 | pushl $X86_EFLAGS_FIXED | |
473 | popfl | |
474 | jmp .Lsysenter_flags_fixed | |
f2b37575 | 475 | GLOBAL(__end_SYSENTER_singlestep_region) |
4c8cd0c5 | 476 | ENDPROC(entry_SYSENTER_32) |
1da177e4 | 477 | |
fda57b22 AL |
478 | /* |
479 | * 32-bit legacy system call entry. | |
480 | * | |
481 | * 32-bit x86 Linux system calls traditionally used the INT $0x80 | |
482 | * instruction. INT $0x80 lands here. | |
483 | * | |
484 | * This entry point can be used by any 32-bit perform system calls. | |
485 | * Instances of INT $0x80 can be found inline in various programs and | |
486 | * libraries. It is also used by the vDSO's __kernel_vsyscall | |
487 | * fallback for hardware that doesn't support a faster entry method. | |
488 | * Restarted 32-bit system calls also fall back to INT $0x80 | |
489 | * regardless of what instruction was originally used to do the system | |
490 | * call. (64-bit programs can use INT $0x80 as well, but they can | |
491 | * only run on 64-bit kernels and therefore land in | |
492 | * entry_INT80_compat.) | |
493 | * | |
494 | * This is considered a slow path. It is not used by most libc | |
495 | * implementations on modern hardware except during process startup. | |
496 | * | |
497 | * Arguments: | |
498 | * eax system call number | |
499 | * ebx arg1 | |
500 | * ecx arg2 | |
501 | * edx arg3 | |
502 | * esi arg4 | |
503 | * edi arg5 | |
504 | * ebp arg6 | |
505 | */ | |
b2502b41 | 506 | ENTRY(entry_INT80_32) |
e59d1b0a | 507 | ASM_CLAC |
150ac78d | 508 | pushl %eax /* pt_regs->orig_ax */ |
5f310f73 | 509 | SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest */ |
150ac78d AL |
510 | |
511 | /* | |
a798f091 AL |
512 | * User mode is traced as though IRQs are on, and the interrupt gate |
513 | * turned them off. | |
150ac78d | 514 | */ |
a798f091 | 515 | TRACE_IRQS_OFF |
150ac78d AL |
516 | |
517 | movl %esp, %eax | |
a798f091 | 518 | call do_int80_syscall_32 |
5f310f73 | 519 | .Lsyscall_32_done: |
1da177e4 LT |
520 | |
521 | restore_all: | |
2e04bc76 | 522 | TRACE_IRQS_IRET |
1b00255f | 523 | .Lrestore_all_notrace: |
34273f41 | 524 | #ifdef CONFIG_X86_ESPFIX32 |
1b00255f | 525 | ALTERNATIVE "jmp .Lrestore_nocheck", "", X86_BUG_ESPFIX |
58a5aac5 | 526 | |
a49976d1 IM |
527 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS |
528 | /* | |
529 | * Warning: PT_OLDSS(%esp) contains the wrong/random values if we | |
530 | * are returning to the kernel. | |
531 | * See comments in process.c:copy_thread() for details. | |
532 | */ | |
533 | movb PT_OLDSS(%esp), %ah | |
534 | movb PT_CS(%esp), %al | |
535 | andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax | |
536 | cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax | |
1b00255f | 537 | je .Lldt_ss # returning to user-space with LDT SS |
34273f41 | 538 | #endif |
1b00255f | 539 | .Lrestore_nocheck: |
a49976d1 | 540 | RESTORE_REGS 4 # skip orig_eax/error_code |
1b00255f | 541 | .Lirq_return: |
3701d863 | 542 | INTERRUPT_RETURN |
1b00255f | 543 | |
a49976d1 IM |
544 | .section .fixup, "ax" |
545 | ENTRY(iret_exc ) | |
546 | pushl $0 # no error code | |
547 | pushl $do_iret_error | |
7252c4c3 | 548 | jmp common_exception |
1da177e4 | 549 | .previous |
1b00255f | 550 | _ASM_EXTABLE(.Lirq_return, iret_exc) |
1da177e4 | 551 | |
34273f41 | 552 | #ifdef CONFIG_X86_ESPFIX32 |
1b00255f | 553 | .Lldt_ss: |
dc4c2a0a AH |
554 | /* |
555 | * Setup and switch to ESPFIX stack | |
556 | * | |
557 | * We're returning to userspace with a 16 bit stack. The CPU will not | |
558 | * restore the high word of ESP for us on executing iret... This is an | |
559 | * "official" bug of all the x86-compatible CPUs, which we can work | |
560 | * around to make dosemu and wine happy. We do this by preloading the | |
561 | * high word of ESP with the high word of the userspace ESP while | |
562 | * compensating for the offset by changing to the ESPFIX segment with | |
563 | * a base address that matches for the difference. | |
564 | */ | |
72c511dd | 565 | #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8) |
a49976d1 IM |
566 | mov %esp, %edx /* load kernel esp */ |
567 | mov PT_OLDESP(%esp), %eax /* load userspace esp */ | |
568 | mov %dx, %ax /* eax: new kernel esp */ | |
9b47feb7 DV |
569 | sub %eax, %edx /* offset (low word is 0) */ |
570 | shr $16, %edx | |
a49976d1 IM |
571 | mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */ |
572 | mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */ | |
573 | pushl $__ESPFIX_SS | |
574 | pushl %eax /* new kernel esp */ | |
575 | /* | |
576 | * Disable interrupts, but do not irqtrace this section: we | |
2e04bc76 | 577 | * will soon execute iret and the tracer was already set to |
a49976d1 IM |
578 | * the irqstate after the IRET: |
579 | */ | |
139ec7c4 | 580 | DISABLE_INTERRUPTS(CLBR_EAX) |
a49976d1 | 581 | lss (%esp), %esp /* switch to espfix segment */ |
1b00255f | 582 | jmp .Lrestore_nocheck |
34273f41 | 583 | #endif |
b2502b41 | 584 | ENDPROC(entry_INT80_32) |
1da177e4 | 585 | |
f0d96110 | 586 | .macro FIXUP_ESPFIX_STACK |
dc4c2a0a AH |
587 | /* |
588 | * Switch back for ESPFIX stack to the normal zerobased stack | |
589 | * | |
590 | * We can't call C functions using the ESPFIX stack. This code reads | |
591 | * the high word of the segment base from the GDT and swiches to the | |
592 | * normal stack and adjusts ESP with the matching offset. | |
593 | */ | |
34273f41 | 594 | #ifdef CONFIG_X86_ESPFIX32 |
dc4c2a0a | 595 | /* fixup the stack */ |
a49976d1 IM |
596 | mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */ |
597 | mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */ | |
9b47feb7 | 598 | shl $16, %eax |
a49976d1 IM |
599 | addl %esp, %eax /* the adjusted stack pointer */ |
600 | pushl $__KERNEL_DS | |
601 | pushl %eax | |
602 | lss (%esp), %esp /* switch to the normal stack segment */ | |
34273f41 | 603 | #endif |
f0d96110 TH |
604 | .endm |
605 | .macro UNWIND_ESPFIX_STACK | |
34273f41 | 606 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 | 607 | movl %ss, %eax |
f0d96110 | 608 | /* see if on espfix stack */ |
a49976d1 IM |
609 | cmpw $__ESPFIX_SS, %ax |
610 | jne 27f | |
611 | movl $__KERNEL_DS, %eax | |
612 | movl %eax, %ds | |
613 | movl %eax, %es | |
f0d96110 TH |
614 | /* switch to normal stack */ |
615 | FIXUP_ESPFIX_STACK | |
616 | 27: | |
34273f41 | 617 | #endif |
f0d96110 | 618 | .endm |
1da177e4 LT |
619 | |
620 | /* | |
3304c9c3 DV |
621 | * Build the entry stubs with some assembler magic. |
622 | * We pack 1 stub into every 8-byte block. | |
1da177e4 | 623 | */ |
3304c9c3 | 624 | .align 8 |
1da177e4 | 625 | ENTRY(irq_entries_start) |
3304c9c3 DV |
626 | vector=FIRST_EXTERNAL_VECTOR |
627 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
a49976d1 | 628 | pushl $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
629 | vector=vector+1 |
630 | jmp common_interrupt | |
3304c9c3 DV |
631 | .align 8 |
632 | .endr | |
47a55cd7 JB |
633 | END(irq_entries_start) |
634 | ||
55f327fa IM |
635 | /* |
636 | * the CPU automatically disables interrupts when executing an IRQ vector, | |
637 | * so IRQ-flags tracing has to follow that: | |
638 | */ | |
b7c6244f | 639 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
1da177e4 | 640 | common_interrupt: |
e59d1b0a | 641 | ASM_CLAC |
a49976d1 | 642 | addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */ |
1da177e4 | 643 | SAVE_ALL |
55f327fa | 644 | TRACE_IRQS_OFF |
a49976d1 IM |
645 | movl %esp, %eax |
646 | call do_IRQ | |
647 | jmp ret_from_intr | |
47a55cd7 | 648 | ENDPROC(common_interrupt) |
1da177e4 | 649 | |
02cf94c3 | 650 | #define BUILD_INTERRUPT3(name, nr, fn) \ |
1da177e4 | 651 | ENTRY(name) \ |
e59d1b0a | 652 | ASM_CLAC; \ |
a49976d1 | 653 | pushl $~(nr); \ |
fe7cacc1 | 654 | SAVE_ALL; \ |
55f327fa | 655 | TRACE_IRQS_OFF \ |
a49976d1 IM |
656 | movl %esp, %eax; \ |
657 | call fn; \ | |
658 | jmp ret_from_intr; \ | |
47a55cd7 | 659 | ENDPROC(name) |
1da177e4 | 660 | |
cf910e83 SA |
661 | |
662 | #ifdef CONFIG_TRACING | |
a49976d1 | 663 | # define TRACE_BUILD_INTERRUPT(name, nr) BUILD_INTERRUPT3(trace_##name, nr, smp_trace_##name) |
cf910e83 | 664 | #else |
a49976d1 | 665 | # define TRACE_BUILD_INTERRUPT(name, nr) |
cf910e83 SA |
666 | #endif |
667 | ||
a49976d1 IM |
668 | #define BUILD_INTERRUPT(name, nr) \ |
669 | BUILD_INTERRUPT3(name, nr, smp_##name); \ | |
cf910e83 | 670 | TRACE_BUILD_INTERRUPT(name, nr) |
02cf94c3 | 671 | |
1da177e4 | 672 | /* The include is where all of the SMP etc. interrupts come from */ |
1164dd00 | 673 | #include <asm/entry_arch.h> |
1da177e4 | 674 | |
1da177e4 | 675 | ENTRY(coprocessor_error) |
e59d1b0a | 676 | ASM_CLAC |
a49976d1 IM |
677 | pushl $0 |
678 | pushl $do_coprocessor_error | |
7252c4c3 | 679 | jmp common_exception |
47a55cd7 | 680 | END(coprocessor_error) |
1da177e4 LT |
681 | |
682 | ENTRY(simd_coprocessor_error) | |
e59d1b0a | 683 | ASM_CLAC |
a49976d1 | 684 | pushl $0 |
40d2e763 BG |
685 | #ifdef CONFIG_X86_INVD_BUG |
686 | /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */ | |
a49976d1 IM |
687 | ALTERNATIVE "pushl $do_general_protection", \ |
688 | "pushl $do_simd_coprocessor_error", \ | |
8e65f6e0 | 689 | X86_FEATURE_XMM |
40d2e763 | 690 | #else |
a49976d1 | 691 | pushl $do_simd_coprocessor_error |
40d2e763 | 692 | #endif |
7252c4c3 | 693 | jmp common_exception |
47a55cd7 | 694 | END(simd_coprocessor_error) |
1da177e4 LT |
695 | |
696 | ENTRY(device_not_available) | |
e59d1b0a | 697 | ASM_CLAC |
a49976d1 IM |
698 | pushl $-1 # mark this as an int |
699 | pushl $do_device_not_available | |
7252c4c3 | 700 | jmp common_exception |
47a55cd7 | 701 | END(device_not_available) |
1da177e4 | 702 | |
d3561b7f RR |
703 | #ifdef CONFIG_PARAVIRT |
704 | ENTRY(native_iret) | |
3701d863 | 705 | iret |
6837a54d | 706 | _ASM_EXTABLE(native_iret, iret_exc) |
47a55cd7 | 707 | END(native_iret) |
d3561b7f RR |
708 | #endif |
709 | ||
1da177e4 | 710 | ENTRY(overflow) |
e59d1b0a | 711 | ASM_CLAC |
a49976d1 IM |
712 | pushl $0 |
713 | pushl $do_overflow | |
7252c4c3 | 714 | jmp common_exception |
47a55cd7 | 715 | END(overflow) |
1da177e4 LT |
716 | |
717 | ENTRY(bounds) | |
e59d1b0a | 718 | ASM_CLAC |
a49976d1 IM |
719 | pushl $0 |
720 | pushl $do_bounds | |
7252c4c3 | 721 | jmp common_exception |
47a55cd7 | 722 | END(bounds) |
1da177e4 LT |
723 | |
724 | ENTRY(invalid_op) | |
e59d1b0a | 725 | ASM_CLAC |
a49976d1 IM |
726 | pushl $0 |
727 | pushl $do_invalid_op | |
7252c4c3 | 728 | jmp common_exception |
47a55cd7 | 729 | END(invalid_op) |
1da177e4 LT |
730 | |
731 | ENTRY(coprocessor_segment_overrun) | |
e59d1b0a | 732 | ASM_CLAC |
a49976d1 IM |
733 | pushl $0 |
734 | pushl $do_coprocessor_segment_overrun | |
7252c4c3 | 735 | jmp common_exception |
47a55cd7 | 736 | END(coprocessor_segment_overrun) |
1da177e4 LT |
737 | |
738 | ENTRY(invalid_TSS) | |
e59d1b0a | 739 | ASM_CLAC |
a49976d1 | 740 | pushl $do_invalid_TSS |
7252c4c3 | 741 | jmp common_exception |
47a55cd7 | 742 | END(invalid_TSS) |
1da177e4 LT |
743 | |
744 | ENTRY(segment_not_present) | |
e59d1b0a | 745 | ASM_CLAC |
a49976d1 | 746 | pushl $do_segment_not_present |
7252c4c3 | 747 | jmp common_exception |
47a55cd7 | 748 | END(segment_not_present) |
1da177e4 LT |
749 | |
750 | ENTRY(stack_segment) | |
e59d1b0a | 751 | ASM_CLAC |
a49976d1 | 752 | pushl $do_stack_segment |
7252c4c3 | 753 | jmp common_exception |
47a55cd7 | 754 | END(stack_segment) |
1da177e4 | 755 | |
1da177e4 | 756 | ENTRY(alignment_check) |
e59d1b0a | 757 | ASM_CLAC |
a49976d1 | 758 | pushl $do_alignment_check |
7252c4c3 | 759 | jmp common_exception |
47a55cd7 | 760 | END(alignment_check) |
1da177e4 | 761 | |
d28c4393 | 762 | ENTRY(divide_error) |
e59d1b0a | 763 | ASM_CLAC |
a49976d1 IM |
764 | pushl $0 # no error code |
765 | pushl $do_divide_error | |
7252c4c3 | 766 | jmp common_exception |
47a55cd7 | 767 | END(divide_error) |
1da177e4 LT |
768 | |
769 | #ifdef CONFIG_X86_MCE | |
770 | ENTRY(machine_check) | |
e59d1b0a | 771 | ASM_CLAC |
a49976d1 IM |
772 | pushl $0 |
773 | pushl machine_check_vector | |
7252c4c3 | 774 | jmp common_exception |
47a55cd7 | 775 | END(machine_check) |
1da177e4 LT |
776 | #endif |
777 | ||
778 | ENTRY(spurious_interrupt_bug) | |
e59d1b0a | 779 | ASM_CLAC |
a49976d1 IM |
780 | pushl $0 |
781 | pushl $do_spurious_interrupt_bug | |
7252c4c3 | 782 | jmp common_exception |
47a55cd7 | 783 | END(spurious_interrupt_bug) |
1da177e4 | 784 | |
5ead97c8 JF |
785 | #ifdef CONFIG_XEN |
786 | ENTRY(xen_hypervisor_callback) | |
a49976d1 | 787 | pushl $-1 /* orig_ax = -1 => not a system call */ |
5ead97c8 JF |
788 | SAVE_ALL |
789 | TRACE_IRQS_OFF | |
9ec2b804 | 790 | |
a49976d1 IM |
791 | /* |
792 | * Check to see if we got the event in the critical | |
793 | * region in xen_iret_direct, after we've reenabled | |
794 | * events and checked for pending events. This simulates | |
795 | * iret instruction's behaviour where it delivers a | |
796 | * pending interrupt when enabling interrupts: | |
797 | */ | |
798 | movl PT_EIP(%esp), %eax | |
799 | cmpl $xen_iret_start_crit, %eax | |
800 | jb 1f | |
801 | cmpl $xen_iret_end_crit, %eax | |
802 | jae 1f | |
9ec2b804 | 803 | |
a49976d1 | 804 | jmp xen_iret_crit_fixup |
e2a81baf | 805 | |
e2a81baf | 806 | ENTRY(xen_do_upcall) |
a49976d1 IM |
807 | 1: mov %esp, %eax |
808 | call xen_evtchn_do_upcall | |
fdfd811d | 809 | #ifndef CONFIG_PREEMPT |
a49976d1 | 810 | call xen_maybe_preempt_hcall |
fdfd811d | 811 | #endif |
a49976d1 | 812 | jmp ret_from_intr |
5ead97c8 JF |
813 | ENDPROC(xen_hypervisor_callback) |
814 | ||
a49976d1 IM |
815 | /* |
816 | * Hypervisor uses this for application faults while it executes. | |
817 | * We get here for two reasons: | |
818 | * 1. Fault while reloading DS, ES, FS or GS | |
819 | * 2. Fault while executing IRET | |
820 | * Category 1 we fix up by reattempting the load, and zeroing the segment | |
821 | * register if the load fails. | |
822 | * Category 2 we fix up by jumping to do_iret_error. We cannot use the | |
823 | * normal Linux return path in this case because if we use the IRET hypercall | |
824 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
825 | * We distinguish between categories by maintaining a status value in EAX. | |
826 | */ | |
5ead97c8 | 827 | ENTRY(xen_failsafe_callback) |
a49976d1 IM |
828 | pushl %eax |
829 | movl $1, %eax | |
830 | 1: mov 4(%esp), %ds | |
831 | 2: mov 8(%esp), %es | |
832 | 3: mov 12(%esp), %fs | |
833 | 4: mov 16(%esp), %gs | |
a349e23d DV |
834 | /* EAX == 0 => Category 1 (Bad segment) |
835 | EAX != 0 => Category 2 (Bad IRET) */ | |
a49976d1 IM |
836 | testl %eax, %eax |
837 | popl %eax | |
838 | lea 16(%esp), %esp | |
839 | jz 5f | |
840 | jmp iret_exc | |
841 | 5: pushl $-1 /* orig_ax = -1 => not a system call */ | |
5ead97c8 | 842 | SAVE_ALL |
a49976d1 IM |
843 | jmp ret_from_exception |
844 | ||
845 | .section .fixup, "ax" | |
846 | 6: xorl %eax, %eax | |
847 | movl %eax, 4(%esp) | |
848 | jmp 1b | |
849 | 7: xorl %eax, %eax | |
850 | movl %eax, 8(%esp) | |
851 | jmp 2b | |
852 | 8: xorl %eax, %eax | |
853 | movl %eax, 12(%esp) | |
854 | jmp 3b | |
855 | 9: xorl %eax, %eax | |
856 | movl %eax, 16(%esp) | |
857 | jmp 4b | |
5ead97c8 | 858 | .previous |
a49976d1 IM |
859 | _ASM_EXTABLE(1b, 6b) |
860 | _ASM_EXTABLE(2b, 7b) | |
861 | _ASM_EXTABLE(3b, 8b) | |
862 | _ASM_EXTABLE(4b, 9b) | |
5ead97c8 JF |
863 | ENDPROC(xen_failsafe_callback) |
864 | ||
bc2b0331 | 865 | BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR, |
38e20b07 SY |
866 | xen_evtchn_do_upcall) |
867 | ||
a49976d1 | 868 | #endif /* CONFIG_XEN */ |
bc2b0331 S |
869 | |
870 | #if IS_ENABLED(CONFIG_HYPERV) | |
871 | ||
872 | BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR, | |
873 | hyperv_vector_handler) | |
874 | ||
875 | #endif /* CONFIG_HYPERV */ | |
5ead97c8 | 876 | |
606576ce | 877 | #ifdef CONFIG_FUNCTION_TRACER |
d61f82d0 SR |
878 | #ifdef CONFIG_DYNAMIC_FTRACE |
879 | ||
880 | ENTRY(mcount) | |
d61f82d0 SR |
881 | ret |
882 | END(mcount) | |
883 | ||
884 | ENTRY(ftrace_caller) | |
a49976d1 IM |
885 | pushl %eax |
886 | pushl %ecx | |
887 | pushl %edx | |
888 | pushl $0 /* Pass NULL as regs pointer */ | |
889 | movl 4*4(%esp), %eax | |
890 | movl 0x4(%ebp), %edx | |
891 | movl function_trace_op, %ecx | |
892 | subl $MCOUNT_INSN_SIZE, %eax | |
d61f82d0 SR |
893 | |
894 | .globl ftrace_call | |
895 | ftrace_call: | |
a49976d1 | 896 | call ftrace_stub |
d61f82d0 | 897 | |
a49976d1 IM |
898 | addl $4, %esp /* skip NULL pointer */ |
899 | popl %edx | |
900 | popl %ecx | |
901 | popl %eax | |
1b00255f | 902 | .Lftrace_ret: |
5a45cfe1 SR |
903 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
904 | .globl ftrace_graph_call | |
905 | ftrace_graph_call: | |
a49976d1 | 906 | jmp ftrace_stub |
5a45cfe1 | 907 | #endif |
d61f82d0 SR |
908 | |
909 | .globl ftrace_stub | |
910 | ftrace_stub: | |
911 | ret | |
912 | END(ftrace_caller) | |
913 | ||
4de72395 SR |
914 | ENTRY(ftrace_regs_caller) |
915 | pushf /* push flags before compare (in cs location) */ | |
4de72395 SR |
916 | |
917 | /* | |
918 | * i386 does not save SS and ESP when coming from kernel. | |
919 | * Instead, to get sp, ®s->sp is used (see ptrace.h). | |
920 | * Unfortunately, that means eflags must be at the same location | |
921 | * as the current return ip is. We move the return ip into the | |
922 | * ip location, and move flags into the return ip location. | |
923 | */ | |
a49976d1 IM |
924 | pushl 4(%esp) /* save return ip into ip slot */ |
925 | ||
926 | pushl $0 /* Load 0 into orig_ax */ | |
927 | pushl %gs | |
928 | pushl %fs | |
929 | pushl %es | |
930 | pushl %ds | |
931 | pushl %eax | |
932 | pushl %ebp | |
933 | pushl %edi | |
934 | pushl %esi | |
935 | pushl %edx | |
936 | pushl %ecx | |
937 | pushl %ebx | |
938 | ||
939 | movl 13*4(%esp), %eax /* Get the saved flags */ | |
940 | movl %eax, 14*4(%esp) /* Move saved flags into regs->flags location */ | |
941 | /* clobbering return ip */ | |
942 | movl $__KERNEL_CS, 13*4(%esp) | |
943 | ||
944 | movl 12*4(%esp), %eax /* Load ip (1st parameter) */ | |
945 | subl $MCOUNT_INSN_SIZE, %eax /* Adjust ip */ | |
946 | movl 0x4(%ebp), %edx /* Load parent ip (2nd parameter) */ | |
947 | movl function_trace_op, %ecx /* Save ftrace_pos in 3rd parameter */ | |
948 | pushl %esp /* Save pt_regs as 4th parameter */ | |
4de72395 SR |
949 | |
950 | GLOBAL(ftrace_regs_call) | |
a49976d1 IM |
951 | call ftrace_stub |
952 | ||
953 | addl $4, %esp /* Skip pt_regs */ | |
954 | movl 14*4(%esp), %eax /* Move flags back into cs */ | |
955 | movl %eax, 13*4(%esp) /* Needed to keep addl from modifying flags */ | |
956 | movl 12*4(%esp), %eax /* Get return ip from regs->ip */ | |
957 | movl %eax, 14*4(%esp) /* Put return ip back for ret */ | |
958 | ||
959 | popl %ebx | |
960 | popl %ecx | |
961 | popl %edx | |
962 | popl %esi | |
963 | popl %edi | |
964 | popl %ebp | |
965 | popl %eax | |
966 | popl %ds | |
967 | popl %es | |
968 | popl %fs | |
969 | popl %gs | |
970 | addl $8, %esp /* Skip orig_ax and ip */ | |
971 | popf /* Pop flags at end (no addl to corrupt flags) */ | |
1b00255f | 972 | jmp .Lftrace_ret |
4de72395 | 973 | |
4de72395 | 974 | popf |
a49976d1 | 975 | jmp ftrace_stub |
d61f82d0 SR |
976 | #else /* ! CONFIG_DYNAMIC_FTRACE */ |
977 | ||
16444a8a | 978 | ENTRY(mcount) |
a49976d1 IM |
979 | cmpl $__PAGE_OFFSET, %esp |
980 | jb ftrace_stub /* Paging not enabled yet? */ | |
af058ab0 | 981 | |
a49976d1 | 982 | cmpl $ftrace_stub, ftrace_trace_function |
1b00255f | 983 | jnz .Ltrace |
fb52607a | 984 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
a49976d1 IM |
985 | cmpl $ftrace_stub, ftrace_graph_return |
986 | jnz ftrace_graph_caller | |
e49dc19c | 987 | |
a49976d1 IM |
988 | cmpl $ftrace_graph_entry_stub, ftrace_graph_entry |
989 | jnz ftrace_graph_caller | |
caf4b323 | 990 | #endif |
16444a8a ACM |
991 | .globl ftrace_stub |
992 | ftrace_stub: | |
993 | ret | |
994 | ||
995 | /* taken from glibc */ | |
1b00255f | 996 | .Ltrace: |
a49976d1 IM |
997 | pushl %eax |
998 | pushl %ecx | |
999 | pushl %edx | |
1000 | movl 0xc(%esp), %eax | |
1001 | movl 0x4(%ebp), %edx | |
1002 | subl $MCOUNT_INSN_SIZE, %eax | |
1003 | ||
1004 | call *ftrace_trace_function | |
1005 | ||
1006 | popl %edx | |
1007 | popl %ecx | |
1008 | popl %eax | |
1009 | jmp ftrace_stub | |
16444a8a | 1010 | END(mcount) |
d61f82d0 | 1011 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
784d5699 | 1012 | EXPORT_SYMBOL(mcount) |
606576ce | 1013 | #endif /* CONFIG_FUNCTION_TRACER */ |
16444a8a | 1014 | |
fb52607a FW |
1015 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1016 | ENTRY(ftrace_graph_caller) | |
a49976d1 IM |
1017 | pushl %eax |
1018 | pushl %ecx | |
1019 | pushl %edx | |
1020 | movl 0xc(%esp), %eax | |
1021 | lea 0x4(%ebp), %edx | |
1022 | movl (%ebp), %ecx | |
1023 | subl $MCOUNT_INSN_SIZE, %eax | |
1024 | call prepare_ftrace_return | |
1025 | popl %edx | |
1026 | popl %ecx | |
1027 | popl %eax | |
e7d3737e | 1028 | ret |
fb52607a | 1029 | END(ftrace_graph_caller) |
caf4b323 FW |
1030 | |
1031 | .globl return_to_handler | |
1032 | return_to_handler: | |
a49976d1 IM |
1033 | pushl %eax |
1034 | pushl %edx | |
1035 | movl %ebp, %eax | |
1036 | call ftrace_return_to_handler | |
1037 | movl %eax, %ecx | |
1038 | popl %edx | |
1039 | popl %eax | |
1040 | jmp *%ecx | |
e7d3737e | 1041 | #endif |
16444a8a | 1042 | |
25c74b10 SA |
1043 | #ifdef CONFIG_TRACING |
1044 | ENTRY(trace_page_fault) | |
25c74b10 | 1045 | ASM_CLAC |
a49976d1 | 1046 | pushl $trace_do_page_fault |
7252c4c3 | 1047 | jmp common_exception |
25c74b10 SA |
1048 | END(trace_page_fault) |
1049 | #endif | |
1050 | ||
d211af05 | 1051 | ENTRY(page_fault) |
e59d1b0a | 1052 | ASM_CLAC |
a49976d1 | 1053 | pushl $do_page_fault |
d211af05 | 1054 | ALIGN |
7252c4c3 JP |
1055 | jmp common_exception |
1056 | END(page_fault) | |
1057 | ||
1058 | common_exception: | |
ccbeed3a | 1059 | /* the function address is in %gs's slot on the stack */ |
a49976d1 IM |
1060 | pushl %fs |
1061 | pushl %es | |
1062 | pushl %ds | |
1063 | pushl %eax | |
1064 | pushl %ebp | |
1065 | pushl %edi | |
1066 | pushl %esi | |
1067 | pushl %edx | |
1068 | pushl %ecx | |
1069 | pushl %ebx | |
d211af05 | 1070 | cld |
a49976d1 IM |
1071 | movl $(__KERNEL_PERCPU), %ecx |
1072 | movl %ecx, %fs | |
d211af05 | 1073 | UNWIND_ESPFIX_STACK |
ccbeed3a | 1074 | GS_TO_REG %ecx |
a49976d1 IM |
1075 | movl PT_GS(%esp), %edi # get the function address |
1076 | movl PT_ORIG_EAX(%esp), %edx # get the error code | |
1077 | movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart | |
ccbeed3a TH |
1078 | REG_TO_PTGS %ecx |
1079 | SET_KERNEL_GS %ecx | |
a49976d1 IM |
1080 | movl $(__USER_DS), %ecx |
1081 | movl %ecx, %ds | |
1082 | movl %ecx, %es | |
d211af05 | 1083 | TRACE_IRQS_OFF |
a49976d1 IM |
1084 | movl %esp, %eax # pt_regs pointer |
1085 | call *%edi | |
1086 | jmp ret_from_exception | |
7252c4c3 | 1087 | END(common_exception) |
d211af05 | 1088 | |
d211af05 | 1089 | ENTRY(debug) |
7536656f AL |
1090 | /* |
1091 | * #DB can happen at the first instruction of | |
1092 | * entry_SYSENTER_32 or in Xen's SYSENTER prologue. If this | |
1093 | * happens, then we will be running on a very small stack. We | |
1094 | * need to detect this condition and switch to the thread | |
1095 | * stack before calling any C code at all. | |
1096 | * | |
1097 | * If you edit this code, keep in mind that NMIs can happen in here. | |
1098 | */ | |
e59d1b0a | 1099 | ASM_CLAC |
a49976d1 | 1100 | pushl $-1 # mark this as an int |
d211af05 | 1101 | SAVE_ALL |
a49976d1 IM |
1102 | xorl %edx, %edx # error code 0 |
1103 | movl %esp, %eax # pt_regs pointer | |
7536656f AL |
1104 | |
1105 | /* Are we currently on the SYSENTER stack? */ | |
1106 | PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) | |
1107 | subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ | |
1108 | cmpl $SIZEOF_SYSENTER_stack, %ecx | |
1109 | jb .Ldebug_from_sysenter_stack | |
1110 | ||
1111 | TRACE_IRQS_OFF | |
1112 | call do_debug | |
1113 | jmp ret_from_exception | |
1114 | ||
1115 | .Ldebug_from_sysenter_stack: | |
1116 | /* We're on the SYSENTER stack. Switch off. */ | |
1117 | movl %esp, %ebp | |
1118 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esp | |
1119 | TRACE_IRQS_OFF | |
a49976d1 | 1120 | call do_debug |
7536656f | 1121 | movl %ebp, %esp |
a49976d1 | 1122 | jmp ret_from_exception |
d211af05 AH |
1123 | END(debug) |
1124 | ||
1125 | /* | |
7536656f AL |
1126 | * NMI is doubly nasty. It can happen on the first instruction of |
1127 | * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning | |
1128 | * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32 | |
1129 | * switched stacks. We handle both conditions by simply checking whether we | |
1130 | * interrupted kernel code running on the SYSENTER stack. | |
d211af05 AH |
1131 | */ |
1132 | ENTRY(nmi) | |
e59d1b0a | 1133 | ASM_CLAC |
34273f41 | 1134 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 IM |
1135 | pushl %eax |
1136 | movl %ss, %eax | |
1137 | cmpw $__ESPFIX_SS, %ax | |
1138 | popl %eax | |
1b00255f | 1139 | je .Lnmi_espfix_stack |
34273f41 | 1140 | #endif |
7536656f AL |
1141 | |
1142 | pushl %eax # pt_regs->orig_ax | |
d211af05 | 1143 | SAVE_ALL |
a49976d1 IM |
1144 | xorl %edx, %edx # zero error code |
1145 | movl %esp, %eax # pt_regs pointer | |
7536656f AL |
1146 | |
1147 | /* Are we currently on the SYSENTER stack? */ | |
1148 | PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) | |
1149 | subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ | |
1150 | cmpl $SIZEOF_SYSENTER_stack, %ecx | |
1151 | jb .Lnmi_from_sysenter_stack | |
1152 | ||
1153 | /* Not on SYSENTER stack. */ | |
a49976d1 | 1154 | call do_nmi |
1b00255f | 1155 | jmp .Lrestore_all_notrace |
d211af05 | 1156 | |
7536656f AL |
1157 | .Lnmi_from_sysenter_stack: |
1158 | /* | |
1159 | * We're on the SYSENTER stack. Switch off. No one (not even debug) | |
1160 | * is using the thread stack right now, so it's safe for us to use it. | |
1161 | */ | |
1162 | movl %esp, %ebp | |
1163 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esp | |
1164 | call do_nmi | |
1165 | movl %ebp, %esp | |
1b00255f | 1166 | jmp .Lrestore_all_notrace |
d211af05 | 1167 | |
34273f41 | 1168 | #ifdef CONFIG_X86_ESPFIX32 |
1b00255f | 1169 | .Lnmi_espfix_stack: |
131484c8 | 1170 | /* |
d211af05 AH |
1171 | * create the pointer to lss back |
1172 | */ | |
a49976d1 IM |
1173 | pushl %ss |
1174 | pushl %esp | |
1175 | addl $4, (%esp) | |
d211af05 AH |
1176 | /* copy the iret frame of 12 bytes */ |
1177 | .rept 3 | |
a49976d1 | 1178 | pushl 16(%esp) |
d211af05 | 1179 | .endr |
a49976d1 | 1180 | pushl %eax |
d211af05 | 1181 | SAVE_ALL |
a49976d1 IM |
1182 | FIXUP_ESPFIX_STACK # %eax == %esp |
1183 | xorl %edx, %edx # zero error code | |
1184 | call do_nmi | |
d211af05 | 1185 | RESTORE_REGS |
a49976d1 | 1186 | lss 12+4(%esp), %esp # back to espfix stack |
1b00255f | 1187 | jmp .Lirq_return |
34273f41 | 1188 | #endif |
d211af05 AH |
1189 | END(nmi) |
1190 | ||
1191 | ENTRY(int3) | |
e59d1b0a | 1192 | ASM_CLAC |
a49976d1 | 1193 | pushl $-1 # mark this as an int |
d211af05 AH |
1194 | SAVE_ALL |
1195 | TRACE_IRQS_OFF | |
a49976d1 IM |
1196 | xorl %edx, %edx # zero error code |
1197 | movl %esp, %eax # pt_regs pointer | |
1198 | call do_int3 | |
1199 | jmp ret_from_exception | |
d211af05 AH |
1200 | END(int3) |
1201 | ||
1202 | ENTRY(general_protection) | |
a49976d1 | 1203 | pushl $do_general_protection |
7252c4c3 | 1204 | jmp common_exception |
d211af05 AH |
1205 | END(general_protection) |
1206 | ||
631bc487 GN |
1207 | #ifdef CONFIG_KVM_GUEST |
1208 | ENTRY(async_page_fault) | |
e59d1b0a | 1209 | ASM_CLAC |
a49976d1 | 1210 | pushl $do_async_page_fault |
7252c4c3 | 1211 | jmp common_exception |
2ae9d293 | 1212 | END(async_page_fault) |
631bc487 | 1213 | #endif |
2deb4be2 AL |
1214 | |
1215 | ENTRY(rewind_stack_do_exit) | |
1216 | /* Prevent any naive code from trying to unwind to our caller. */ | |
1217 | xorl %ebp, %ebp | |
1218 | ||
1219 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esi | |
1220 | leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp | |
1221 | ||
1222 | call do_exit | |
1223 | 1: jmp 1b | |
1224 | END(rewind_stack_do_exit) |