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Commit | Line | Data |
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1da177e4 | 1 | /* |
a49976d1 | 2 | * Copyright (C) 1991,1992 Linus Torvalds |
1da177e4 | 3 | * |
a49976d1 | 4 | * entry_32.S contains the system-call and low-level fault and trap handling routines. |
1da177e4 | 5 | * |
39e8701f | 6 | * Stack layout while running C code: |
a49976d1 IM |
7 | * ptrace needs to have all registers on the stack. |
8 | * If the order here is changed, it needs to be | |
9 | * updated in fork.c:copy_process(), signal.c:do_signal(), | |
1da177e4 LT |
10 | * ptrace.c and ptrace.h |
11 | * | |
12 | * 0(%esp) - %ebx | |
13 | * 4(%esp) - %ecx | |
14 | * 8(%esp) - %edx | |
9b47feb7 | 15 | * C(%esp) - %esi |
1da177e4 LT |
16 | * 10(%esp) - %edi |
17 | * 14(%esp) - %ebp | |
18 | * 18(%esp) - %eax | |
19 | * 1C(%esp) - %ds | |
20 | * 20(%esp) - %es | |
464d1a78 | 21 | * 24(%esp) - %fs |
ccbeed3a TH |
22 | * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS |
23 | * 2C(%esp) - orig_eax | |
24 | * 30(%esp) - %eip | |
25 | * 34(%esp) - %cs | |
26 | * 38(%esp) - %eflags | |
27 | * 3C(%esp) - %oldesp | |
28 | * 40(%esp) - %oldss | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 | 31 | #include <linux/linkage.h> |
d7e7528b | 32 | #include <linux/err.h> |
1da177e4 | 33 | #include <asm/thread_info.h> |
55f327fa | 34 | #include <asm/irqflags.h> |
1da177e4 LT |
35 | #include <asm/errno.h> |
36 | #include <asm/segment.h> | |
37 | #include <asm/smp.h> | |
be44d2aa | 38 | #include <asm/percpu.h> |
ab68ed98 | 39 | #include <asm/processor-flags.h> |
9b7dc567 | 40 | #include <asm/irq_vectors.h> |
cd4d09ec | 41 | #include <asm/cpufeatures.h> |
b4ca46e4 | 42 | #include <asm/alternative-asm.h> |
6837a54d | 43 | #include <asm/asm.h> |
e59d1b0a | 44 | #include <asm/smap.h> |
4d516f41 | 45 | #include <asm/frame.h> |
1da177e4 | 46 | |
ea714547 JO |
47 | .section .entry.text, "ax" |
48 | ||
139ec7c4 RR |
49 | /* |
50 | * We use macros for low-level operations which need to be overridden | |
51 | * for paravirtualization. The following will never clobber any registers: | |
52 | * INTERRUPT_RETURN (aka. "iret") | |
53 | * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax") | |
d75cd22f | 54 | * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit"). |
139ec7c4 RR |
55 | * |
56 | * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must | |
57 | * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY). | |
58 | * Allowing a register to be clobbered can shrink the paravirt replacement | |
59 | * enough to patch inline, increasing performance. | |
60 | */ | |
61 | ||
1da177e4 | 62 | #ifdef CONFIG_PREEMPT |
a49976d1 | 63 | # define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF |
1da177e4 | 64 | #else |
a49976d1 IM |
65 | # define preempt_stop(clobbers) |
66 | # define resume_kernel restore_all | |
1da177e4 LT |
67 | #endif |
68 | ||
55f327fa IM |
69 | .macro TRACE_IRQS_IRET |
70 | #ifdef CONFIG_TRACE_IRQFLAGS | |
a49976d1 IM |
71 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off? |
72 | jz 1f | |
55f327fa IM |
73 | TRACE_IRQS_ON |
74 | 1: | |
75 | #endif | |
76 | .endm | |
77 | ||
ccbeed3a TH |
78 | /* |
79 | * User gs save/restore | |
80 | * | |
81 | * %gs is used for userland TLS and kernel only uses it for stack | |
82 | * canary which is required to be at %gs:20 by gcc. Read the comment | |
83 | * at the top of stackprotector.h for more info. | |
84 | * | |
85 | * Local labels 98 and 99 are used. | |
86 | */ | |
87 | #ifdef CONFIG_X86_32_LAZY_GS | |
88 | ||
89 | /* unfortunately push/pop can't be no-op */ | |
90 | .macro PUSH_GS | |
a49976d1 | 91 | pushl $0 |
ccbeed3a TH |
92 | .endm |
93 | .macro POP_GS pop=0 | |
a49976d1 | 94 | addl $(4 + \pop), %esp |
ccbeed3a TH |
95 | .endm |
96 | .macro POP_GS_EX | |
97 | .endm | |
98 | ||
99 | /* all the rest are no-op */ | |
100 | .macro PTGS_TO_GS | |
101 | .endm | |
102 | .macro PTGS_TO_GS_EX | |
103 | .endm | |
104 | .macro GS_TO_REG reg | |
105 | .endm | |
106 | .macro REG_TO_PTGS reg | |
107 | .endm | |
108 | .macro SET_KERNEL_GS reg | |
109 | .endm | |
110 | ||
111 | #else /* CONFIG_X86_32_LAZY_GS */ | |
112 | ||
113 | .macro PUSH_GS | |
a49976d1 | 114 | pushl %gs |
ccbeed3a TH |
115 | .endm |
116 | ||
117 | .macro POP_GS pop=0 | |
a49976d1 | 118 | 98: popl %gs |
ccbeed3a | 119 | .if \pop <> 0 |
9b47feb7 | 120 | add $\pop, %esp |
ccbeed3a TH |
121 | .endif |
122 | .endm | |
123 | .macro POP_GS_EX | |
124 | .pushsection .fixup, "ax" | |
a49976d1 IM |
125 | 99: movl $0, (%esp) |
126 | jmp 98b | |
ccbeed3a | 127 | .popsection |
a49976d1 | 128 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
129 | .endm |
130 | ||
131 | .macro PTGS_TO_GS | |
a49976d1 | 132 | 98: mov PT_GS(%esp), %gs |
ccbeed3a TH |
133 | .endm |
134 | .macro PTGS_TO_GS_EX | |
135 | .pushsection .fixup, "ax" | |
a49976d1 IM |
136 | 99: movl $0, PT_GS(%esp) |
137 | jmp 98b | |
ccbeed3a | 138 | .popsection |
a49976d1 | 139 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
140 | .endm |
141 | ||
142 | .macro GS_TO_REG reg | |
a49976d1 | 143 | movl %gs, \reg |
ccbeed3a TH |
144 | .endm |
145 | .macro REG_TO_PTGS reg | |
a49976d1 | 146 | movl \reg, PT_GS(%esp) |
ccbeed3a TH |
147 | .endm |
148 | .macro SET_KERNEL_GS reg | |
a49976d1 IM |
149 | movl $(__KERNEL_STACK_CANARY), \reg |
150 | movl \reg, %gs | |
ccbeed3a TH |
151 | .endm |
152 | ||
a49976d1 | 153 | #endif /* CONFIG_X86_32_LAZY_GS */ |
ccbeed3a | 154 | |
150ac78d | 155 | .macro SAVE_ALL pt_regs_ax=%eax |
f0d96110 | 156 | cld |
ccbeed3a | 157 | PUSH_GS |
a49976d1 IM |
158 | pushl %fs |
159 | pushl %es | |
160 | pushl %ds | |
150ac78d | 161 | pushl \pt_regs_ax |
a49976d1 IM |
162 | pushl %ebp |
163 | pushl %edi | |
164 | pushl %esi | |
165 | pushl %edx | |
166 | pushl %ecx | |
167 | pushl %ebx | |
168 | movl $(__USER_DS), %edx | |
169 | movl %edx, %ds | |
170 | movl %edx, %es | |
171 | movl $(__KERNEL_PERCPU), %edx | |
172 | movl %edx, %fs | |
ccbeed3a | 173 | SET_KERNEL_GS %edx |
f0d96110 | 174 | .endm |
1da177e4 | 175 | |
946c1911 JP |
176 | /* |
177 | * This is a sneaky trick to help the unwinder find pt_regs on the stack. The | |
178 | * frame pointer is replaced with an encoded pointer to pt_regs. The encoding | |
179 | * is just setting the LSB, which makes it an invalid stack address and is also | |
180 | * a signal to the unwinder that it's a pt_regs pointer in disguise. | |
181 | * | |
182 | * NOTE: This macro must be used *after* SAVE_ALL because it corrupts the | |
183 | * original rbp. | |
184 | */ | |
185 | .macro ENCODE_FRAME_POINTER | |
186 | #ifdef CONFIG_FRAME_POINTER | |
187 | mov %esp, %ebp | |
188 | orl $0x1, %ebp | |
189 | #endif | |
190 | .endm | |
191 | ||
f0d96110 | 192 | .macro RESTORE_INT_REGS |
a49976d1 IM |
193 | popl %ebx |
194 | popl %ecx | |
195 | popl %edx | |
196 | popl %esi | |
197 | popl %edi | |
198 | popl %ebp | |
199 | popl %eax | |
f0d96110 | 200 | .endm |
1da177e4 | 201 | |
ccbeed3a | 202 | .macro RESTORE_REGS pop=0 |
f0d96110 | 203 | RESTORE_INT_REGS |
a49976d1 IM |
204 | 1: popl %ds |
205 | 2: popl %es | |
206 | 3: popl %fs | |
ccbeed3a | 207 | POP_GS \pop |
f0d96110 | 208 | .pushsection .fixup, "ax" |
a49976d1 IM |
209 | 4: movl $0, (%esp) |
210 | jmp 1b | |
211 | 5: movl $0, (%esp) | |
212 | jmp 2b | |
213 | 6: movl $0, (%esp) | |
214 | jmp 3b | |
f95d47ca | 215 | .popsection |
a49976d1 IM |
216 | _ASM_EXTABLE(1b, 4b) |
217 | _ASM_EXTABLE(2b, 5b) | |
218 | _ASM_EXTABLE(3b, 6b) | |
ccbeed3a | 219 | POP_GS_EX |
f0d96110 | 220 | .endm |
1da177e4 | 221 | |
0100301b BG |
222 | /* |
223 | * %eax: prev task | |
224 | * %edx: next task | |
225 | */ | |
226 | ENTRY(__switch_to_asm) | |
227 | /* | |
228 | * Save callee-saved registers | |
229 | * This must match the order in struct inactive_task_frame | |
230 | */ | |
231 | pushl %ebp | |
232 | pushl %ebx | |
233 | pushl %edi | |
234 | pushl %esi | |
235 | ||
236 | /* switch stack */ | |
237 | movl %esp, TASK_threadsp(%eax) | |
238 | movl TASK_threadsp(%edx), %esp | |
239 | ||
240 | #ifdef CONFIG_CC_STACKPROTECTOR | |
241 | movl TASK_stack_canary(%edx), %ebx | |
242 | movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset | |
243 | #endif | |
244 | ||
245 | /* restore callee-saved registers */ | |
246 | popl %esi | |
247 | popl %edi | |
248 | popl %ebx | |
249 | popl %ebp | |
250 | ||
251 | jmp __switch_to | |
252 | END(__switch_to_asm) | |
253 | ||
254 | /* | |
255 | * A newly forked process directly context switches into this address. | |
256 | * | |
257 | * eax: prev task we switched from | |
616d2483 BG |
258 | * ebx: kernel thread func (NULL for user thread) |
259 | * edi: kernel thread arg | |
0100301b | 260 | */ |
1da177e4 | 261 | ENTRY(ret_from_fork) |
ff3f7e24 JP |
262 | FRAME_BEGIN /* help unwinder find end of stack */ |
263 | ||
264 | /* | |
265 | * schedule_tail() is asmlinkage so we have to put its 'prev' argument | |
266 | * on the stack. | |
267 | */ | |
268 | pushl %eax | |
269 | call schedule_tail | |
270 | popl %eax | |
39e8701f | 271 | |
616d2483 BG |
272 | testl %ebx, %ebx |
273 | jnz 1f /* kernel threads are uncommon */ | |
274 | ||
275 | 2: | |
39e8701f | 276 | /* When we fork, we trace the syscall return in the child, too. */ |
ff3f7e24 | 277 | leal FRAME_OFFSET(%esp), %eax |
39e8701f | 278 | call syscall_return_slowpath |
ff3f7e24 | 279 | FRAME_END |
39e8701f | 280 | jmp restore_all |
39e8701f | 281 | |
616d2483 BG |
282 | /* kernel thread */ |
283 | 1: movl %edi, %eax | |
284 | call *%ebx | |
39e8701f | 285 | /* |
616d2483 BG |
286 | * A kernel thread is allowed to return here after successfully |
287 | * calling do_execve(). Exit to userspace to complete the execve() | |
288 | * syscall. | |
39e8701f | 289 | */ |
616d2483 BG |
290 | movl $0, PT_EAX(%esp) |
291 | jmp 2b | |
292 | END(ret_from_fork) | |
6783eaa2 | 293 | |
1da177e4 LT |
294 | /* |
295 | * Return to user mode is not as complex as all this looks, | |
296 | * but we want the default path for a system call return to | |
297 | * go as quickly as possible which is why some of this is | |
298 | * less clear than it otherwise should be. | |
299 | */ | |
300 | ||
301 | # userspace resumption stub bypassing syscall exit tracing | |
302 | ALIGN | |
303 | ret_from_exception: | |
139ec7c4 | 304 | preempt_stop(CLBR_ANY) |
1da177e4 | 305 | ret_from_intr: |
29a2e283 | 306 | #ifdef CONFIG_VM86 |
a49976d1 IM |
307 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS |
308 | movb PT_CS(%esp), %al | |
309 | andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax | |
29a2e283 DA |
310 | #else |
311 | /* | |
6783eaa2 | 312 | * We can be coming here from child spawned by kernel_thread(). |
29a2e283 | 313 | */ |
a49976d1 IM |
314 | movl PT_CS(%esp), %eax |
315 | andl $SEGMENT_RPL_MASK, %eax | |
29a2e283 | 316 | #endif |
a49976d1 IM |
317 | cmpl $USER_RPL, %eax |
318 | jb resume_kernel # not returning to v8086 or userspace | |
f95d47ca | 319 | |
1da177e4 | 320 | ENTRY(resume_userspace) |
5d73fc70 | 321 | DISABLE_INTERRUPTS(CLBR_ANY) |
e32e58a9 | 322 | TRACE_IRQS_OFF |
5d73fc70 AL |
323 | movl %esp, %eax |
324 | call prepare_exit_to_usermode | |
a49976d1 | 325 | jmp restore_all |
47a55cd7 | 326 | END(ret_from_exception) |
1da177e4 LT |
327 | |
328 | #ifdef CONFIG_PREEMPT | |
329 | ENTRY(resume_kernel) | |
139ec7c4 | 330 | DISABLE_INTERRUPTS(CLBR_ANY) |
1b00255f | 331 | .Lneed_resched: |
a49976d1 IM |
332 | cmpl $0, PER_CPU_VAR(__preempt_count) |
333 | jnz restore_all | |
334 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ? | |
335 | jz restore_all | |
336 | call preempt_schedule_irq | |
1b00255f | 337 | jmp .Lneed_resched |
47a55cd7 | 338 | END(resume_kernel) |
1da177e4 LT |
339 | #endif |
340 | ||
f2b37575 AL |
341 | GLOBAL(__begin_SYSENTER_singlestep_region) |
342 | /* | |
343 | * All code from here through __end_SYSENTER_singlestep_region is subject | |
344 | * to being single-stepped if a user program sets TF and executes SYSENTER. | |
345 | * There is absolutely nothing that we can do to prevent this from happening | |
346 | * (thanks Intel!). To keep our handling of this situation as simple as | |
347 | * possible, we handle TF just like AC and NT, except that our #DB handler | |
348 | * will ignore all of the single-step traps generated in this range. | |
349 | */ | |
350 | ||
351 | #ifdef CONFIG_XEN | |
352 | /* | |
353 | * Xen doesn't set %esp to be precisely what the normal SYSENTER | |
354 | * entry point expects, so fix it up before using the normal path. | |
355 | */ | |
356 | ENTRY(xen_sysenter_target) | |
357 | addl $5*4, %esp /* remove xen-provided frame */ | |
1b00255f | 358 | jmp .Lsysenter_past_esp |
f2b37575 AL |
359 | #endif |
360 | ||
fda57b22 AL |
361 | /* |
362 | * 32-bit SYSENTER entry. | |
363 | * | |
364 | * 32-bit system calls through the vDSO's __kernel_vsyscall enter here | |
365 | * if X86_FEATURE_SEP is available. This is the preferred system call | |
366 | * entry on 32-bit systems. | |
367 | * | |
368 | * The SYSENTER instruction, in principle, should *only* occur in the | |
369 | * vDSO. In practice, a small number of Android devices were shipped | |
370 | * with a copy of Bionic that inlined a SYSENTER instruction. This | |
371 | * never happened in any of Google's Bionic versions -- it only happened | |
372 | * in a narrow range of Intel-provided versions. | |
373 | * | |
374 | * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs. | |
375 | * IF and VM in RFLAGS are cleared (IOW: interrupts are off). | |
376 | * SYSENTER does not save anything on the stack, | |
377 | * and does not save old EIP (!!!), ESP, or EFLAGS. | |
378 | * | |
379 | * To avoid losing track of EFLAGS.VM (and thus potentially corrupting | |
380 | * user and/or vm86 state), we explicitly disable the SYSENTER | |
381 | * instruction in vm86 mode by reprogramming the MSRs. | |
382 | * | |
383 | * Arguments: | |
384 | * eax system call number | |
385 | * ebx arg1 | |
386 | * ecx arg2 | |
387 | * edx arg3 | |
388 | * esi arg4 | |
389 | * edi arg5 | |
390 | * ebp user stack | |
391 | * 0(%ebp) arg6 | |
392 | */ | |
4c8cd0c5 | 393 | ENTRY(entry_SYSENTER_32) |
a49976d1 | 394 | movl TSS_sysenter_sp0(%esp), %esp |
1b00255f | 395 | .Lsysenter_past_esp: |
5f310f73 | 396 | pushl $__USER_DS /* pt_regs->ss */ |
30bfa7b3 | 397 | pushl %ebp /* pt_regs->sp (stashed in bp) */ |
5f310f73 AL |
398 | pushfl /* pt_regs->flags (except IF = 0) */ |
399 | orl $X86_EFLAGS_IF, (%esp) /* Fix IF */ | |
400 | pushl $__USER_CS /* pt_regs->cs */ | |
401 | pushl $0 /* pt_regs->ip = 0 (placeholder) */ | |
402 | pushl %eax /* pt_regs->orig_ax */ | |
403 | SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest */ | |
404 | ||
67f590e8 | 405 | /* |
f2b37575 AL |
406 | * SYSENTER doesn't filter flags, so we need to clear NT, AC |
407 | * and TF ourselves. To save a few cycles, we can check whether | |
67f590e8 AL |
408 | * either was set instead of doing an unconditional popfq. |
409 | * This needs to happen before enabling interrupts so that | |
410 | * we don't get preempted with NT set. | |
411 | * | |
f2b37575 AL |
412 | * If TF is set, we will single-step all the way to here -- do_debug |
413 | * will ignore all the traps. (Yes, this is slow, but so is | |
414 | * single-stepping in general. This allows us to avoid having | |
415 | * a more complicated code to handle the case where a user program | |
416 | * forces us to single-step through the SYSENTER entry code.) | |
417 | * | |
67f590e8 AL |
418 | * NB.: .Lsysenter_fix_flags is a label with the code under it moved |
419 | * out-of-line as an optimization: NT is unlikely to be set in the | |
420 | * majority of the cases and instead of polluting the I$ unnecessarily, | |
421 | * we're keeping that code behind a branch which will predict as | |
422 | * not-taken and therefore its instructions won't be fetched. | |
423 | */ | |
f2b37575 | 424 | testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp) |
67f590e8 AL |
425 | jnz .Lsysenter_fix_flags |
426 | .Lsysenter_flags_fixed: | |
427 | ||
55f327fa | 428 | /* |
5f310f73 AL |
429 | * User mode is traced as though IRQs are on, and SYSENTER |
430 | * turned them off. | |
e6e5494c | 431 | */ |
55f327fa | 432 | TRACE_IRQS_OFF |
5f310f73 AL |
433 | |
434 | movl %esp, %eax | |
435 | call do_fast_syscall_32 | |
91e2eea9 BO |
436 | /* XEN PV guests always use IRET path */ |
437 | ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \ | |
438 | "jmp .Lsyscall_32_done", X86_FEATURE_XENPV | |
5f310f73 AL |
439 | |
440 | /* Opportunistic SYSEXIT */ | |
441 | TRACE_IRQS_ON /* User mode traces as IRQs on. */ | |
442 | movl PT_EIP(%esp), %edx /* pt_regs->ip */ | |
443 | movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */ | |
3bd29515 AL |
444 | 1: mov PT_FS(%esp), %fs |
445 | PTGS_TO_GS | |
5f310f73 AL |
446 | popl %ebx /* pt_regs->bx */ |
447 | addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */ | |
448 | popl %esi /* pt_regs->si */ | |
449 | popl %edi /* pt_regs->di */ | |
450 | popl %ebp /* pt_regs->bp */ | |
451 | popl %eax /* pt_regs->ax */ | |
5f310f73 | 452 | |
c2c9b52f AL |
453 | /* |
454 | * Restore all flags except IF. (We restore IF separately because | |
455 | * STI gives a one-instruction window in which we won't be interrupted, | |
456 | * whereas POPF does not.) | |
457 | */ | |
458 | addl $PT_EFLAGS-PT_DS, %esp /* point esp at pt_regs->flags */ | |
459 | btr $X86_EFLAGS_IF_BIT, (%esp) | |
460 | popfl | |
461 | ||
5f310f73 AL |
462 | /* |
463 | * Return back to the vDSO, which will pop ecx and edx. | |
464 | * Don't bother with DS and ES (they already contain __USER_DS). | |
465 | */ | |
88c15ec9 BO |
466 | sti |
467 | sysexit | |
af0575bb | 468 | |
a49976d1 IM |
469 | .pushsection .fixup, "ax" |
470 | 2: movl $0, PT_FS(%esp) | |
471 | jmp 1b | |
f95d47ca | 472 | .popsection |
a49976d1 | 473 | _ASM_EXTABLE(1b, 2b) |
ccbeed3a | 474 | PTGS_TO_GS_EX |
67f590e8 AL |
475 | |
476 | .Lsysenter_fix_flags: | |
477 | pushl $X86_EFLAGS_FIXED | |
478 | popfl | |
479 | jmp .Lsysenter_flags_fixed | |
f2b37575 | 480 | GLOBAL(__end_SYSENTER_singlestep_region) |
4c8cd0c5 | 481 | ENDPROC(entry_SYSENTER_32) |
1da177e4 | 482 | |
fda57b22 AL |
483 | /* |
484 | * 32-bit legacy system call entry. | |
485 | * | |
486 | * 32-bit x86 Linux system calls traditionally used the INT $0x80 | |
487 | * instruction. INT $0x80 lands here. | |
488 | * | |
489 | * This entry point can be used by any 32-bit perform system calls. | |
490 | * Instances of INT $0x80 can be found inline in various programs and | |
491 | * libraries. It is also used by the vDSO's __kernel_vsyscall | |
492 | * fallback for hardware that doesn't support a faster entry method. | |
493 | * Restarted 32-bit system calls also fall back to INT $0x80 | |
494 | * regardless of what instruction was originally used to do the system | |
495 | * call. (64-bit programs can use INT $0x80 as well, but they can | |
496 | * only run on 64-bit kernels and therefore land in | |
497 | * entry_INT80_compat.) | |
498 | * | |
499 | * This is considered a slow path. It is not used by most libc | |
500 | * implementations on modern hardware except during process startup. | |
501 | * | |
502 | * Arguments: | |
503 | * eax system call number | |
504 | * ebx arg1 | |
505 | * ecx arg2 | |
506 | * edx arg3 | |
507 | * esi arg4 | |
508 | * edi arg5 | |
509 | * ebp arg6 | |
510 | */ | |
b2502b41 | 511 | ENTRY(entry_INT80_32) |
e59d1b0a | 512 | ASM_CLAC |
150ac78d | 513 | pushl %eax /* pt_regs->orig_ax */ |
5f310f73 | 514 | SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest */ |
150ac78d AL |
515 | |
516 | /* | |
a798f091 AL |
517 | * User mode is traced as though IRQs are on, and the interrupt gate |
518 | * turned them off. | |
150ac78d | 519 | */ |
a798f091 | 520 | TRACE_IRQS_OFF |
150ac78d AL |
521 | |
522 | movl %esp, %eax | |
a798f091 | 523 | call do_int80_syscall_32 |
5f310f73 | 524 | .Lsyscall_32_done: |
1da177e4 LT |
525 | |
526 | restore_all: | |
2e04bc76 | 527 | TRACE_IRQS_IRET |
1b00255f | 528 | .Lrestore_all_notrace: |
34273f41 | 529 | #ifdef CONFIG_X86_ESPFIX32 |
1b00255f | 530 | ALTERNATIVE "jmp .Lrestore_nocheck", "", X86_BUG_ESPFIX |
58a5aac5 | 531 | |
a49976d1 IM |
532 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS |
533 | /* | |
534 | * Warning: PT_OLDSS(%esp) contains the wrong/random values if we | |
535 | * are returning to the kernel. | |
536 | * See comments in process.c:copy_thread() for details. | |
537 | */ | |
538 | movb PT_OLDSS(%esp), %ah | |
539 | movb PT_CS(%esp), %al | |
540 | andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax | |
541 | cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax | |
1b00255f | 542 | je .Lldt_ss # returning to user-space with LDT SS |
34273f41 | 543 | #endif |
1b00255f | 544 | .Lrestore_nocheck: |
a49976d1 | 545 | RESTORE_REGS 4 # skip orig_eax/error_code |
1b00255f | 546 | .Lirq_return: |
3701d863 | 547 | INTERRUPT_RETURN |
1b00255f | 548 | |
a49976d1 IM |
549 | .section .fixup, "ax" |
550 | ENTRY(iret_exc ) | |
551 | pushl $0 # no error code | |
552 | pushl $do_iret_error | |
7252c4c3 | 553 | jmp common_exception |
1da177e4 | 554 | .previous |
1b00255f | 555 | _ASM_EXTABLE(.Lirq_return, iret_exc) |
1da177e4 | 556 | |
34273f41 | 557 | #ifdef CONFIG_X86_ESPFIX32 |
1b00255f | 558 | .Lldt_ss: |
dc4c2a0a AH |
559 | /* |
560 | * Setup and switch to ESPFIX stack | |
561 | * | |
562 | * We're returning to userspace with a 16 bit stack. The CPU will not | |
563 | * restore the high word of ESP for us on executing iret... This is an | |
564 | * "official" bug of all the x86-compatible CPUs, which we can work | |
565 | * around to make dosemu and wine happy. We do this by preloading the | |
566 | * high word of ESP with the high word of the userspace ESP while | |
567 | * compensating for the offset by changing to the ESPFIX segment with | |
568 | * a base address that matches for the difference. | |
569 | */ | |
72c511dd | 570 | #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8) |
a49976d1 IM |
571 | mov %esp, %edx /* load kernel esp */ |
572 | mov PT_OLDESP(%esp), %eax /* load userspace esp */ | |
573 | mov %dx, %ax /* eax: new kernel esp */ | |
9b47feb7 DV |
574 | sub %eax, %edx /* offset (low word is 0) */ |
575 | shr $16, %edx | |
a49976d1 IM |
576 | mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */ |
577 | mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */ | |
578 | pushl $__ESPFIX_SS | |
579 | pushl %eax /* new kernel esp */ | |
580 | /* | |
581 | * Disable interrupts, but do not irqtrace this section: we | |
2e04bc76 | 582 | * will soon execute iret and the tracer was already set to |
a49976d1 IM |
583 | * the irqstate after the IRET: |
584 | */ | |
fdbd518a | 585 | DISABLE_INTERRUPTS(CLBR_ANY) |
a49976d1 | 586 | lss (%esp), %esp /* switch to espfix segment */ |
1b00255f | 587 | jmp .Lrestore_nocheck |
34273f41 | 588 | #endif |
b2502b41 | 589 | ENDPROC(entry_INT80_32) |
1da177e4 | 590 | |
f0d96110 | 591 | .macro FIXUP_ESPFIX_STACK |
dc4c2a0a AH |
592 | /* |
593 | * Switch back for ESPFIX stack to the normal zerobased stack | |
594 | * | |
595 | * We can't call C functions using the ESPFIX stack. This code reads | |
596 | * the high word of the segment base from the GDT and swiches to the | |
597 | * normal stack and adjusts ESP with the matching offset. | |
598 | */ | |
34273f41 | 599 | #ifdef CONFIG_X86_ESPFIX32 |
dc4c2a0a | 600 | /* fixup the stack */ |
a49976d1 IM |
601 | mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */ |
602 | mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */ | |
9b47feb7 | 603 | shl $16, %eax |
a49976d1 IM |
604 | addl %esp, %eax /* the adjusted stack pointer */ |
605 | pushl $__KERNEL_DS | |
606 | pushl %eax | |
607 | lss (%esp), %esp /* switch to the normal stack segment */ | |
34273f41 | 608 | #endif |
f0d96110 TH |
609 | .endm |
610 | .macro UNWIND_ESPFIX_STACK | |
34273f41 | 611 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 | 612 | movl %ss, %eax |
f0d96110 | 613 | /* see if on espfix stack */ |
a49976d1 IM |
614 | cmpw $__ESPFIX_SS, %ax |
615 | jne 27f | |
616 | movl $__KERNEL_DS, %eax | |
617 | movl %eax, %ds | |
618 | movl %eax, %es | |
f0d96110 TH |
619 | /* switch to normal stack */ |
620 | FIXUP_ESPFIX_STACK | |
621 | 27: | |
34273f41 | 622 | #endif |
f0d96110 | 623 | .endm |
1da177e4 LT |
624 | |
625 | /* | |
3304c9c3 DV |
626 | * Build the entry stubs with some assembler magic. |
627 | * We pack 1 stub into every 8-byte block. | |
1da177e4 | 628 | */ |
3304c9c3 | 629 | .align 8 |
1da177e4 | 630 | ENTRY(irq_entries_start) |
3304c9c3 DV |
631 | vector=FIRST_EXTERNAL_VECTOR |
632 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
a49976d1 | 633 | pushl $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
634 | vector=vector+1 |
635 | jmp common_interrupt | |
3304c9c3 DV |
636 | .align 8 |
637 | .endr | |
47a55cd7 JB |
638 | END(irq_entries_start) |
639 | ||
55f327fa IM |
640 | /* |
641 | * the CPU automatically disables interrupts when executing an IRQ vector, | |
642 | * so IRQ-flags tracing has to follow that: | |
643 | */ | |
b7c6244f | 644 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
1da177e4 | 645 | common_interrupt: |
e59d1b0a | 646 | ASM_CLAC |
a49976d1 | 647 | addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */ |
1da177e4 | 648 | SAVE_ALL |
946c1911 | 649 | ENCODE_FRAME_POINTER |
55f327fa | 650 | TRACE_IRQS_OFF |
a49976d1 IM |
651 | movl %esp, %eax |
652 | call do_IRQ | |
653 | jmp ret_from_intr | |
47a55cd7 | 654 | ENDPROC(common_interrupt) |
1da177e4 | 655 | |
02cf94c3 | 656 | #define BUILD_INTERRUPT3(name, nr, fn) \ |
1da177e4 | 657 | ENTRY(name) \ |
e59d1b0a | 658 | ASM_CLAC; \ |
a49976d1 | 659 | pushl $~(nr); \ |
fe7cacc1 | 660 | SAVE_ALL; \ |
946c1911 | 661 | ENCODE_FRAME_POINTER; \ |
55f327fa | 662 | TRACE_IRQS_OFF \ |
a49976d1 IM |
663 | movl %esp, %eax; \ |
664 | call fn; \ | |
665 | jmp ret_from_intr; \ | |
47a55cd7 | 666 | ENDPROC(name) |
1da177e4 | 667 | |
cf910e83 SA |
668 | |
669 | #ifdef CONFIG_TRACING | |
a49976d1 | 670 | # define TRACE_BUILD_INTERRUPT(name, nr) BUILD_INTERRUPT3(trace_##name, nr, smp_trace_##name) |
cf910e83 | 671 | #else |
a49976d1 | 672 | # define TRACE_BUILD_INTERRUPT(name, nr) |
cf910e83 SA |
673 | #endif |
674 | ||
a49976d1 IM |
675 | #define BUILD_INTERRUPT(name, nr) \ |
676 | BUILD_INTERRUPT3(name, nr, smp_##name); \ | |
cf910e83 | 677 | TRACE_BUILD_INTERRUPT(name, nr) |
02cf94c3 | 678 | |
1da177e4 | 679 | /* The include is where all of the SMP etc. interrupts come from */ |
1164dd00 | 680 | #include <asm/entry_arch.h> |
1da177e4 | 681 | |
1da177e4 | 682 | ENTRY(coprocessor_error) |
e59d1b0a | 683 | ASM_CLAC |
a49976d1 IM |
684 | pushl $0 |
685 | pushl $do_coprocessor_error | |
7252c4c3 | 686 | jmp common_exception |
47a55cd7 | 687 | END(coprocessor_error) |
1da177e4 LT |
688 | |
689 | ENTRY(simd_coprocessor_error) | |
e59d1b0a | 690 | ASM_CLAC |
a49976d1 | 691 | pushl $0 |
40d2e763 BG |
692 | #ifdef CONFIG_X86_INVD_BUG |
693 | /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */ | |
a49976d1 IM |
694 | ALTERNATIVE "pushl $do_general_protection", \ |
695 | "pushl $do_simd_coprocessor_error", \ | |
8e65f6e0 | 696 | X86_FEATURE_XMM |
40d2e763 | 697 | #else |
a49976d1 | 698 | pushl $do_simd_coprocessor_error |
40d2e763 | 699 | #endif |
7252c4c3 | 700 | jmp common_exception |
47a55cd7 | 701 | END(simd_coprocessor_error) |
1da177e4 LT |
702 | |
703 | ENTRY(device_not_available) | |
e59d1b0a | 704 | ASM_CLAC |
a49976d1 IM |
705 | pushl $-1 # mark this as an int |
706 | pushl $do_device_not_available | |
7252c4c3 | 707 | jmp common_exception |
47a55cd7 | 708 | END(device_not_available) |
1da177e4 | 709 | |
d3561b7f RR |
710 | #ifdef CONFIG_PARAVIRT |
711 | ENTRY(native_iret) | |
3701d863 | 712 | iret |
6837a54d | 713 | _ASM_EXTABLE(native_iret, iret_exc) |
47a55cd7 | 714 | END(native_iret) |
d3561b7f RR |
715 | #endif |
716 | ||
1da177e4 | 717 | ENTRY(overflow) |
e59d1b0a | 718 | ASM_CLAC |
a49976d1 IM |
719 | pushl $0 |
720 | pushl $do_overflow | |
7252c4c3 | 721 | jmp common_exception |
47a55cd7 | 722 | END(overflow) |
1da177e4 LT |
723 | |
724 | ENTRY(bounds) | |
e59d1b0a | 725 | ASM_CLAC |
a49976d1 IM |
726 | pushl $0 |
727 | pushl $do_bounds | |
7252c4c3 | 728 | jmp common_exception |
47a55cd7 | 729 | END(bounds) |
1da177e4 LT |
730 | |
731 | ENTRY(invalid_op) | |
e59d1b0a | 732 | ASM_CLAC |
a49976d1 IM |
733 | pushl $0 |
734 | pushl $do_invalid_op | |
7252c4c3 | 735 | jmp common_exception |
47a55cd7 | 736 | END(invalid_op) |
1da177e4 LT |
737 | |
738 | ENTRY(coprocessor_segment_overrun) | |
e59d1b0a | 739 | ASM_CLAC |
a49976d1 IM |
740 | pushl $0 |
741 | pushl $do_coprocessor_segment_overrun | |
7252c4c3 | 742 | jmp common_exception |
47a55cd7 | 743 | END(coprocessor_segment_overrun) |
1da177e4 LT |
744 | |
745 | ENTRY(invalid_TSS) | |
e59d1b0a | 746 | ASM_CLAC |
a49976d1 | 747 | pushl $do_invalid_TSS |
7252c4c3 | 748 | jmp common_exception |
47a55cd7 | 749 | END(invalid_TSS) |
1da177e4 LT |
750 | |
751 | ENTRY(segment_not_present) | |
e59d1b0a | 752 | ASM_CLAC |
a49976d1 | 753 | pushl $do_segment_not_present |
7252c4c3 | 754 | jmp common_exception |
47a55cd7 | 755 | END(segment_not_present) |
1da177e4 LT |
756 | |
757 | ENTRY(stack_segment) | |
e59d1b0a | 758 | ASM_CLAC |
a49976d1 | 759 | pushl $do_stack_segment |
7252c4c3 | 760 | jmp common_exception |
47a55cd7 | 761 | END(stack_segment) |
1da177e4 | 762 | |
1da177e4 | 763 | ENTRY(alignment_check) |
e59d1b0a | 764 | ASM_CLAC |
a49976d1 | 765 | pushl $do_alignment_check |
7252c4c3 | 766 | jmp common_exception |
47a55cd7 | 767 | END(alignment_check) |
1da177e4 | 768 | |
d28c4393 | 769 | ENTRY(divide_error) |
e59d1b0a | 770 | ASM_CLAC |
a49976d1 IM |
771 | pushl $0 # no error code |
772 | pushl $do_divide_error | |
7252c4c3 | 773 | jmp common_exception |
47a55cd7 | 774 | END(divide_error) |
1da177e4 LT |
775 | |
776 | #ifdef CONFIG_X86_MCE | |
777 | ENTRY(machine_check) | |
e59d1b0a | 778 | ASM_CLAC |
a49976d1 IM |
779 | pushl $0 |
780 | pushl machine_check_vector | |
7252c4c3 | 781 | jmp common_exception |
47a55cd7 | 782 | END(machine_check) |
1da177e4 LT |
783 | #endif |
784 | ||
785 | ENTRY(spurious_interrupt_bug) | |
e59d1b0a | 786 | ASM_CLAC |
a49976d1 IM |
787 | pushl $0 |
788 | pushl $do_spurious_interrupt_bug | |
7252c4c3 | 789 | jmp common_exception |
47a55cd7 | 790 | END(spurious_interrupt_bug) |
1da177e4 | 791 | |
5ead97c8 JF |
792 | #ifdef CONFIG_XEN |
793 | ENTRY(xen_hypervisor_callback) | |
a49976d1 | 794 | pushl $-1 /* orig_ax = -1 => not a system call */ |
5ead97c8 | 795 | SAVE_ALL |
946c1911 | 796 | ENCODE_FRAME_POINTER |
5ead97c8 | 797 | TRACE_IRQS_OFF |
9ec2b804 | 798 | |
a49976d1 IM |
799 | /* |
800 | * Check to see if we got the event in the critical | |
801 | * region in xen_iret_direct, after we've reenabled | |
802 | * events and checked for pending events. This simulates | |
803 | * iret instruction's behaviour where it delivers a | |
804 | * pending interrupt when enabling interrupts: | |
805 | */ | |
806 | movl PT_EIP(%esp), %eax | |
807 | cmpl $xen_iret_start_crit, %eax | |
808 | jb 1f | |
809 | cmpl $xen_iret_end_crit, %eax | |
810 | jae 1f | |
9ec2b804 | 811 | |
a49976d1 | 812 | jmp xen_iret_crit_fixup |
e2a81baf | 813 | |
e2a81baf | 814 | ENTRY(xen_do_upcall) |
a49976d1 IM |
815 | 1: mov %esp, %eax |
816 | call xen_evtchn_do_upcall | |
fdfd811d | 817 | #ifndef CONFIG_PREEMPT |
a49976d1 | 818 | call xen_maybe_preempt_hcall |
fdfd811d | 819 | #endif |
a49976d1 | 820 | jmp ret_from_intr |
5ead97c8 JF |
821 | ENDPROC(xen_hypervisor_callback) |
822 | ||
a49976d1 IM |
823 | /* |
824 | * Hypervisor uses this for application faults while it executes. | |
825 | * We get here for two reasons: | |
826 | * 1. Fault while reloading DS, ES, FS or GS | |
827 | * 2. Fault while executing IRET | |
828 | * Category 1 we fix up by reattempting the load, and zeroing the segment | |
829 | * register if the load fails. | |
830 | * Category 2 we fix up by jumping to do_iret_error. We cannot use the | |
831 | * normal Linux return path in this case because if we use the IRET hypercall | |
832 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
833 | * We distinguish between categories by maintaining a status value in EAX. | |
834 | */ | |
5ead97c8 | 835 | ENTRY(xen_failsafe_callback) |
a49976d1 IM |
836 | pushl %eax |
837 | movl $1, %eax | |
838 | 1: mov 4(%esp), %ds | |
839 | 2: mov 8(%esp), %es | |
840 | 3: mov 12(%esp), %fs | |
841 | 4: mov 16(%esp), %gs | |
a349e23d DV |
842 | /* EAX == 0 => Category 1 (Bad segment) |
843 | EAX != 0 => Category 2 (Bad IRET) */ | |
a49976d1 IM |
844 | testl %eax, %eax |
845 | popl %eax | |
846 | lea 16(%esp), %esp | |
847 | jz 5f | |
848 | jmp iret_exc | |
849 | 5: pushl $-1 /* orig_ax = -1 => not a system call */ | |
5ead97c8 | 850 | SAVE_ALL |
946c1911 | 851 | ENCODE_FRAME_POINTER |
a49976d1 IM |
852 | jmp ret_from_exception |
853 | ||
854 | .section .fixup, "ax" | |
855 | 6: xorl %eax, %eax | |
856 | movl %eax, 4(%esp) | |
857 | jmp 1b | |
858 | 7: xorl %eax, %eax | |
859 | movl %eax, 8(%esp) | |
860 | jmp 2b | |
861 | 8: xorl %eax, %eax | |
862 | movl %eax, 12(%esp) | |
863 | jmp 3b | |
864 | 9: xorl %eax, %eax | |
865 | movl %eax, 16(%esp) | |
866 | jmp 4b | |
5ead97c8 | 867 | .previous |
a49976d1 IM |
868 | _ASM_EXTABLE(1b, 6b) |
869 | _ASM_EXTABLE(2b, 7b) | |
870 | _ASM_EXTABLE(3b, 8b) | |
871 | _ASM_EXTABLE(4b, 9b) | |
5ead97c8 JF |
872 | ENDPROC(xen_failsafe_callback) |
873 | ||
bc2b0331 | 874 | BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR, |
38e20b07 SY |
875 | xen_evtchn_do_upcall) |
876 | ||
a49976d1 | 877 | #endif /* CONFIG_XEN */ |
bc2b0331 S |
878 | |
879 | #if IS_ENABLED(CONFIG_HYPERV) | |
880 | ||
881 | BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR, | |
882 | hyperv_vector_handler) | |
883 | ||
884 | #endif /* CONFIG_HYPERV */ | |
5ead97c8 | 885 | |
25c74b10 SA |
886 | #ifdef CONFIG_TRACING |
887 | ENTRY(trace_page_fault) | |
25c74b10 | 888 | ASM_CLAC |
a49976d1 | 889 | pushl $trace_do_page_fault |
7252c4c3 | 890 | jmp common_exception |
25c74b10 SA |
891 | END(trace_page_fault) |
892 | #endif | |
893 | ||
d211af05 | 894 | ENTRY(page_fault) |
e59d1b0a | 895 | ASM_CLAC |
a49976d1 | 896 | pushl $do_page_fault |
d211af05 | 897 | ALIGN |
7252c4c3 JP |
898 | jmp common_exception |
899 | END(page_fault) | |
900 | ||
901 | common_exception: | |
ccbeed3a | 902 | /* the function address is in %gs's slot on the stack */ |
a49976d1 IM |
903 | pushl %fs |
904 | pushl %es | |
905 | pushl %ds | |
906 | pushl %eax | |
907 | pushl %ebp | |
908 | pushl %edi | |
909 | pushl %esi | |
910 | pushl %edx | |
911 | pushl %ecx | |
912 | pushl %ebx | |
946c1911 | 913 | ENCODE_FRAME_POINTER |
d211af05 | 914 | cld |
a49976d1 IM |
915 | movl $(__KERNEL_PERCPU), %ecx |
916 | movl %ecx, %fs | |
d211af05 | 917 | UNWIND_ESPFIX_STACK |
ccbeed3a | 918 | GS_TO_REG %ecx |
a49976d1 IM |
919 | movl PT_GS(%esp), %edi # get the function address |
920 | movl PT_ORIG_EAX(%esp), %edx # get the error code | |
921 | movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart | |
ccbeed3a TH |
922 | REG_TO_PTGS %ecx |
923 | SET_KERNEL_GS %ecx | |
a49976d1 IM |
924 | movl $(__USER_DS), %ecx |
925 | movl %ecx, %ds | |
926 | movl %ecx, %es | |
d211af05 | 927 | TRACE_IRQS_OFF |
a49976d1 IM |
928 | movl %esp, %eax # pt_regs pointer |
929 | call *%edi | |
930 | jmp ret_from_exception | |
7252c4c3 | 931 | END(common_exception) |
d211af05 | 932 | |
d211af05 | 933 | ENTRY(debug) |
7536656f AL |
934 | /* |
935 | * #DB can happen at the first instruction of | |
936 | * entry_SYSENTER_32 or in Xen's SYSENTER prologue. If this | |
937 | * happens, then we will be running on a very small stack. We | |
938 | * need to detect this condition and switch to the thread | |
939 | * stack before calling any C code at all. | |
940 | * | |
941 | * If you edit this code, keep in mind that NMIs can happen in here. | |
942 | */ | |
e59d1b0a | 943 | ASM_CLAC |
a49976d1 | 944 | pushl $-1 # mark this as an int |
d211af05 | 945 | SAVE_ALL |
946c1911 | 946 | ENCODE_FRAME_POINTER |
a49976d1 IM |
947 | xorl %edx, %edx # error code 0 |
948 | movl %esp, %eax # pt_regs pointer | |
7536656f AL |
949 | |
950 | /* Are we currently on the SYSENTER stack? */ | |
951 | PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) | |
952 | subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ | |
953 | cmpl $SIZEOF_SYSENTER_stack, %ecx | |
954 | jb .Ldebug_from_sysenter_stack | |
955 | ||
956 | TRACE_IRQS_OFF | |
957 | call do_debug | |
958 | jmp ret_from_exception | |
959 | ||
960 | .Ldebug_from_sysenter_stack: | |
961 | /* We're on the SYSENTER stack. Switch off. */ | |
946c1911 | 962 | movl %esp, %ebx |
7536656f AL |
963 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esp |
964 | TRACE_IRQS_OFF | |
a49976d1 | 965 | call do_debug |
946c1911 | 966 | movl %ebx, %esp |
a49976d1 | 967 | jmp ret_from_exception |
d211af05 AH |
968 | END(debug) |
969 | ||
970 | /* | |
7536656f AL |
971 | * NMI is doubly nasty. It can happen on the first instruction of |
972 | * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning | |
973 | * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32 | |
974 | * switched stacks. We handle both conditions by simply checking whether we | |
975 | * interrupted kernel code running on the SYSENTER stack. | |
d211af05 AH |
976 | */ |
977 | ENTRY(nmi) | |
e59d1b0a | 978 | ASM_CLAC |
34273f41 | 979 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 IM |
980 | pushl %eax |
981 | movl %ss, %eax | |
982 | cmpw $__ESPFIX_SS, %ax | |
983 | popl %eax | |
1b00255f | 984 | je .Lnmi_espfix_stack |
34273f41 | 985 | #endif |
7536656f AL |
986 | |
987 | pushl %eax # pt_regs->orig_ax | |
d211af05 | 988 | SAVE_ALL |
946c1911 | 989 | ENCODE_FRAME_POINTER |
a49976d1 IM |
990 | xorl %edx, %edx # zero error code |
991 | movl %esp, %eax # pt_regs pointer | |
7536656f AL |
992 | |
993 | /* Are we currently on the SYSENTER stack? */ | |
994 | PER_CPU(cpu_tss + CPU_TSS_SYSENTER_stack + SIZEOF_SYSENTER_stack, %ecx) | |
995 | subl %eax, %ecx /* ecx = (end of SYSENTER_stack) - esp */ | |
996 | cmpl $SIZEOF_SYSENTER_stack, %ecx | |
997 | jb .Lnmi_from_sysenter_stack | |
998 | ||
999 | /* Not on SYSENTER stack. */ | |
a49976d1 | 1000 | call do_nmi |
1b00255f | 1001 | jmp .Lrestore_all_notrace |
d211af05 | 1002 | |
7536656f AL |
1003 | .Lnmi_from_sysenter_stack: |
1004 | /* | |
1005 | * We're on the SYSENTER stack. Switch off. No one (not even debug) | |
1006 | * is using the thread stack right now, so it's safe for us to use it. | |
1007 | */ | |
946c1911 | 1008 | movl %esp, %ebx |
7536656f AL |
1009 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esp |
1010 | call do_nmi | |
946c1911 | 1011 | movl %ebx, %esp |
1b00255f | 1012 | jmp .Lrestore_all_notrace |
d211af05 | 1013 | |
34273f41 | 1014 | #ifdef CONFIG_X86_ESPFIX32 |
1b00255f | 1015 | .Lnmi_espfix_stack: |
131484c8 | 1016 | /* |
d211af05 AH |
1017 | * create the pointer to lss back |
1018 | */ | |
a49976d1 IM |
1019 | pushl %ss |
1020 | pushl %esp | |
1021 | addl $4, (%esp) | |
d211af05 AH |
1022 | /* copy the iret frame of 12 bytes */ |
1023 | .rept 3 | |
a49976d1 | 1024 | pushl 16(%esp) |
d211af05 | 1025 | .endr |
a49976d1 | 1026 | pushl %eax |
d211af05 | 1027 | SAVE_ALL |
946c1911 | 1028 | ENCODE_FRAME_POINTER |
a49976d1 IM |
1029 | FIXUP_ESPFIX_STACK # %eax == %esp |
1030 | xorl %edx, %edx # zero error code | |
1031 | call do_nmi | |
d211af05 | 1032 | RESTORE_REGS |
a49976d1 | 1033 | lss 12+4(%esp), %esp # back to espfix stack |
1b00255f | 1034 | jmp .Lirq_return |
34273f41 | 1035 | #endif |
d211af05 AH |
1036 | END(nmi) |
1037 | ||
1038 | ENTRY(int3) | |
e59d1b0a | 1039 | ASM_CLAC |
a49976d1 | 1040 | pushl $-1 # mark this as an int |
d211af05 | 1041 | SAVE_ALL |
946c1911 | 1042 | ENCODE_FRAME_POINTER |
d211af05 | 1043 | TRACE_IRQS_OFF |
a49976d1 IM |
1044 | xorl %edx, %edx # zero error code |
1045 | movl %esp, %eax # pt_regs pointer | |
1046 | call do_int3 | |
1047 | jmp ret_from_exception | |
d211af05 AH |
1048 | END(int3) |
1049 | ||
1050 | ENTRY(general_protection) | |
a49976d1 | 1051 | pushl $do_general_protection |
7252c4c3 | 1052 | jmp common_exception |
d211af05 AH |
1053 | END(general_protection) |
1054 | ||
631bc487 GN |
1055 | #ifdef CONFIG_KVM_GUEST |
1056 | ENTRY(async_page_fault) | |
e59d1b0a | 1057 | ASM_CLAC |
a49976d1 | 1058 | pushl $do_async_page_fault |
7252c4c3 | 1059 | jmp common_exception |
2ae9d293 | 1060 | END(async_page_fault) |
631bc487 | 1061 | #endif |
2deb4be2 AL |
1062 | |
1063 | ENTRY(rewind_stack_do_exit) | |
1064 | /* Prevent any naive code from trying to unwind to our caller. */ | |
1065 | xorl %ebp, %ebp | |
1066 | ||
1067 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esi | |
1068 | leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp | |
1069 | ||
1070 | call do_exit | |
1071 | 1: jmp 1b | |
1072 | END(rewind_stack_do_exit) |