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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/entry.S | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
4d732138 | 7 | * |
1da177e4 LT |
8 | * entry.S contains the system-call and fault low-level handling routines. |
9 | * | |
8b4777a4 AL |
10 | * Some of this is documented in Documentation/x86/entry_64.txt |
11 | * | |
0bd7b798 | 12 | * A note on terminology: |
4d732138 IM |
13 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
14 | * at the top of the kernel process stack. | |
2e91a17b AK |
15 | * |
16 | * Some macro usage: | |
4d732138 IM |
17 | * - ENTRY/END: Define functions in the symbol table. |
18 | * - TRACE_IRQ_*: Trace hardirq state for lock debugging. | |
19 | * - idtentry: Define exception entry points. | |
1da177e4 | 20 | */ |
1da177e4 LT |
21 | #include <linux/linkage.h> |
22 | #include <asm/segment.h> | |
1da177e4 LT |
23 | #include <asm/cache.h> |
24 | #include <asm/errno.h> | |
d36f9479 | 25 | #include "calling.h" |
e2d5df93 | 26 | #include <asm/asm-offsets.h> |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/unistd.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/hw_irq.h> | |
0341c14d | 31 | #include <asm/page_types.h> |
2601e64d | 32 | #include <asm/irqflags.h> |
72fe4858 | 33 | #include <asm/paravirt.h> |
9939ddaf | 34 | #include <asm/percpu.h> |
d7abc0fa | 35 | #include <asm/asm.h> |
63bcff2a | 36 | #include <asm/smap.h> |
3891a04a | 37 | #include <asm/pgtable_types.h> |
784d5699 | 38 | #include <asm/export.h> |
d7e7528b | 39 | #include <linux/err.h> |
1da177e4 | 40 | |
4d732138 IM |
41 | .code64 |
42 | .section .entry.text, "ax" | |
16444a8a | 43 | |
72fe4858 | 44 | #ifdef CONFIG_PARAVIRT |
2be29982 | 45 | ENTRY(native_usergs_sysret64) |
72fe4858 GOC |
46 | swapgs |
47 | sysretq | |
b3baaa13 | 48 | ENDPROC(native_usergs_sysret64) |
72fe4858 GOC |
49 | #endif /* CONFIG_PARAVIRT */ |
50 | ||
f2db9382 | 51 | .macro TRACE_IRQS_IRETQ |
2601e64d | 52 | #ifdef CONFIG_TRACE_IRQFLAGS |
4d732138 IM |
53 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
54 | jnc 1f | |
2601e64d IM |
55 | TRACE_IRQS_ON |
56 | 1: | |
57 | #endif | |
58 | .endm | |
59 | ||
5963e317 SR |
60 | /* |
61 | * When dynamic function tracer is enabled it will add a breakpoint | |
62 | * to all locations that it is about to modify, sync CPUs, update | |
63 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
64 | * if lockdep is enabled, it might jump back into the debug handler | |
65 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
66 | * | |
67 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
68 | * make sure the stack pointer does not get reset back to the top | |
69 | * of the debug stack, and instead just reuses the current stack. | |
70 | */ | |
71 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
72 | ||
73 | .macro TRACE_IRQS_OFF_DEBUG | |
4d732138 | 74 | call debug_stack_set_zero |
5963e317 | 75 | TRACE_IRQS_OFF |
4d732138 | 76 | call debug_stack_reset |
5963e317 SR |
77 | .endm |
78 | ||
79 | .macro TRACE_IRQS_ON_DEBUG | |
4d732138 | 80 | call debug_stack_set_zero |
5963e317 | 81 | TRACE_IRQS_ON |
4d732138 | 82 | call debug_stack_reset |
5963e317 SR |
83 | .endm |
84 | ||
f2db9382 | 85 | .macro TRACE_IRQS_IRETQ_DEBUG |
4d732138 IM |
86 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
87 | jnc 1f | |
5963e317 SR |
88 | TRACE_IRQS_ON_DEBUG |
89 | 1: | |
90 | .endm | |
91 | ||
92 | #else | |
4d732138 IM |
93 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF |
94 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
95 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
5963e317 SR |
96 | #endif |
97 | ||
1da177e4 | 98 | /* |
4d732138 | 99 | * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 100 | * |
fda57b22 AL |
101 | * This is the only entry point used for 64-bit system calls. The |
102 | * hardware interface is reasonably well designed and the register to | |
103 | * argument mapping Linux uses fits well with the registers that are | |
104 | * available when SYSCALL is used. | |
105 | * | |
106 | * SYSCALL instructions can be found inlined in libc implementations as | |
107 | * well as some other programs and libraries. There are also a handful | |
108 | * of SYSCALL instructions in the vDSO used, for example, as a | |
109 | * clock_gettimeofday fallback. | |
110 | * | |
4d732138 | 111 | * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
b87cf63e DV |
112 | * then loads new ss, cs, and rip from previously programmed MSRs. |
113 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
114 | * are not needed). SYSCALL does not save anything on the stack | |
115 | * and does not change rsp. | |
116 | * | |
117 | * Registers on entry: | |
1da177e4 | 118 | * rax system call number |
b87cf63e DV |
119 | * rcx return address |
120 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 121 | * rdi arg0 |
1da177e4 | 122 | * rsi arg1 |
0bd7b798 | 123 | * rdx arg2 |
b87cf63e | 124 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
125 | * r8 arg4 |
126 | * r9 arg5 | |
4d732138 | 127 | * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) |
0bd7b798 | 128 | * |
1da177e4 LT |
129 | * Only called from user space. |
130 | * | |
7fcb3bc3 | 131 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
132 | * it deals with uncanonical addresses better. SYSRET has trouble |
133 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 134 | */ |
1da177e4 | 135 | |
b2502b41 | 136 | ENTRY(entry_SYSCALL_64) |
9ed8e7d8 DV |
137 | /* |
138 | * Interrupts are off on entry. | |
139 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
140 | * it is too small to ever cause noticeable irq latency. | |
141 | */ | |
72fe4858 GOC |
142 | SWAPGS_UNSAFE_STACK |
143 | /* | |
144 | * A hypervisor implementation might want to use a label | |
145 | * after the swapgs, so that it can do the swapgs | |
146 | * for the guest and jump here on syscall. | |
147 | */ | |
b2502b41 | 148 | GLOBAL(entry_SYSCALL_64_after_swapgs) |
72fe4858 | 149 | |
4d732138 IM |
150 | movq %rsp, PER_CPU_VAR(rsp_scratch) |
151 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
9ed8e7d8 | 152 | |
1e423bff AL |
153 | TRACE_IRQS_OFF |
154 | ||
9ed8e7d8 | 155 | /* Construct struct pt_regs on stack */ |
4d732138 IM |
156 | pushq $__USER_DS /* pt_regs->ss */ |
157 | pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
4d732138 IM |
158 | pushq %r11 /* pt_regs->flags */ |
159 | pushq $__USER_CS /* pt_regs->cs */ | |
160 | pushq %rcx /* pt_regs->ip */ | |
161 | pushq %rax /* pt_regs->orig_ax */ | |
162 | pushq %rdi /* pt_regs->di */ | |
163 | pushq %rsi /* pt_regs->si */ | |
164 | pushq %rdx /* pt_regs->dx */ | |
165 | pushq %rcx /* pt_regs->cx */ | |
166 | pushq $-ENOSYS /* pt_regs->ax */ | |
167 | pushq %r8 /* pt_regs->r8 */ | |
168 | pushq %r9 /* pt_regs->r9 */ | |
169 | pushq %r10 /* pt_regs->r10 */ | |
170 | pushq %r11 /* pt_regs->r11 */ | |
171 | sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 not saved */ | |
172 | ||
1e423bff AL |
173 | /* |
174 | * If we need to do entry work or if we guess we'll need to do | |
175 | * exit work, go straight to the slow path. | |
176 | */ | |
15f4eae7 AL |
177 | movq PER_CPU_VAR(current_task), %r11 |
178 | testl $_TIF_WORK_SYSCALL_ENTRY|_TIF_ALLWORK_MASK, TASK_TI_flags(%r11) | |
1e423bff AL |
179 | jnz entry_SYSCALL64_slow_path |
180 | ||
b2502b41 | 181 | entry_SYSCALL_64_fastpath: |
1e423bff AL |
182 | /* |
183 | * Easy case: enable interrupts and issue the syscall. If the syscall | |
184 | * needs pt_regs, we'll call a stub that disables interrupts again | |
185 | * and jumps to the slow path. | |
186 | */ | |
187 | TRACE_IRQS_ON | |
188 | ENABLE_INTERRUPTS(CLBR_NONE) | |
fca460f9 | 189 | #if __SYSCALL_MASK == ~0 |
4d732138 | 190 | cmpq $__NR_syscall_max, %rax |
fca460f9 | 191 | #else |
4d732138 IM |
192 | andl $__SYSCALL_MASK, %eax |
193 | cmpl $__NR_syscall_max, %eax | |
fca460f9 | 194 | #endif |
4d732138 IM |
195 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
196 | movq %r10, %rcx | |
302f5b26 AL |
197 | |
198 | /* | |
199 | * This call instruction is handled specially in stub_ptregs_64. | |
b7765086 AL |
200 | * It might end up jumping to the slow path. If it jumps, RAX |
201 | * and all argument registers are clobbered. | |
302f5b26 | 202 | */ |
4d732138 | 203 | call *sys_call_table(, %rax, 8) |
302f5b26 AL |
204 | .Lentry_SYSCALL_64_after_fastpath_call: |
205 | ||
4d732138 | 206 | movq %rax, RAX(%rsp) |
146b2b09 | 207 | 1: |
b3494a4a AL |
208 | |
209 | /* | |
1e423bff AL |
210 | * If we get here, then we know that pt_regs is clean for SYSRET64. |
211 | * If we see that no exit work is required (which we are required | |
212 | * to check with IRQs off), then we can go straight to SYSRET64. | |
b3494a4a | 213 | */ |
2140a994 | 214 | DISABLE_INTERRUPTS(CLBR_ANY) |
1e423bff | 215 | TRACE_IRQS_OFF |
15f4eae7 AL |
216 | movq PER_CPU_VAR(current_task), %r11 |
217 | testl $_TIF_ALLWORK_MASK, TASK_TI_flags(%r11) | |
1e423bff | 218 | jnz 1f |
b3494a4a | 219 | |
1e423bff AL |
220 | LOCKDEP_SYS_EXIT |
221 | TRACE_IRQS_ON /* user mode is traced as IRQs on */ | |
eb2a54c3 AL |
222 | movq RIP(%rsp), %rcx |
223 | movq EFLAGS(%rsp), %r11 | |
224 | RESTORE_C_REGS_EXCEPT_RCX_R11 | |
4d732138 | 225 | movq RSP(%rsp), %rsp |
2be29982 | 226 | USERGS_SYSRET64 |
1da177e4 | 227 | |
1e423bff AL |
228 | 1: |
229 | /* | |
230 | * The fast path looked good when we started, but something changed | |
231 | * along the way and we need to switch to the slow path. Calling | |
232 | * raise(3) will trigger this, for example. IRQs are off. | |
233 | */ | |
29ea1b25 | 234 | TRACE_IRQS_ON |
2140a994 | 235 | ENABLE_INTERRUPTS(CLBR_ANY) |
76f5df43 | 236 | SAVE_EXTRA_REGS |
4d732138 | 237 | movq %rsp, %rdi |
1e423bff AL |
238 | call syscall_return_slowpath /* returns with IRQs disabled */ |
239 | jmp return_from_SYSCALL_64 | |
0bd7b798 | 240 | |
1e423bff AL |
241 | entry_SYSCALL64_slow_path: |
242 | /* IRQs are off. */ | |
76f5df43 | 243 | SAVE_EXTRA_REGS |
29ea1b25 | 244 | movq %rsp, %rdi |
1e423bff AL |
245 | call do_syscall_64 /* returns with IRQs disabled */ |
246 | ||
247 | return_from_SYSCALL_64: | |
76f5df43 | 248 | RESTORE_EXTRA_REGS |
29ea1b25 | 249 | TRACE_IRQS_IRETQ /* we're about to change IF */ |
fffbb5dc DV |
250 | |
251 | /* | |
252 | * Try to use SYSRET instead of IRET if we're returning to | |
253 | * a completely clean 64-bit userspace context. | |
254 | */ | |
4d732138 IM |
255 | movq RCX(%rsp), %rcx |
256 | movq RIP(%rsp), %r11 | |
257 | cmpq %rcx, %r11 /* RCX == RIP */ | |
258 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
259 | |
260 | /* | |
261 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
262 | * in kernel space. This essentially lets the user take over | |
17be0aec | 263 | * the kernel, since userspace controls RSP. |
fffbb5dc | 264 | * |
17be0aec | 265 | * If width of "canonical tail" ever becomes variable, this will need |
fffbb5dc | 266 | * to be updated to remain correct on both old and new CPUs. |
361b4b58 | 267 | * |
cbe0317b KS |
268 | * Change top bits to match most significant bit (47th or 56th bit |
269 | * depending on paging mode) in the address. | |
fffbb5dc | 270 | */ |
17be0aec DV |
271 | shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx |
272 | sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
4d732138 | 273 | |
17be0aec DV |
274 | /* If this changed %rcx, it was not canonical */ |
275 | cmpq %rcx, %r11 | |
276 | jne opportunistic_sysret_failed | |
fffbb5dc | 277 | |
4d732138 IM |
278 | cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ |
279 | jne opportunistic_sysret_failed | |
fffbb5dc | 280 | |
4d732138 IM |
281 | movq R11(%rsp), %r11 |
282 | cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ | |
283 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
284 | |
285 | /* | |
3e035305 BP |
286 | * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot |
287 | * restore RF properly. If the slowpath sets it for whatever reason, we | |
288 | * need to restore it correctly. | |
289 | * | |
290 | * SYSRET can restore TF, but unlike IRET, restoring TF results in a | |
291 | * trap from userspace immediately after SYSRET. This would cause an | |
292 | * infinite loop whenever #DB happens with register state that satisfies | |
293 | * the opportunistic SYSRET conditions. For example, single-stepping | |
294 | * this user code: | |
fffbb5dc | 295 | * |
4d732138 | 296 | * movq $stuck_here, %rcx |
fffbb5dc DV |
297 | * pushfq |
298 | * popq %r11 | |
299 | * stuck_here: | |
300 | * | |
301 | * would never get past 'stuck_here'. | |
302 | */ | |
4d732138 IM |
303 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 |
304 | jnz opportunistic_sysret_failed | |
fffbb5dc DV |
305 | |
306 | /* nothing to check for RSP */ | |
307 | ||
4d732138 IM |
308 | cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ |
309 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
310 | |
311 | /* | |
4d732138 IM |
312 | * We win! This label is here just for ease of understanding |
313 | * perf profiles. Nothing jumps here. | |
fffbb5dc DV |
314 | */ |
315 | syscall_return_via_sysret: | |
17be0aec DV |
316 | /* rcx and r11 are already restored (see code above) */ |
317 | RESTORE_C_REGS_EXCEPT_RCX_R11 | |
4d732138 | 318 | movq RSP(%rsp), %rsp |
fffbb5dc | 319 | USERGS_SYSRET64 |
fffbb5dc DV |
320 | |
321 | opportunistic_sysret_failed: | |
322 | SWAPGS | |
323 | jmp restore_c_regs_and_iret | |
b2502b41 | 324 | END(entry_SYSCALL_64) |
0bd7b798 | 325 | |
302f5b26 AL |
326 | ENTRY(stub_ptregs_64) |
327 | /* | |
328 | * Syscalls marked as needing ptregs land here. | |
b7765086 AL |
329 | * If we are on the fast path, we need to save the extra regs, |
330 | * which we achieve by trying again on the slow path. If we are on | |
331 | * the slow path, the extra regs are already saved. | |
302f5b26 AL |
332 | * |
333 | * RAX stores a pointer to the C function implementing the syscall. | |
b7765086 | 334 | * IRQs are on. |
302f5b26 AL |
335 | */ |
336 | cmpq $.Lentry_SYSCALL_64_after_fastpath_call, (%rsp) | |
337 | jne 1f | |
338 | ||
b7765086 AL |
339 | /* |
340 | * Called from fast path -- disable IRQs again, pop return address | |
341 | * and jump to slow path | |
342 | */ | |
2140a994 | 343 | DISABLE_INTERRUPTS(CLBR_ANY) |
b7765086 | 344 | TRACE_IRQS_OFF |
302f5b26 | 345 | popq %rax |
b7765086 | 346 | jmp entry_SYSCALL64_slow_path |
302f5b26 AL |
347 | |
348 | 1: | |
b3830e8d | 349 | jmp *%rax /* Called from C */ |
302f5b26 AL |
350 | END(stub_ptregs_64) |
351 | ||
352 | .macro ptregs_stub func | |
353 | ENTRY(ptregs_\func) | |
354 | leaq \func(%rip), %rax | |
355 | jmp stub_ptregs_64 | |
356 | END(ptregs_\func) | |
357 | .endm | |
358 | ||
359 | /* Instantiate ptregs_stub for each ptregs-using syscall */ | |
360 | #define __SYSCALL_64_QUAL_(sym) | |
361 | #define __SYSCALL_64_QUAL_ptregs(sym) ptregs_stub sym | |
362 | #define __SYSCALL_64(nr, sym, qual) __SYSCALL_64_QUAL_##qual(sym) | |
363 | #include <asm/syscalls_64.h> | |
fffbb5dc | 364 | |
0100301b BG |
365 | /* |
366 | * %rdi: prev task | |
367 | * %rsi: next task | |
368 | */ | |
369 | ENTRY(__switch_to_asm) | |
370 | /* | |
371 | * Save callee-saved registers | |
372 | * This must match the order in inactive_task_frame | |
373 | */ | |
374 | pushq %rbp | |
375 | pushq %rbx | |
376 | pushq %r12 | |
377 | pushq %r13 | |
378 | pushq %r14 | |
379 | pushq %r15 | |
380 | ||
381 | /* switch stack */ | |
382 | movq %rsp, TASK_threadsp(%rdi) | |
383 | movq TASK_threadsp(%rsi), %rsp | |
384 | ||
385 | #ifdef CONFIG_CC_STACKPROTECTOR | |
386 | movq TASK_stack_canary(%rsi), %rbx | |
387 | movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset | |
388 | #endif | |
389 | ||
390 | /* restore callee-saved registers */ | |
391 | popq %r15 | |
392 | popq %r14 | |
393 | popq %r13 | |
394 | popq %r12 | |
395 | popq %rbx | |
396 | popq %rbp | |
397 | ||
398 | jmp __switch_to | |
399 | END(__switch_to_asm) | |
400 | ||
1eeb207f DV |
401 | /* |
402 | * A newly forked process directly context switches into this address. | |
403 | * | |
0100301b | 404 | * rax: prev task we switched from |
616d2483 BG |
405 | * rbx: kernel thread func (NULL for user thread) |
406 | * r12: kernel thread arg | |
1eeb207f DV |
407 | */ |
408 | ENTRY(ret_from_fork) | |
0100301b | 409 | movq %rax, %rdi |
ebd57499 | 410 | call schedule_tail /* rdi: 'prev' task parameter */ |
1eeb207f | 411 | |
ebd57499 JP |
412 | testq %rbx, %rbx /* from kernel_thread? */ |
413 | jnz 1f /* kernel threads are uncommon */ | |
24d978b7 | 414 | |
616d2483 | 415 | 2: |
ebd57499 | 416 | movq %rsp, %rdi |
24d978b7 AL |
417 | call syscall_return_slowpath /* returns with IRQs disabled */ |
418 | TRACE_IRQS_ON /* user mode is traced as IRQS on */ | |
419 | SWAPGS | |
420 | jmp restore_regs_and_iret | |
616d2483 BG |
421 | |
422 | 1: | |
423 | /* kernel thread */ | |
424 | movq %r12, %rdi | |
425 | call *%rbx | |
426 | /* | |
427 | * A kernel thread is allowed to return here after successfully | |
428 | * calling do_execve(). Exit to userspace to complete the execve() | |
429 | * syscall. | |
430 | */ | |
431 | movq $0, RAX(%rsp) | |
432 | jmp 2b | |
1eeb207f DV |
433 | END(ret_from_fork) |
434 | ||
939b7871 | 435 | /* |
3304c9c3 DV |
436 | * Build the entry stubs with some assembler magic. |
437 | * We pack 1 stub into every 8-byte block. | |
939b7871 | 438 | */ |
3304c9c3 | 439 | .align 8 |
939b7871 | 440 | ENTRY(irq_entries_start) |
3304c9c3 DV |
441 | vector=FIRST_EXTERNAL_VECTOR |
442 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
4d732138 | 443 | pushq $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
444 | vector=vector+1 |
445 | jmp common_interrupt | |
3304c9c3 DV |
446 | .align 8 |
447 | .endr | |
939b7871 PA |
448 | END(irq_entries_start) |
449 | ||
1d3e53e8 AL |
450 | .macro DEBUG_ENTRY_ASSERT_IRQS_OFF |
451 | #ifdef CONFIG_DEBUG_ENTRY | |
452 | pushfq | |
453 | testl $X86_EFLAGS_IF, (%rsp) | |
454 | jz .Lokay_\@ | |
455 | ud2 | |
456 | .Lokay_\@: | |
457 | addq $8, %rsp | |
458 | #endif | |
459 | .endm | |
460 | ||
461 | /* | |
462 | * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers | |
463 | * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. | |
464 | * Requires kernel GSBASE. | |
465 | * | |
466 | * The invariant is that, if irq_count != -1, then the IRQ stack is in use. | |
467 | */ | |
468 | .macro ENTER_IRQ_STACK old_rsp | |
469 | DEBUG_ENTRY_ASSERT_IRQS_OFF | |
470 | movq %rsp, \old_rsp | |
471 | incl PER_CPU_VAR(irq_count) | |
472 | ||
473 | /* | |
474 | * Right now, if we just incremented irq_count to zero, we've | |
475 | * claimed the IRQ stack but we haven't switched to it yet. | |
476 | * | |
477 | * If anything is added that can interrupt us here without using IST, | |
478 | * it must be *extremely* careful to limit its stack usage. This | |
479 | * could include kprobes and a hypothetical future IST-less #DB | |
480 | * handler. | |
481 | */ | |
482 | ||
483 | cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp | |
484 | pushq \old_rsp | |
485 | .endm | |
486 | ||
487 | /* | |
488 | * Undoes ENTER_IRQ_STACK. | |
489 | */ | |
490 | .macro LEAVE_IRQ_STACK | |
491 | DEBUG_ENTRY_ASSERT_IRQS_OFF | |
492 | /* We need to be off the IRQ stack before decrementing irq_count. */ | |
493 | popq %rsp | |
494 | ||
495 | /* | |
496 | * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming | |
497 | * the irq stack but we're not on it. | |
498 | */ | |
499 | ||
500 | decl PER_CPU_VAR(irq_count) | |
501 | .endm | |
502 | ||
d99015b1 | 503 | /* |
1da177e4 LT |
504 | * Interrupt entry/exit. |
505 | * | |
506 | * Interrupt entry points save only callee clobbered registers in fast path. | |
d99015b1 AH |
507 | * |
508 | * Entry runs with interrupts off. | |
509 | */ | |
1da177e4 | 510 | |
722024db | 511 | /* 0(%rsp): ~(interrupt number) */ |
1da177e4 | 512 | .macro interrupt func |
f6f64681 | 513 | cld |
ff467594 AL |
514 | ALLOC_PT_GPREGS_ON_STACK |
515 | SAVE_C_REGS | |
516 | SAVE_EXTRA_REGS | |
946c1911 | 517 | ENCODE_FRAME_POINTER |
76f5df43 | 518 | |
ff467594 | 519 | testb $3, CS(%rsp) |
dde74f2e | 520 | jz 1f |
02bc7768 AL |
521 | |
522 | /* | |
523 | * IRQ from user mode. Switch to kernel gsbase and inform context | |
524 | * tracking that we're in kernel mode. | |
525 | */ | |
f6f64681 | 526 | SWAPGS |
f1075053 AL |
527 | |
528 | /* | |
529 | * We need to tell lockdep that IRQs are off. We can't do this until | |
530 | * we fix gsbase, and we should do it before enter_from_user_mode | |
531 | * (which can take locks). Since TRACE_IRQS_OFF idempotent, | |
532 | * the simplest way to handle it is to just call it twice if | |
533 | * we enter from user mode. There's no reason to optimize this since | |
534 | * TRACE_IRQS_OFF is a no-op if lockdep is off. | |
535 | */ | |
536 | TRACE_IRQS_OFF | |
537 | ||
478dc89c | 538 | CALL_enter_from_user_mode |
02bc7768 | 539 | |
76f5df43 | 540 | 1: |
1d3e53e8 | 541 | ENTER_IRQ_STACK old_rsp=%rdi |
f6f64681 DV |
542 | /* We entered an interrupt context - irqs are off: */ |
543 | TRACE_IRQS_OFF | |
544 | ||
a586f98e | 545 | call \func /* rdi points to pt_regs */ |
1da177e4 LT |
546 | .endm |
547 | ||
722024db AH |
548 | /* |
549 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
550 | * then jump to common_interrupt. | |
551 | */ | |
939b7871 PA |
552 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
553 | common_interrupt: | |
ee4eb87b | 554 | ASM_CLAC |
4d732138 | 555 | addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ |
1da177e4 | 556 | interrupt do_IRQ |
34061f13 | 557 | /* 0(%rsp): old RSP */ |
7effaa88 | 558 | ret_from_intr: |
2140a994 | 559 | DISABLE_INTERRUPTS(CLBR_ANY) |
2601e64d | 560 | TRACE_IRQS_OFF |
625dbc3b | 561 | |
1d3e53e8 | 562 | LEAVE_IRQ_STACK |
625dbc3b | 563 | |
03335e95 | 564 | testb $3, CS(%rsp) |
dde74f2e | 565 | jz retint_kernel |
4d732138 | 566 | |
02bc7768 | 567 | /* Interrupt came from user space */ |
02bc7768 AL |
568 | GLOBAL(retint_user) |
569 | mov %rsp,%rdi | |
570 | call prepare_exit_to_usermode | |
2601e64d | 571 | TRACE_IRQS_IRETQ |
72fe4858 | 572 | SWAPGS |
ff467594 | 573 | jmp restore_regs_and_iret |
2601e64d | 574 | |
627276cb | 575 | /* Returning to kernel space */ |
6ba71b76 | 576 | retint_kernel: |
627276cb DV |
577 | #ifdef CONFIG_PREEMPT |
578 | /* Interrupts are off */ | |
579 | /* Check if we need preemption */ | |
4d732138 | 580 | bt $9, EFLAGS(%rsp) /* were interrupts off? */ |
6ba71b76 | 581 | jnc 1f |
4d732138 | 582 | 0: cmpl $0, PER_CPU_VAR(__preempt_count) |
36acef25 | 583 | jnz 1f |
627276cb | 584 | call preempt_schedule_irq |
36acef25 | 585 | jmp 0b |
6ba71b76 | 586 | 1: |
627276cb | 587 | #endif |
2601e64d IM |
588 | /* |
589 | * The iretq could re-enable interrupts: | |
590 | */ | |
591 | TRACE_IRQS_IRETQ | |
fffbb5dc DV |
592 | |
593 | /* | |
594 | * At this label, code paths which return to kernel and to user, | |
595 | * which come from interrupts/exception and from syscalls, merge. | |
596 | */ | |
ee08c6bd | 597 | GLOBAL(restore_regs_and_iret) |
ff467594 | 598 | RESTORE_EXTRA_REGS |
fffbb5dc | 599 | restore_c_regs_and_iret: |
76f5df43 DV |
600 | RESTORE_C_REGS |
601 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
7209a75d AL |
602 | INTERRUPT_RETURN |
603 | ||
604 | ENTRY(native_iret) | |
3891a04a PA |
605 | /* |
606 | * Are we returning to a stack segment from the LDT? Note: in | |
607 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
608 | */ | |
34273f41 | 609 | #ifdef CONFIG_X86_ESPFIX64 |
4d732138 IM |
610 | testb $4, (SS-RIP)(%rsp) |
611 | jnz native_irq_return_ldt | |
34273f41 | 612 | #endif |
3891a04a | 613 | |
af726f21 | 614 | .global native_irq_return_iret |
7209a75d | 615 | native_irq_return_iret: |
b645af2d AL |
616 | /* |
617 | * This may fault. Non-paranoid faults on return to userspace are | |
618 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
619 | * Double-faults due to espfix64 are handled in do_double_fault. | |
620 | * Other faults here are fatal. | |
621 | */ | |
1da177e4 | 622 | iretq |
3701d863 | 623 | |
34273f41 | 624 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 625 | native_irq_return_ldt: |
85063fac AL |
626 | /* |
627 | * We are running with user GSBASE. All GPRs contain their user | |
628 | * values. We have a percpu ESPFIX stack that is eight slots | |
629 | * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom | |
630 | * of the ESPFIX stack. | |
631 | * | |
632 | * We clobber RAX and RDI in this code. We stash RDI on the | |
633 | * normal stack and RAX on the ESPFIX stack. | |
634 | * | |
635 | * The ESPFIX stack layout we set up looks like this: | |
636 | * | |
637 | * --- top of ESPFIX stack --- | |
638 | * SS | |
639 | * RSP | |
640 | * RFLAGS | |
641 | * CS | |
642 | * RIP <-- RSP points here when we're done | |
643 | * RAX <-- espfix_waddr points here | |
644 | * --- bottom of ESPFIX stack --- | |
645 | */ | |
646 | ||
647 | pushq %rdi /* Stash user RDI */ | |
3891a04a | 648 | SWAPGS |
4d732138 | 649 | movq PER_CPU_VAR(espfix_waddr), %rdi |
85063fac AL |
650 | movq %rax, (0*8)(%rdi) /* user RAX */ |
651 | movq (1*8)(%rsp), %rax /* user RIP */ | |
4d732138 | 652 | movq %rax, (1*8)(%rdi) |
85063fac | 653 | movq (2*8)(%rsp), %rax /* user CS */ |
4d732138 | 654 | movq %rax, (2*8)(%rdi) |
85063fac | 655 | movq (3*8)(%rsp), %rax /* user RFLAGS */ |
4d732138 | 656 | movq %rax, (3*8)(%rdi) |
85063fac | 657 | movq (5*8)(%rsp), %rax /* user SS */ |
4d732138 | 658 | movq %rax, (5*8)(%rdi) |
85063fac | 659 | movq (4*8)(%rsp), %rax /* user RSP */ |
4d732138 | 660 | movq %rax, (4*8)(%rdi) |
85063fac AL |
661 | /* Now RAX == RSP. */ |
662 | ||
663 | andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ | |
664 | popq %rdi /* Restore user RDI */ | |
665 | ||
666 | /* | |
667 | * espfix_stack[31:16] == 0. The page tables are set up such that | |
668 | * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of | |
669 | * espfix_waddr for any X. That is, there are 65536 RO aliases of | |
670 | * the same page. Set up RSP so that RSP[31:16] contains the | |
671 | * respective 16 bits of the /userspace/ RSP and RSP nonetheless | |
672 | * still points to an RO alias of the ESPFIX stack. | |
673 | */ | |
4d732138 | 674 | orq PER_CPU_VAR(espfix_stack), %rax |
3891a04a | 675 | SWAPGS |
4d732138 | 676 | movq %rax, %rsp |
85063fac AL |
677 | |
678 | /* | |
679 | * At this point, we cannot write to the stack any more, but we can | |
680 | * still read. | |
681 | */ | |
682 | popq %rax /* Restore user RAX */ | |
683 | ||
684 | /* | |
685 | * RSP now points to an ordinary IRET frame, except that the page | |
686 | * is read-only and RSP[31:16] are preloaded with the userspace | |
687 | * values. We can now IRET back to userspace. | |
688 | */ | |
4d732138 | 689 | jmp native_irq_return_iret |
34273f41 | 690 | #endif |
4b787e0b | 691 | END(common_interrupt) |
3891a04a | 692 | |
1da177e4 LT |
693 | /* |
694 | * APIC interrupts. | |
0bd7b798 | 695 | */ |
cf910e83 | 696 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 697 | ENTRY(\sym) |
ee4eb87b | 698 | ASM_CLAC |
4d732138 | 699 | pushq $~(\num) |
39e95433 | 700 | .Lcommon_\sym: |
322648d1 | 701 | interrupt \do_sym |
4d732138 | 702 | jmp ret_from_intr |
322648d1 AH |
703 | END(\sym) |
704 | .endm | |
1da177e4 | 705 | |
cf910e83 SA |
706 | #ifdef CONFIG_TRACING |
707 | #define trace(sym) trace_##sym | |
708 | #define smp_trace(sym) smp_trace_##sym | |
709 | ||
710 | .macro trace_apicinterrupt num sym | |
711 | apicinterrupt3 \num trace(\sym) smp_trace(\sym) | |
712 | .endm | |
713 | #else | |
714 | .macro trace_apicinterrupt num sym do_sym | |
715 | .endm | |
716 | #endif | |
717 | ||
469f0023 AP |
718 | /* Make sure APIC interrupt handlers end up in the irqentry section: */ |
719 | #if defined(CONFIG_FUNCTION_GRAPH_TRACER) || defined(CONFIG_KASAN) | |
720 | # define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" | |
721 | # define POP_SECTION_IRQENTRY .popsection | |
722 | #else | |
723 | # define PUSH_SECTION_IRQENTRY | |
724 | # define POP_SECTION_IRQENTRY | |
725 | #endif | |
726 | ||
cf910e83 | 727 | .macro apicinterrupt num sym do_sym |
469f0023 | 728 | PUSH_SECTION_IRQENTRY |
cf910e83 SA |
729 | apicinterrupt3 \num \sym \do_sym |
730 | trace_apicinterrupt \num \sym | |
469f0023 | 731 | POP_SECTION_IRQENTRY |
cf910e83 SA |
732 | .endm |
733 | ||
322648d1 | 734 | #ifdef CONFIG_SMP |
4d732138 IM |
735 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
736 | apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt | |
322648d1 | 737 | #endif |
1da177e4 | 738 | |
03b48632 | 739 | #ifdef CONFIG_X86_UV |
4d732138 | 740 | apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 741 | #endif |
4d732138 IM |
742 | |
743 | apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt | |
744 | apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 745 | |
d78f2664 | 746 | #ifdef CONFIG_HAVE_KVM |
4d732138 IM |
747 | apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
748 | apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi | |
d78f2664 YZ |
749 | #endif |
750 | ||
33e5ff63 | 751 | #ifdef CONFIG_X86_MCE_THRESHOLD |
4d732138 | 752 | apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
753 | #endif |
754 | ||
24fd78a8 | 755 | #ifdef CONFIG_X86_MCE_AMD |
4d732138 | 756 | apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt |
24fd78a8 AG |
757 | #endif |
758 | ||
33e5ff63 | 759 | #ifdef CONFIG_X86_THERMAL_VECTOR |
4d732138 | 760 | apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt |
33e5ff63 | 761 | #endif |
1812924b | 762 | |
322648d1 | 763 | #ifdef CONFIG_SMP |
4d732138 IM |
764 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt |
765 | apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt | |
766 | apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt | |
322648d1 | 767 | #endif |
1da177e4 | 768 | |
4d732138 IM |
769 | apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt |
770 | apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 771 | |
e360adbe | 772 | #ifdef CONFIG_IRQ_WORK |
4d732138 | 773 | apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt |
241771ef IM |
774 | #endif |
775 | ||
1da177e4 LT |
776 | /* |
777 | * Exception entry points. | |
0bd7b798 | 778 | */ |
9b476688 | 779 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) |
577ed45e AL |
780 | |
781 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 782 | ENTRY(\sym) |
577ed45e AL |
783 | /* Sanity check */ |
784 | .if \shift_ist != -1 && \paranoid == 0 | |
785 | .error "using shift_ist requires paranoid=1" | |
786 | .endif | |
787 | ||
ee4eb87b | 788 | ASM_CLAC |
b8b1d08b | 789 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
cb5dd2c5 AL |
790 | |
791 | .ifeq \has_error_code | |
4d732138 | 792 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
cb5dd2c5 AL |
793 | .endif |
794 | ||
76f5df43 | 795 | ALLOC_PT_GPREGS_ON_STACK |
cb5dd2c5 AL |
796 | |
797 | .if \paranoid | |
48e08d0f | 798 | .if \paranoid == 1 |
4d732138 IM |
799 | testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ |
800 | jnz 1f | |
48e08d0f | 801 | .endif |
4d732138 | 802 | call paranoid_entry |
cb5dd2c5 | 803 | .else |
4d732138 | 804 | call error_entry |
cb5dd2c5 | 805 | .endif |
ebfc453e | 806 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 807 | |
cb5dd2c5 | 808 | .if \paranoid |
577ed45e | 809 | .if \shift_ist != -1 |
4d732138 | 810 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ |
577ed45e | 811 | .else |
b8b1d08b | 812 | TRACE_IRQS_OFF |
cb5dd2c5 | 813 | .endif |
577ed45e | 814 | .endif |
cb5dd2c5 | 815 | |
4d732138 | 816 | movq %rsp, %rdi /* pt_regs pointer */ |
cb5dd2c5 AL |
817 | |
818 | .if \has_error_code | |
4d732138 IM |
819 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
820 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
cb5dd2c5 | 821 | .else |
4d732138 | 822 | xorl %esi, %esi /* no error code */ |
cb5dd2c5 AL |
823 | .endif |
824 | ||
577ed45e | 825 | .if \shift_ist != -1 |
4d732138 | 826 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
827 | .endif |
828 | ||
4d732138 | 829 | call \do_sym |
cb5dd2c5 | 830 | |
577ed45e | 831 | .if \shift_ist != -1 |
4d732138 | 832 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
833 | .endif |
834 | ||
ebfc453e | 835 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 836 | .if \paranoid |
4d732138 | 837 | jmp paranoid_exit |
cb5dd2c5 | 838 | .else |
4d732138 | 839 | jmp error_exit |
cb5dd2c5 AL |
840 | .endif |
841 | ||
48e08d0f | 842 | .if \paranoid == 1 |
48e08d0f AL |
843 | /* |
844 | * Paranoid entry from userspace. Switch stacks and treat it | |
845 | * as a normal entry. This means that paranoid handlers | |
846 | * run in real process context if user_mode(regs). | |
847 | */ | |
848 | 1: | |
4d732138 | 849 | call error_entry |
48e08d0f | 850 | |
48e08d0f | 851 | |
4d732138 IM |
852 | movq %rsp, %rdi /* pt_regs pointer */ |
853 | call sync_regs | |
854 | movq %rax, %rsp /* switch stack */ | |
48e08d0f | 855 | |
4d732138 | 856 | movq %rsp, %rdi /* pt_regs pointer */ |
48e08d0f AL |
857 | |
858 | .if \has_error_code | |
4d732138 IM |
859 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
860 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
48e08d0f | 861 | .else |
4d732138 | 862 | xorl %esi, %esi /* no error code */ |
48e08d0f AL |
863 | .endif |
864 | ||
4d732138 | 865 | call \do_sym |
48e08d0f | 866 | |
4d732138 | 867 | jmp error_exit /* %ebx: no swapgs flag */ |
48e08d0f | 868 | .endif |
ddeb8f21 | 869 | END(\sym) |
322648d1 | 870 | .endm |
b8b1d08b | 871 | |
25c74b10 | 872 | #ifdef CONFIG_TRACING |
cb5dd2c5 AL |
873 | .macro trace_idtentry sym do_sym has_error_code:req |
874 | idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code | |
875 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
876 | .endm |
877 | #else | |
cb5dd2c5 AL |
878 | .macro trace_idtentry sym do_sym has_error_code:req |
879 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
880 | .endm |
881 | #endif | |
882 | ||
4d732138 IM |
883 | idtentry divide_error do_divide_error has_error_code=0 |
884 | idtentry overflow do_overflow has_error_code=0 | |
885 | idtentry bounds do_bounds has_error_code=0 | |
886 | idtentry invalid_op do_invalid_op has_error_code=0 | |
887 | idtentry device_not_available do_device_not_available has_error_code=0 | |
888 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 | |
889 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 | |
890 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
891 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
892 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
893 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
894 | idtentry alignment_check do_alignment_check has_error_code=1 | |
895 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
896 | ||
897 | ||
898 | /* | |
899 | * Reload gs selector with exception handling | |
900 | * edi: new selector | |
901 | */ | |
9f9d489a | 902 | ENTRY(native_load_gs_index) |
131484c8 | 903 | pushfq |
b8aa287f | 904 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
9f1e87ea | 905 | SWAPGS |
42c748bb | 906 | .Lgs_change: |
4d732138 | 907 | movl %edi, %gs |
96e5d28a | 908 | 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE |
72fe4858 | 909 | SWAPGS |
131484c8 | 910 | popfq |
9f1e87ea | 911 | ret |
6efdcfaf | 912 | END(native_load_gs_index) |
784d5699 | 913 | EXPORT_SYMBOL(native_load_gs_index) |
0bd7b798 | 914 | |
42c748bb | 915 | _ASM_EXTABLE(.Lgs_change, bad_gs) |
4d732138 | 916 | .section .fixup, "ax" |
1da177e4 | 917 | /* running with kernelgs */ |
0bd7b798 | 918 | bad_gs: |
4d732138 | 919 | SWAPGS /* switch back to user gs */ |
b038c842 AL |
920 | .macro ZAP_GS |
921 | /* This can't be a string because the preprocessor needs to see it. */ | |
922 | movl $__USER_DS, %eax | |
923 | movl %eax, %gs | |
924 | .endm | |
925 | ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG | |
4d732138 IM |
926 | xorl %eax, %eax |
927 | movl %eax, %gs | |
928 | jmp 2b | |
9f1e87ea | 929 | .previous |
0bd7b798 | 930 | |
2699500b | 931 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 932 | ENTRY(do_softirq_own_stack) |
4d732138 IM |
933 | pushq %rbp |
934 | mov %rsp, %rbp | |
1d3e53e8 | 935 | ENTER_IRQ_STACK old_rsp=%r11 |
4d732138 | 936 | call __do_softirq |
1d3e53e8 | 937 | LEAVE_IRQ_STACK |
2699500b | 938 | leaveq |
ed6b676c | 939 | ret |
7d65f4a6 | 940 | END(do_softirq_own_stack) |
75154f40 | 941 | |
3d75e1b8 | 942 | #ifdef CONFIG_XEN |
cb5dd2c5 | 943 | idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
944 | |
945 | /* | |
9f1e87ea CG |
946 | * A note on the "critical region" in our callback handler. |
947 | * We want to avoid stacking callback handlers due to events occurring | |
948 | * during handling of the last event. To do this, we keep events disabled | |
949 | * until we've done all processing. HOWEVER, we must enable events before | |
950 | * popping the stack frame (can't be done atomically) and so it would still | |
951 | * be possible to get enough handler activations to overflow the stack. | |
952 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
953 | * like to avoid the possibility. | |
954 | * So, on entry to the handler we detect whether we interrupted an | |
955 | * existing activation in its critical region -- if so, we pop the current | |
956 | * activation and restart the handler using the previous one. | |
957 | */ | |
4d732138 IM |
958 | ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ |
959 | ||
9f1e87ea CG |
960 | /* |
961 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
962 | * see the correct pointer to the pt_regs | |
963 | */ | |
4d732138 | 964 | movq %rdi, %rsp /* we don't return, adjust the stack frame */ |
1d3e53e8 AL |
965 | |
966 | ENTER_IRQ_STACK old_rsp=%r10 | |
4d732138 | 967 | call xen_evtchn_do_upcall |
1d3e53e8 AL |
968 | LEAVE_IRQ_STACK |
969 | ||
fdfd811d | 970 | #ifndef CONFIG_PREEMPT |
4d732138 | 971 | call xen_maybe_preempt_hcall |
fdfd811d | 972 | #endif |
4d732138 | 973 | jmp error_exit |
371c394a | 974 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
975 | |
976 | /* | |
9f1e87ea CG |
977 | * Hypervisor uses this for application faults while it executes. |
978 | * We get here for two reasons: | |
979 | * 1. Fault while reloading DS, ES, FS or GS | |
980 | * 2. Fault while executing IRET | |
981 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
982 | * registers that could be reloaded and zeroed the others. | |
983 | * Category 2 we fix up by killing the current process. We cannot use the | |
984 | * normal Linux return path in this case because if we use the IRET hypercall | |
985 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
986 | * We distinguish between categories by comparing each saved segment register | |
987 | * with its current contents: any discrepancy means we in category 1. | |
988 | */ | |
3d75e1b8 | 989 | ENTRY(xen_failsafe_callback) |
4d732138 IM |
990 | movl %ds, %ecx |
991 | cmpw %cx, 0x10(%rsp) | |
992 | jne 1f | |
993 | movl %es, %ecx | |
994 | cmpw %cx, 0x18(%rsp) | |
995 | jne 1f | |
996 | movl %fs, %ecx | |
997 | cmpw %cx, 0x20(%rsp) | |
998 | jne 1f | |
999 | movl %gs, %ecx | |
1000 | cmpw %cx, 0x28(%rsp) | |
1001 | jne 1f | |
3d75e1b8 | 1002 | /* All segments match their saved values => Category 2 (Bad IRET). */ |
4d732138 IM |
1003 | movq (%rsp), %rcx |
1004 | movq 8(%rsp), %r11 | |
1005 | addq $0x30, %rsp | |
1006 | pushq $0 /* RIP */ | |
1007 | pushq %r11 | |
1008 | pushq %rcx | |
1009 | jmp general_protection | |
3d75e1b8 | 1010 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ |
4d732138 IM |
1011 | movq (%rsp), %rcx |
1012 | movq 8(%rsp), %r11 | |
1013 | addq $0x30, %rsp | |
1014 | pushq $-1 /* orig_ax = -1 => not a system call */ | |
76f5df43 DV |
1015 | ALLOC_PT_GPREGS_ON_STACK |
1016 | SAVE_C_REGS | |
1017 | SAVE_EXTRA_REGS | |
946c1911 | 1018 | ENCODE_FRAME_POINTER |
4d732138 | 1019 | jmp error_exit |
3d75e1b8 JF |
1020 | END(xen_failsafe_callback) |
1021 | ||
cf910e83 | 1022 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
1023 | xen_hvm_callback_vector xen_evtchn_do_upcall |
1024 | ||
3d75e1b8 | 1025 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 1026 | |
bc2b0331 | 1027 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 1028 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 S |
1029 | hyperv_callback_vector hyperv_vector_handler |
1030 | #endif /* CONFIG_HYPERV */ | |
1031 | ||
4d732138 IM |
1032 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
1033 | idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK | |
1034 | idtentry stack_segment do_stack_segment has_error_code=1 | |
1035 | ||
6cac5a92 | 1036 | #ifdef CONFIG_XEN |
4d732138 IM |
1037 | idtentry xen_debug do_debug has_error_code=0 |
1038 | idtentry xen_int3 do_int3 has_error_code=0 | |
1039 | idtentry xen_stack_segment do_stack_segment has_error_code=1 | |
6cac5a92 | 1040 | #endif |
4d732138 IM |
1041 | |
1042 | idtentry general_protection do_general_protection has_error_code=1 | |
1043 | trace_idtentry page_fault do_page_fault has_error_code=1 | |
1044 | ||
631bc487 | 1045 | #ifdef CONFIG_KVM_GUEST |
4d732138 | 1046 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 1047 | #endif |
4d732138 | 1048 | |
ddeb8f21 | 1049 | #ifdef CONFIG_X86_MCE |
4d732138 | 1050 | idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip) |
ddeb8f21 AH |
1051 | #endif |
1052 | ||
ebfc453e DV |
1053 | /* |
1054 | * Save all registers in pt_regs, and switch gs if needed. | |
1055 | * Use slow, but surefire "are we in kernel?" check. | |
1056 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
1057 | */ | |
1058 | ENTRY(paranoid_entry) | |
1eeb207f DV |
1059 | cld |
1060 | SAVE_C_REGS 8 | |
1061 | SAVE_EXTRA_REGS 8 | |
946c1911 | 1062 | ENCODE_FRAME_POINTER 8 |
4d732138 IM |
1063 | movl $1, %ebx |
1064 | movl $MSR_GS_BASE, %ecx | |
1eeb207f | 1065 | rdmsr |
4d732138 IM |
1066 | testl %edx, %edx |
1067 | js 1f /* negative -> in kernel */ | |
1eeb207f | 1068 | SWAPGS |
4d732138 | 1069 | xorl %ebx, %ebx |
1eeb207f | 1070 | 1: ret |
ebfc453e | 1071 | END(paranoid_entry) |
ddeb8f21 | 1072 | |
ebfc453e DV |
1073 | /* |
1074 | * "Paranoid" exit path from exception stack. This is invoked | |
1075 | * only on return from non-NMI IST interrupts that came | |
1076 | * from kernel space. | |
1077 | * | |
1078 | * We may be returning to very strange contexts (e.g. very early | |
1079 | * in syscall entry), so checking for preemption here would | |
1080 | * be complicated. Fortunately, we there's no good reason | |
1081 | * to try to handle preemption here. | |
4d732138 IM |
1082 | * |
1083 | * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) | |
ebfc453e | 1084 | */ |
ddeb8f21 | 1085 | ENTRY(paranoid_exit) |
2140a994 | 1086 | DISABLE_INTERRUPTS(CLBR_ANY) |
5963e317 | 1087 | TRACE_IRQS_OFF_DEBUG |
4d732138 IM |
1088 | testl %ebx, %ebx /* swapgs needed? */ |
1089 | jnz paranoid_exit_no_swapgs | |
f2db9382 | 1090 | TRACE_IRQS_IRETQ |
ddeb8f21 | 1091 | SWAPGS_UNSAFE_STACK |
4d732138 | 1092 | jmp paranoid_exit_restore |
0d550836 | 1093 | paranoid_exit_no_swapgs: |
f2db9382 | 1094 | TRACE_IRQS_IRETQ_DEBUG |
0d550836 | 1095 | paranoid_exit_restore: |
76f5df43 DV |
1096 | RESTORE_EXTRA_REGS |
1097 | RESTORE_C_REGS | |
1098 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
48e08d0f | 1099 | INTERRUPT_RETURN |
ddeb8f21 AH |
1100 | END(paranoid_exit) |
1101 | ||
1102 | /* | |
ebfc453e | 1103 | * Save all registers in pt_regs, and switch gs if needed. |
539f5113 | 1104 | * Return: EBX=0: came from user mode; EBX=1: otherwise |
ddeb8f21 AH |
1105 | */ |
1106 | ENTRY(error_entry) | |
ddeb8f21 | 1107 | cld |
76f5df43 DV |
1108 | SAVE_C_REGS 8 |
1109 | SAVE_EXTRA_REGS 8 | |
946c1911 | 1110 | ENCODE_FRAME_POINTER 8 |
4d732138 | 1111 | xorl %ebx, %ebx |
03335e95 | 1112 | testb $3, CS+8(%rsp) |
cb6f64ed | 1113 | jz .Lerror_kernelspace |
539f5113 | 1114 | |
cb6f64ed AL |
1115 | /* |
1116 | * We entered from user mode or we're pretending to have entered | |
1117 | * from user mode due to an IRET fault. | |
1118 | */ | |
ddeb8f21 | 1119 | SWAPGS |
539f5113 | 1120 | |
cb6f64ed | 1121 | .Lerror_entry_from_usermode_after_swapgs: |
f1075053 AL |
1122 | /* |
1123 | * We need to tell lockdep that IRQs are off. We can't do this until | |
1124 | * we fix gsbase, and we should do it before enter_from_user_mode | |
1125 | * (which can take locks). | |
1126 | */ | |
1127 | TRACE_IRQS_OFF | |
478dc89c | 1128 | CALL_enter_from_user_mode |
f1075053 | 1129 | ret |
02bc7768 | 1130 | |
cb6f64ed | 1131 | .Lerror_entry_done: |
ddeb8f21 AH |
1132 | TRACE_IRQS_OFF |
1133 | ret | |
ddeb8f21 | 1134 | |
ebfc453e DV |
1135 | /* |
1136 | * There are two places in the kernel that can potentially fault with | |
1137 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1138 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1139 | * for these here too. | |
1140 | */ | |
cb6f64ed | 1141 | .Lerror_kernelspace: |
4d732138 IM |
1142 | incl %ebx |
1143 | leaq native_irq_return_iret(%rip), %rcx | |
1144 | cmpq %rcx, RIP+8(%rsp) | |
cb6f64ed | 1145 | je .Lerror_bad_iret |
4d732138 IM |
1146 | movl %ecx, %eax /* zero extend */ |
1147 | cmpq %rax, RIP+8(%rsp) | |
cb6f64ed | 1148 | je .Lbstep_iret |
42c748bb | 1149 | cmpq $.Lgs_change, RIP+8(%rsp) |
cb6f64ed | 1150 | jne .Lerror_entry_done |
539f5113 AL |
1151 | |
1152 | /* | |
42c748bb | 1153 | * hack: .Lgs_change can fail with user gsbase. If this happens, fix up |
539f5113 | 1154 | * gsbase and proceed. We'll fix up the exception and land in |
42c748bb | 1155 | * .Lgs_change's error handler with kernel gsbase. |
539f5113 | 1156 | */ |
2fa5f04f WL |
1157 | SWAPGS |
1158 | jmp .Lerror_entry_done | |
ae24ffe5 | 1159 | |
cb6f64ed | 1160 | .Lbstep_iret: |
ae24ffe5 | 1161 | /* Fix truncated RIP */ |
4d732138 | 1162 | movq %rcx, RIP+8(%rsp) |
b645af2d AL |
1163 | /* fall through */ |
1164 | ||
cb6f64ed | 1165 | .Lerror_bad_iret: |
539f5113 AL |
1166 | /* |
1167 | * We came from an IRET to user mode, so we have user gsbase. | |
1168 | * Switch to kernel gsbase: | |
1169 | */ | |
b645af2d | 1170 | SWAPGS |
539f5113 AL |
1171 | |
1172 | /* | |
1173 | * Pretend that the exception came from user mode: set up pt_regs | |
1174 | * as if we faulted immediately after IRET and clear EBX so that | |
1175 | * error_exit knows that we will be returning to user mode. | |
1176 | */ | |
4d732138 IM |
1177 | mov %rsp, %rdi |
1178 | call fixup_bad_iret | |
1179 | mov %rax, %rsp | |
539f5113 | 1180 | decl %ebx |
cb6f64ed | 1181 | jmp .Lerror_entry_from_usermode_after_swapgs |
ddeb8f21 AH |
1182 | END(error_entry) |
1183 | ||
1184 | ||
539f5113 | 1185 | /* |
75ca5b22 | 1186 | * On entry, EBX is a "return to kernel mode" flag: |
539f5113 AL |
1187 | * 1: already in kernel mode, don't need SWAPGS |
1188 | * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode | |
1189 | */ | |
ddeb8f21 | 1190 | ENTRY(error_exit) |
2140a994 | 1191 | DISABLE_INTERRUPTS(CLBR_ANY) |
ddeb8f21 | 1192 | TRACE_IRQS_OFF |
2140a994 | 1193 | testl %ebx, %ebx |
4d732138 IM |
1194 | jnz retint_kernel |
1195 | jmp retint_user | |
ddeb8f21 AH |
1196 | END(error_exit) |
1197 | ||
0784b364 | 1198 | /* Runs on exception stack */ |
ddeb8f21 | 1199 | ENTRY(nmi) |
fc57a7c6 AL |
1200 | /* |
1201 | * Fix up the exception frame if we're on Xen. | |
1202 | * PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most | |
1203 | * one value to the stack on native, so it may clobber the rdx | |
1204 | * scratch slot, but it won't clobber any of the important | |
1205 | * slots past it. | |
1206 | * | |
1207 | * Xen is a different story, because the Xen frame itself overlaps | |
1208 | * the "NMI executing" variable. | |
1209 | */ | |
ddeb8f21 | 1210 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
fc57a7c6 | 1211 | |
3f3c8b8c SR |
1212 | /* |
1213 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1214 | * the iretq it performs will take us out of NMI context. | |
1215 | * This means that we can have nested NMIs where the next | |
1216 | * NMI is using the top of the stack of the previous NMI. We | |
1217 | * can't let it execute because the nested NMI will corrupt the | |
1218 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1219 | * anyway. | |
1220 | * | |
1221 | * To handle this case we do the following: | |
1222 | * Check the a special location on the stack that contains | |
1223 | * a variable that is set when NMIs are executing. | |
1224 | * The interrupted task's stack is also checked to see if it | |
1225 | * is an NMI stack. | |
1226 | * If the variable is not set and the stack is not the NMI | |
1227 | * stack then: | |
1228 | * o Set the special variable on the stack | |
0b22930e AL |
1229 | * o Copy the interrupt frame into an "outermost" location on the |
1230 | * stack | |
1231 | * o Copy the interrupt frame into an "iret" location on the stack | |
3f3c8b8c SR |
1232 | * o Continue processing the NMI |
1233 | * If the variable is set or the previous stack is the NMI stack: | |
0b22930e | 1234 | * o Modify the "iret" location to jump to the repeat_nmi |
3f3c8b8c SR |
1235 | * o return back to the first NMI |
1236 | * | |
1237 | * Now on exit of the first NMI, we first clear the stack variable | |
1238 | * The NMI stack will tell any nested NMIs at that point that it is | |
1239 | * nested. Then we pop the stack normally with iret, and if there was | |
1240 | * a nested NMI that updated the copy interrupt stack frame, a | |
1241 | * jump will be made to the repeat_nmi code that will handle the second | |
1242 | * NMI. | |
9b6e6a83 AL |
1243 | * |
1244 | * However, espfix prevents us from directly returning to userspace | |
1245 | * with a single IRET instruction. Similarly, IRET to user mode | |
1246 | * can fault. We therefore handle NMIs from user space like | |
1247 | * other IST entries. | |
3f3c8b8c SR |
1248 | */ |
1249 | ||
146b2b09 | 1250 | /* Use %rdx as our temp variable throughout */ |
4d732138 | 1251 | pushq %rdx |
3f3c8b8c | 1252 | |
9b6e6a83 AL |
1253 | testb $3, CS-RIP+8(%rsp) |
1254 | jz .Lnmi_from_kernel | |
1255 | ||
1256 | /* | |
1257 | * NMI from user mode. We need to run on the thread stack, but we | |
1258 | * can't go through the normal entry paths: NMIs are masked, and | |
1259 | * we don't want to enable interrupts, because then we'll end | |
1260 | * up in an awkward situation in which IRQs are on but NMIs | |
1261 | * are off. | |
83c133cf AL |
1262 | * |
1263 | * We also must not push anything to the stack before switching | |
1264 | * stacks lest we corrupt the "NMI executing" variable. | |
9b6e6a83 AL |
1265 | */ |
1266 | ||
83c133cf | 1267 | SWAPGS_UNSAFE_STACK |
9b6e6a83 AL |
1268 | cld |
1269 | movq %rsp, %rdx | |
1270 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
1271 | pushq 5*8(%rdx) /* pt_regs->ss */ | |
1272 | pushq 4*8(%rdx) /* pt_regs->rsp */ | |
1273 | pushq 3*8(%rdx) /* pt_regs->flags */ | |
1274 | pushq 2*8(%rdx) /* pt_regs->cs */ | |
1275 | pushq 1*8(%rdx) /* pt_regs->rip */ | |
1276 | pushq $-1 /* pt_regs->orig_ax */ | |
1277 | pushq %rdi /* pt_regs->di */ | |
1278 | pushq %rsi /* pt_regs->si */ | |
1279 | pushq (%rdx) /* pt_regs->dx */ | |
1280 | pushq %rcx /* pt_regs->cx */ | |
1281 | pushq %rax /* pt_regs->ax */ | |
1282 | pushq %r8 /* pt_regs->r8 */ | |
1283 | pushq %r9 /* pt_regs->r9 */ | |
1284 | pushq %r10 /* pt_regs->r10 */ | |
1285 | pushq %r11 /* pt_regs->r11 */ | |
1286 | pushq %rbx /* pt_regs->rbx */ | |
1287 | pushq %rbp /* pt_regs->rbp */ | |
1288 | pushq %r12 /* pt_regs->r12 */ | |
1289 | pushq %r13 /* pt_regs->r13 */ | |
1290 | pushq %r14 /* pt_regs->r14 */ | |
1291 | pushq %r15 /* pt_regs->r15 */ | |
946c1911 | 1292 | ENCODE_FRAME_POINTER |
9b6e6a83 AL |
1293 | |
1294 | /* | |
1295 | * At this point we no longer need to worry about stack damage | |
1296 | * due to nesting -- we're on the normal thread stack and we're | |
1297 | * done with the NMI stack. | |
1298 | */ | |
1299 | ||
1300 | movq %rsp, %rdi | |
1301 | movq $-1, %rsi | |
1302 | call do_nmi | |
1303 | ||
45d5a168 | 1304 | /* |
9b6e6a83 | 1305 | * Return back to user mode. We must *not* do the normal exit |
946c1911 | 1306 | * work, because we don't want to enable interrupts. |
45d5a168 | 1307 | */ |
9b6e6a83 | 1308 | SWAPGS |
946c1911 | 1309 | jmp restore_regs_and_iret |
45d5a168 | 1310 | |
9b6e6a83 | 1311 | .Lnmi_from_kernel: |
3f3c8b8c | 1312 | /* |
0b22930e AL |
1313 | * Here's what our stack frame will look like: |
1314 | * +---------------------------------------------------------+ | |
1315 | * | original SS | | |
1316 | * | original Return RSP | | |
1317 | * | original RFLAGS | | |
1318 | * | original CS | | |
1319 | * | original RIP | | |
1320 | * +---------------------------------------------------------+ | |
1321 | * | temp storage for rdx | | |
1322 | * +---------------------------------------------------------+ | |
1323 | * | "NMI executing" variable | | |
1324 | * +---------------------------------------------------------+ | |
1325 | * | iret SS } Copied from "outermost" frame | | |
1326 | * | iret Return RSP } on each loop iteration; overwritten | | |
1327 | * | iret RFLAGS } by a nested NMI to force another | | |
1328 | * | iret CS } iteration if needed. | | |
1329 | * | iret RIP } | | |
1330 | * +---------------------------------------------------------+ | |
1331 | * | outermost SS } initialized in first_nmi; | | |
1332 | * | outermost Return RSP } will not be changed before | | |
1333 | * | outermost RFLAGS } NMI processing is done. | | |
1334 | * | outermost CS } Copied to "iret" frame on each | | |
1335 | * | outermost RIP } iteration. | | |
1336 | * +---------------------------------------------------------+ | |
1337 | * | pt_regs | | |
1338 | * +---------------------------------------------------------+ | |
1339 | * | |
1340 | * The "original" frame is used by hardware. Before re-enabling | |
1341 | * NMIs, we need to be done with it, and we need to leave enough | |
1342 | * space for the asm code here. | |
1343 | * | |
1344 | * We return by executing IRET while RSP points to the "iret" frame. | |
1345 | * That will either return for real or it will loop back into NMI | |
1346 | * processing. | |
1347 | * | |
1348 | * The "outermost" frame is copied to the "iret" frame on each | |
1349 | * iteration of the loop, so each iteration starts with the "iret" | |
1350 | * frame pointing to the final return target. | |
1351 | */ | |
1352 | ||
45d5a168 | 1353 | /* |
0b22930e AL |
1354 | * Determine whether we're a nested NMI. |
1355 | * | |
a27507ca AL |
1356 | * If we interrupted kernel code between repeat_nmi and |
1357 | * end_repeat_nmi, then we are a nested NMI. We must not | |
1358 | * modify the "iret" frame because it's being written by | |
1359 | * the outer NMI. That's okay; the outer NMI handler is | |
1360 | * about to about to call do_nmi anyway, so we can just | |
1361 | * resume the outer NMI. | |
45d5a168 | 1362 | */ |
a27507ca AL |
1363 | |
1364 | movq $repeat_nmi, %rdx | |
1365 | cmpq 8(%rsp), %rdx | |
1366 | ja 1f | |
1367 | movq $end_repeat_nmi, %rdx | |
1368 | cmpq 8(%rsp), %rdx | |
1369 | ja nested_nmi_out | |
1370 | 1: | |
45d5a168 | 1371 | |
3f3c8b8c | 1372 | /* |
a27507ca | 1373 | * Now check "NMI executing". If it's set, then we're nested. |
0b22930e AL |
1374 | * This will not detect if we interrupted an outer NMI just |
1375 | * before IRET. | |
3f3c8b8c | 1376 | */ |
4d732138 IM |
1377 | cmpl $1, -8(%rsp) |
1378 | je nested_nmi | |
3f3c8b8c SR |
1379 | |
1380 | /* | |
0b22930e AL |
1381 | * Now test if the previous stack was an NMI stack. This covers |
1382 | * the case where we interrupt an outer NMI after it clears | |
810bc075 AL |
1383 | * "NMI executing" but before IRET. We need to be careful, though: |
1384 | * there is one case in which RSP could point to the NMI stack | |
1385 | * despite there being no NMI active: naughty userspace controls | |
1386 | * RSP at the very beginning of the SYSCALL targets. We can | |
1387 | * pull a fast one on naughty userspace, though: we program | |
1388 | * SYSCALL to mask DF, so userspace cannot cause DF to be set | |
1389 | * if it controls the kernel's RSP. We set DF before we clear | |
1390 | * "NMI executing". | |
3f3c8b8c | 1391 | */ |
0784b364 DV |
1392 | lea 6*8(%rsp), %rdx |
1393 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1394 | cmpq %rdx, 4*8(%rsp) | |
1395 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1396 | ja first_nmi | |
4d732138 | 1397 | |
0784b364 DV |
1398 | subq $EXCEPTION_STKSZ, %rdx |
1399 | cmpq %rdx, 4*8(%rsp) | |
1400 | /* If it is below the NMI stack, it is a normal NMI */ | |
1401 | jb first_nmi | |
810bc075 AL |
1402 | |
1403 | /* Ah, it is within the NMI stack. */ | |
1404 | ||
1405 | testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) | |
1406 | jz first_nmi /* RSP was user controlled. */ | |
1407 | ||
1408 | /* This is a nested NMI. */ | |
0784b364 | 1409 | |
3f3c8b8c SR |
1410 | nested_nmi: |
1411 | /* | |
0b22930e AL |
1412 | * Modify the "iret" frame to point to repeat_nmi, forcing another |
1413 | * iteration of NMI handling. | |
3f3c8b8c | 1414 | */ |
23a781e9 | 1415 | subq $8, %rsp |
4d732138 IM |
1416 | leaq -10*8(%rsp), %rdx |
1417 | pushq $__KERNEL_DS | |
1418 | pushq %rdx | |
131484c8 | 1419 | pushfq |
4d732138 IM |
1420 | pushq $__KERNEL_CS |
1421 | pushq $repeat_nmi | |
3f3c8b8c SR |
1422 | |
1423 | /* Put stack back */ | |
4d732138 | 1424 | addq $(6*8), %rsp |
3f3c8b8c SR |
1425 | |
1426 | nested_nmi_out: | |
4d732138 | 1427 | popq %rdx |
3f3c8b8c | 1428 | |
0b22930e | 1429 | /* We are returning to kernel mode, so this cannot result in a fault. */ |
3f3c8b8c SR |
1430 | INTERRUPT_RETURN |
1431 | ||
1432 | first_nmi: | |
0b22930e | 1433 | /* Restore rdx. */ |
4d732138 | 1434 | movq (%rsp), %rdx |
62610913 | 1435 | |
36f1a77b AL |
1436 | /* Make room for "NMI executing". */ |
1437 | pushq $0 | |
3f3c8b8c | 1438 | |
0b22930e | 1439 | /* Leave room for the "iret" frame */ |
4d732138 | 1440 | subq $(5*8), %rsp |
28696f43 | 1441 | |
0b22930e | 1442 | /* Copy the "original" frame to the "outermost" frame */ |
3f3c8b8c | 1443 | .rept 5 |
4d732138 | 1444 | pushq 11*8(%rsp) |
3f3c8b8c | 1445 | .endr |
62610913 | 1446 | |
79fb4ad6 SR |
1447 | /* Everything up to here is safe from nested NMIs */ |
1448 | ||
a97439aa AL |
1449 | #ifdef CONFIG_DEBUG_ENTRY |
1450 | /* | |
1451 | * For ease of testing, unmask NMIs right away. Disabled by | |
1452 | * default because IRET is very expensive. | |
1453 | */ | |
1454 | pushq $0 /* SS */ | |
1455 | pushq %rsp /* RSP (minus 8 because of the previous push) */ | |
1456 | addq $8, (%rsp) /* Fix up RSP */ | |
1457 | pushfq /* RFLAGS */ | |
1458 | pushq $__KERNEL_CS /* CS */ | |
1459 | pushq $1f /* RIP */ | |
1460 | INTERRUPT_RETURN /* continues at repeat_nmi below */ | |
1461 | 1: | |
1462 | #endif | |
1463 | ||
0b22930e | 1464 | repeat_nmi: |
62610913 JB |
1465 | /* |
1466 | * If there was a nested NMI, the first NMI's iret will return | |
1467 | * here. But NMIs are still enabled and we can take another | |
1468 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1469 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1470 | * it will just return, as we are about to repeat an NMI anyway. | |
1471 | * This makes it safe to copy to the stack frame that a nested | |
1472 | * NMI will update. | |
0b22930e AL |
1473 | * |
1474 | * RSP is pointing to "outermost RIP". gsbase is unknown, but, if | |
1475 | * we're repeating an NMI, gsbase has the same value that it had on | |
1476 | * the first iteration. paranoid_entry will load the kernel | |
36f1a77b AL |
1477 | * gsbase if needed before we call do_nmi. "NMI executing" |
1478 | * is zero. | |
62610913 | 1479 | */ |
36f1a77b | 1480 | movq $1, 10*8(%rsp) /* Set "NMI executing". */ |
3f3c8b8c | 1481 | |
62610913 | 1482 | /* |
0b22930e AL |
1483 | * Copy the "outermost" frame to the "iret" frame. NMIs that nest |
1484 | * here must not modify the "iret" frame while we're writing to | |
1485 | * it or it will end up containing garbage. | |
62610913 | 1486 | */ |
4d732138 | 1487 | addq $(10*8), %rsp |
3f3c8b8c | 1488 | .rept 5 |
4d732138 | 1489 | pushq -6*8(%rsp) |
3f3c8b8c | 1490 | .endr |
4d732138 | 1491 | subq $(5*8), %rsp |
62610913 | 1492 | end_repeat_nmi: |
3f3c8b8c SR |
1493 | |
1494 | /* | |
0b22930e AL |
1495 | * Everything below this point can be preempted by a nested NMI. |
1496 | * If this happens, then the inner NMI will change the "iret" | |
1497 | * frame to point back to repeat_nmi. | |
3f3c8b8c | 1498 | */ |
4d732138 | 1499 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 DV |
1500 | ALLOC_PT_GPREGS_ON_STACK |
1501 | ||
1fd466ef | 1502 | /* |
ebfc453e | 1503 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1504 | * as we should not be calling schedule in NMI context. |
1505 | * Even with normal interrupts enabled. An NMI should not be | |
1506 | * setting NEED_RESCHED or anything that normal interrupts and | |
1507 | * exceptions might do. | |
1508 | */ | |
4d732138 | 1509 | call paranoid_entry |
7fbb98c5 | 1510 | |
ddeb8f21 | 1511 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
4d732138 IM |
1512 | movq %rsp, %rdi |
1513 | movq $-1, %rsi | |
1514 | call do_nmi | |
7fbb98c5 | 1515 | |
4d732138 IM |
1516 | testl %ebx, %ebx /* swapgs needed? */ |
1517 | jnz nmi_restore | |
ddeb8f21 AH |
1518 | nmi_swapgs: |
1519 | SWAPGS_UNSAFE_STACK | |
1520 | nmi_restore: | |
76f5df43 DV |
1521 | RESTORE_EXTRA_REGS |
1522 | RESTORE_C_REGS | |
0b22930e AL |
1523 | |
1524 | /* Point RSP at the "iret" frame. */ | |
76f5df43 | 1525 | REMOVE_PT_GPREGS_FROM_STACK 6*8 |
28696f43 | 1526 | |
810bc075 AL |
1527 | /* |
1528 | * Clear "NMI executing". Set DF first so that we can easily | |
1529 | * distinguish the remaining code between here and IRET from | |
1530 | * the SYSCALL entry and exit paths. On a native kernel, we | |
1531 | * could just inspect RIP, but, on paravirt kernels, | |
1532 | * INTERRUPT_RETURN can translate into a jump into a | |
1533 | * hypercall page. | |
1534 | */ | |
1535 | std | |
1536 | movq $0, 5*8(%rsp) /* clear "NMI executing" */ | |
0b22930e AL |
1537 | |
1538 | /* | |
1539 | * INTERRUPT_RETURN reads the "iret" frame and exits the NMI | |
1540 | * stack in a single instruction. We are returning to kernel | |
1541 | * mode, so this cannot result in a fault. | |
1542 | */ | |
5ca6f70f | 1543 | INTERRUPT_RETURN |
ddeb8f21 AH |
1544 | END(nmi) |
1545 | ||
1546 | ENTRY(ignore_sysret) | |
4d732138 | 1547 | mov $-ENOSYS, %eax |
ddeb8f21 | 1548 | sysret |
ddeb8f21 | 1549 | END(ignore_sysret) |
2deb4be2 AL |
1550 | |
1551 | ENTRY(rewind_stack_do_exit) | |
1552 | /* Prevent any naive code from trying to unwind to our caller. */ | |
1553 | xorl %ebp, %ebp | |
1554 | ||
1555 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rax | |
1556 | leaq -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%rax), %rsp | |
1557 | ||
1558 | call do_exit | |
1559 | 1: jmp 1b | |
1560 | END(rewind_stack_do_exit) |