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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/entry.S | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
4d732138 | 7 | * |
1da177e4 LT |
8 | * entry.S contains the system-call and fault low-level handling routines. |
9 | * | |
8b4777a4 AL |
10 | * Some of this is documented in Documentation/x86/entry_64.txt |
11 | * | |
0bd7b798 | 12 | * A note on terminology: |
4d732138 IM |
13 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
14 | * at the top of the kernel process stack. | |
2e91a17b AK |
15 | * |
16 | * Some macro usage: | |
4d732138 IM |
17 | * - ENTRY/END: Define functions in the symbol table. |
18 | * - TRACE_IRQ_*: Trace hardirq state for lock debugging. | |
19 | * - idtentry: Define exception entry points. | |
1da177e4 | 20 | */ |
1da177e4 LT |
21 | #include <linux/linkage.h> |
22 | #include <asm/segment.h> | |
1da177e4 LT |
23 | #include <asm/cache.h> |
24 | #include <asm/errno.h> | |
d36f9479 | 25 | #include "calling.h" |
e2d5df93 | 26 | #include <asm/asm-offsets.h> |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/unistd.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/hw_irq.h> | |
0341c14d | 31 | #include <asm/page_types.h> |
2601e64d | 32 | #include <asm/irqflags.h> |
72fe4858 | 33 | #include <asm/paravirt.h> |
9939ddaf | 34 | #include <asm/percpu.h> |
d7abc0fa | 35 | #include <asm/asm.h> |
63bcff2a | 36 | #include <asm/smap.h> |
3891a04a | 37 | #include <asm/pgtable_types.h> |
d7e7528b | 38 | #include <linux/err.h> |
1da177e4 | 39 | |
86a1c34a RM |
40 | /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ |
41 | #include <linux/elf-em.h> | |
4d732138 IM |
42 | #define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) |
43 | #define __AUDIT_ARCH_64BIT 0x80000000 | |
44 | #define __AUDIT_ARCH_LE 0x40000000 | |
ea714547 | 45 | |
4d732138 IM |
46 | .code64 |
47 | .section .entry.text, "ax" | |
16444a8a | 48 | |
72fe4858 | 49 | #ifdef CONFIG_PARAVIRT |
2be29982 | 50 | ENTRY(native_usergs_sysret64) |
72fe4858 GOC |
51 | swapgs |
52 | sysretq | |
b3baaa13 | 53 | ENDPROC(native_usergs_sysret64) |
72fe4858 GOC |
54 | #endif /* CONFIG_PARAVIRT */ |
55 | ||
f2db9382 | 56 | .macro TRACE_IRQS_IRETQ |
2601e64d | 57 | #ifdef CONFIG_TRACE_IRQFLAGS |
4d732138 IM |
58 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
59 | jnc 1f | |
2601e64d IM |
60 | TRACE_IRQS_ON |
61 | 1: | |
62 | #endif | |
63 | .endm | |
64 | ||
5963e317 SR |
65 | /* |
66 | * When dynamic function tracer is enabled it will add a breakpoint | |
67 | * to all locations that it is about to modify, sync CPUs, update | |
68 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
69 | * if lockdep is enabled, it might jump back into the debug handler | |
70 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
71 | * | |
72 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
73 | * make sure the stack pointer does not get reset back to the top | |
74 | * of the debug stack, and instead just reuses the current stack. | |
75 | */ | |
76 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
77 | ||
78 | .macro TRACE_IRQS_OFF_DEBUG | |
4d732138 | 79 | call debug_stack_set_zero |
5963e317 | 80 | TRACE_IRQS_OFF |
4d732138 | 81 | call debug_stack_reset |
5963e317 SR |
82 | .endm |
83 | ||
84 | .macro TRACE_IRQS_ON_DEBUG | |
4d732138 | 85 | call debug_stack_set_zero |
5963e317 | 86 | TRACE_IRQS_ON |
4d732138 | 87 | call debug_stack_reset |
5963e317 SR |
88 | .endm |
89 | ||
f2db9382 | 90 | .macro TRACE_IRQS_IRETQ_DEBUG |
4d732138 IM |
91 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
92 | jnc 1f | |
5963e317 SR |
93 | TRACE_IRQS_ON_DEBUG |
94 | 1: | |
95 | .endm | |
96 | ||
97 | #else | |
4d732138 IM |
98 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF |
99 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
100 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
5963e317 SR |
101 | #endif |
102 | ||
1da177e4 | 103 | /* |
4d732138 | 104 | * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 105 | * |
4d732138 | 106 | * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
b87cf63e DV |
107 | * then loads new ss, cs, and rip from previously programmed MSRs. |
108 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
109 | * are not needed). SYSCALL does not save anything on the stack | |
110 | * and does not change rsp. | |
111 | * | |
112 | * Registers on entry: | |
1da177e4 | 113 | * rax system call number |
b87cf63e DV |
114 | * rcx return address |
115 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 116 | * rdi arg0 |
1da177e4 | 117 | * rsi arg1 |
0bd7b798 | 118 | * rdx arg2 |
b87cf63e | 119 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
120 | * r8 arg4 |
121 | * r9 arg5 | |
4d732138 | 122 | * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) |
0bd7b798 | 123 | * |
1da177e4 LT |
124 | * Only called from user space. |
125 | * | |
7fcb3bc3 | 126 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
127 | * it deals with uncanonical addresses better. SYSRET has trouble |
128 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 129 | */ |
1da177e4 | 130 | |
b2502b41 | 131 | ENTRY(entry_SYSCALL_64) |
9ed8e7d8 DV |
132 | /* |
133 | * Interrupts are off on entry. | |
134 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
135 | * it is too small to ever cause noticeable irq latency. | |
136 | */ | |
72fe4858 GOC |
137 | SWAPGS_UNSAFE_STACK |
138 | /* | |
139 | * A hypervisor implementation might want to use a label | |
140 | * after the swapgs, so that it can do the swapgs | |
141 | * for the guest and jump here on syscall. | |
142 | */ | |
b2502b41 | 143 | GLOBAL(entry_SYSCALL_64_after_swapgs) |
72fe4858 | 144 | |
4d732138 IM |
145 | movq %rsp, PER_CPU_VAR(rsp_scratch) |
146 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
9ed8e7d8 DV |
147 | |
148 | /* Construct struct pt_regs on stack */ | |
4d732138 IM |
149 | pushq $__USER_DS /* pt_regs->ss */ |
150 | pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
33db1fd4 | 151 | /* |
9ed8e7d8 DV |
152 | * Re-enable interrupts. |
153 | * We use 'rsp_scratch' as a scratch space, hence irq-off block above | |
154 | * must execute atomically in the face of possible interrupt-driven | |
155 | * task preemption. We must enable interrupts only after we're done | |
156 | * with using rsp_scratch: | |
33db1fd4 DV |
157 | */ |
158 | ENABLE_INTERRUPTS(CLBR_NONE) | |
4d732138 IM |
159 | pushq %r11 /* pt_regs->flags */ |
160 | pushq $__USER_CS /* pt_regs->cs */ | |
161 | pushq %rcx /* pt_regs->ip */ | |
162 | pushq %rax /* pt_regs->orig_ax */ | |
163 | pushq %rdi /* pt_regs->di */ | |
164 | pushq %rsi /* pt_regs->si */ | |
165 | pushq %rdx /* pt_regs->dx */ | |
166 | pushq %rcx /* pt_regs->cx */ | |
167 | pushq $-ENOSYS /* pt_regs->ax */ | |
168 | pushq %r8 /* pt_regs->r8 */ | |
169 | pushq %r9 /* pt_regs->r9 */ | |
170 | pushq %r10 /* pt_regs->r10 */ | |
171 | pushq %r11 /* pt_regs->r11 */ | |
172 | sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 not saved */ | |
173 | ||
174 | testl $_TIF_WORK_SYSCALL_ENTRY, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) | |
175 | jnz tracesys | |
b2502b41 | 176 | entry_SYSCALL_64_fastpath: |
fca460f9 | 177 | #if __SYSCALL_MASK == ~0 |
4d732138 | 178 | cmpq $__NR_syscall_max, %rax |
fca460f9 | 179 | #else |
4d732138 IM |
180 | andl $__SYSCALL_MASK, %eax |
181 | cmpl $__NR_syscall_max, %eax | |
fca460f9 | 182 | #endif |
4d732138 IM |
183 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
184 | movq %r10, %rcx | |
302f5b26 AL |
185 | |
186 | /* | |
187 | * This call instruction is handled specially in stub_ptregs_64. | |
188 | * It might end up jumping to the slow path. If it jumps, RAX is | |
189 | * clobbered. | |
190 | */ | |
4d732138 | 191 | call *sys_call_table(, %rax, 8) |
302f5b26 AL |
192 | .Lentry_SYSCALL_64_after_fastpath_call: |
193 | ||
4d732138 | 194 | movq %rax, RAX(%rsp) |
146b2b09 | 195 | 1: |
1da177e4 | 196 | /* |
146b2b09 DV |
197 | * Syscall return path ending with SYSRET (fast path). |
198 | * Has incompletely filled pt_regs. | |
0bd7b798 | 199 | */ |
10cd706d | 200 | LOCKDEP_SYS_EXIT |
4416c5a6 DV |
201 | /* |
202 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
203 | * it is too small to ever cause noticeable irq latency. | |
204 | */ | |
72fe4858 | 205 | DISABLE_INTERRUPTS(CLBR_NONE) |
b3494a4a AL |
206 | |
207 | /* | |
208 | * We must check ti flags with interrupts (or at least preemption) | |
209 | * off because we must *never* return to userspace without | |
210 | * processing exit work that is enqueued if we're preempted here. | |
211 | * In particular, returning to userspace with any of the one-shot | |
212 | * flags (TIF_NOTIFY_RESUME, TIF_USER_RETURN_NOTIFY, etc) set is | |
213 | * very bad. | |
214 | */ | |
4d732138 IM |
215 | testl $_TIF_ALLWORK_MASK, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) |
216 | jnz int_ret_from_sys_call_irqs_off /* Go to the slow path */ | |
b3494a4a | 217 | |
29722cd4 | 218 | RESTORE_C_REGS_EXCEPT_RCX_R11 |
4d732138 IM |
219 | movq RIP(%rsp), %rcx |
220 | movq EFLAGS(%rsp), %r11 | |
221 | movq RSP(%rsp), %rsp | |
b87cf63e | 222 | /* |
4d732138 | 223 | * 64-bit SYSRET restores rip from rcx, |
b87cf63e DV |
224 | * rflags from r11 (but RF and VM bits are forced to 0), |
225 | * cs and ss are loaded from MSRs. | |
4416c5a6 | 226 | * Restoration of rflags re-enables interrupts. |
61f01dd9 AL |
227 | * |
228 | * NB: On AMD CPUs with the X86_BUG_SYSRET_SS_ATTRS bug, the ss | |
229 | * descriptor is not reinitialized. This means that we should | |
230 | * avoid SYSRET with SS == NULL, which could happen if we schedule, | |
231 | * exit the kernel, and re-enter using an interrupt vector. (All | |
232 | * interrupt entries on x86_64 set SS to NULL.) We prevent that | |
233 | * from happening by reloading SS in __switch_to. (Actually | |
234 | * detecting the failure in 64-bit userspace is tricky but can be | |
235 | * done.) | |
b87cf63e | 236 | */ |
2be29982 | 237 | USERGS_SYSRET64 |
1da177e4 | 238 | |
29ea1b25 AL |
239 | GLOBAL(int_ret_from_sys_call_irqs_off) |
240 | TRACE_IRQS_ON | |
241 | ENABLE_INTERRUPTS(CLBR_NONE) | |
242 | jmp int_ret_from_sys_call | |
243 | ||
7fcb3bc3 | 244 | /* Do syscall entry tracing */ |
0bd7b798 | 245 | tracesys: |
76f5df43 | 246 | SAVE_EXTRA_REGS |
4d732138 | 247 | movq %rsp, %rdi |
302f5b26 | 248 | call syscall_trace_enter |
1dcf74f6 | 249 | |
d4d67150 | 250 | /* |
e90e147c | 251 | * Reload registers from stack in case ptrace changed them. |
302f5b26 | 252 | * We don't reload %rax because syscall_trace_enter() returned |
d4d67150 RM |
253 | * the value it wants us to use in the table lookup. |
254 | */ | |
76f5df43 | 255 | RESTORE_C_REGS_EXCEPT_RAX |
fca460f9 | 256 | #if __SYSCALL_MASK == ~0 |
4d732138 | 257 | cmpq $__NR_syscall_max, %rax |
fca460f9 | 258 | #else |
4d732138 IM |
259 | andl $__SYSCALL_MASK, %eax |
260 | cmpl $__NR_syscall_max, %eax | |
fca460f9 | 261 | #endif |
4d732138 IM |
262 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
263 | movq %r10, %rcx /* fixup for C */ | |
264 | call *sys_call_table(, %rax, 8) | |
265 | movq %rax, RAX(%rsp) | |
46eabf06 | 266 | RESTORE_EXTRA_REGS |
a6de5a21 | 267 | 1: |
7fcb3bc3 | 268 | /* Use IRET because user could have changed pt_regs->foo */ |
0bd7b798 AH |
269 | |
270 | /* | |
1da177e4 | 271 | * Syscall return path ending with IRET. |
7fcb3bc3 | 272 | * Has correct iret frame. |
bcddc015 | 273 | */ |
bc8b2b92 | 274 | GLOBAL(int_ret_from_sys_call) |
76f5df43 | 275 | SAVE_EXTRA_REGS |
29ea1b25 AL |
276 | movq %rsp, %rdi |
277 | call syscall_return_slowpath /* returns with IRQs disabled */ | |
76f5df43 | 278 | RESTORE_EXTRA_REGS |
29ea1b25 | 279 | TRACE_IRQS_IRETQ /* we're about to change IF */ |
fffbb5dc DV |
280 | |
281 | /* | |
282 | * Try to use SYSRET instead of IRET if we're returning to | |
283 | * a completely clean 64-bit userspace context. | |
284 | */ | |
4d732138 IM |
285 | movq RCX(%rsp), %rcx |
286 | movq RIP(%rsp), %r11 | |
287 | cmpq %rcx, %r11 /* RCX == RIP */ | |
288 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
289 | |
290 | /* | |
291 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
292 | * in kernel space. This essentially lets the user take over | |
17be0aec | 293 | * the kernel, since userspace controls RSP. |
fffbb5dc | 294 | * |
17be0aec | 295 | * If width of "canonical tail" ever becomes variable, this will need |
fffbb5dc DV |
296 | * to be updated to remain correct on both old and new CPUs. |
297 | */ | |
298 | .ifne __VIRTUAL_MASK_SHIFT - 47 | |
299 | .error "virtual address width changed -- SYSRET checks need update" | |
300 | .endif | |
4d732138 | 301 | |
17be0aec DV |
302 | /* Change top 16 bits to be the sign-extension of 47th bit */ |
303 | shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
304 | sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
4d732138 | 305 | |
17be0aec DV |
306 | /* If this changed %rcx, it was not canonical */ |
307 | cmpq %rcx, %r11 | |
308 | jne opportunistic_sysret_failed | |
fffbb5dc | 309 | |
4d732138 IM |
310 | cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ |
311 | jne opportunistic_sysret_failed | |
fffbb5dc | 312 | |
4d732138 IM |
313 | movq R11(%rsp), %r11 |
314 | cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ | |
315 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
316 | |
317 | /* | |
318 | * SYSRET can't restore RF. SYSRET can restore TF, but unlike IRET, | |
319 | * restoring TF results in a trap from userspace immediately after | |
320 | * SYSRET. This would cause an infinite loop whenever #DB happens | |
321 | * with register state that satisfies the opportunistic SYSRET | |
322 | * conditions. For example, single-stepping this user code: | |
323 | * | |
4d732138 | 324 | * movq $stuck_here, %rcx |
fffbb5dc DV |
325 | * pushfq |
326 | * popq %r11 | |
327 | * stuck_here: | |
328 | * | |
329 | * would never get past 'stuck_here'. | |
330 | */ | |
4d732138 IM |
331 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 |
332 | jnz opportunistic_sysret_failed | |
fffbb5dc DV |
333 | |
334 | /* nothing to check for RSP */ | |
335 | ||
4d732138 IM |
336 | cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ |
337 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
338 | |
339 | /* | |
4d732138 IM |
340 | * We win! This label is here just for ease of understanding |
341 | * perf profiles. Nothing jumps here. | |
fffbb5dc DV |
342 | */ |
343 | syscall_return_via_sysret: | |
17be0aec DV |
344 | /* rcx and r11 are already restored (see code above) */ |
345 | RESTORE_C_REGS_EXCEPT_RCX_R11 | |
4d732138 | 346 | movq RSP(%rsp), %rsp |
fffbb5dc | 347 | USERGS_SYSRET64 |
fffbb5dc DV |
348 | |
349 | opportunistic_sysret_failed: | |
350 | SWAPGS | |
351 | jmp restore_c_regs_and_iret | |
b2502b41 | 352 | END(entry_SYSCALL_64) |
0bd7b798 | 353 | |
302f5b26 AL |
354 | ENTRY(stub_ptregs_64) |
355 | /* | |
356 | * Syscalls marked as needing ptregs land here. | |
357 | * If we are on the fast path, we need to save the extra regs. | |
358 | * If we are on the slow path, the extra regs are already saved. | |
359 | * | |
360 | * RAX stores a pointer to the C function implementing the syscall. | |
361 | */ | |
362 | cmpq $.Lentry_SYSCALL_64_after_fastpath_call, (%rsp) | |
363 | jne 1f | |
364 | ||
365 | /* Called from fast path -- pop return address and jump to slow path */ | |
366 | popq %rax | |
367 | jmp tracesys /* called from fast path */ | |
368 | ||
369 | 1: | |
370 | /* Called from C */ | |
371 | jmp *%rax /* called from C */ | |
372 | END(stub_ptregs_64) | |
373 | ||
374 | .macro ptregs_stub func | |
375 | ENTRY(ptregs_\func) | |
376 | leaq \func(%rip), %rax | |
377 | jmp stub_ptregs_64 | |
378 | END(ptregs_\func) | |
379 | .endm | |
380 | ||
381 | /* Instantiate ptregs_stub for each ptregs-using syscall */ | |
382 | #define __SYSCALL_64_QUAL_(sym) | |
383 | #define __SYSCALL_64_QUAL_ptregs(sym) ptregs_stub sym | |
384 | #define __SYSCALL_64(nr, sym, qual) __SYSCALL_64_QUAL_##qual(sym) | |
385 | #include <asm/syscalls_64.h> | |
fffbb5dc | 386 | |
1eeb207f DV |
387 | /* |
388 | * A newly forked process directly context switches into this address. | |
389 | * | |
390 | * rdi: prev task we switched from | |
391 | */ | |
392 | ENTRY(ret_from_fork) | |
4d732138 | 393 | LOCK ; btr $TIF_FORK, TI_flags(%r8) |
1eeb207f | 394 | |
4d732138 IM |
395 | pushq $0x0002 |
396 | popfq /* reset kernel eflags */ | |
1eeb207f | 397 | |
4d732138 | 398 | call schedule_tail /* rdi: 'prev' task parameter */ |
1eeb207f | 399 | |
4d732138 | 400 | testb $3, CS(%rsp) /* from kernel_thread? */ |
24d978b7 | 401 | jnz 1f |
1eeb207f | 402 | |
1e3fbb8a | 403 | /* |
24d978b7 AL |
404 | * We came from kernel_thread. This code path is quite twisted, and |
405 | * someone should clean it up. | |
406 | * | |
407 | * copy_thread_tls stashes the function pointer in RBX and the | |
408 | * parameter to be passed in RBP. The called function is permitted | |
409 | * to call do_execve and thereby jump to user mode. | |
1e3fbb8a | 410 | */ |
24d978b7 AL |
411 | movq RBP(%rsp), %rdi |
412 | call *RBX(%rsp) | |
413 | movl $0, RAX(%rsp) | |
1eeb207f | 414 | |
4d732138 | 415 | /* |
24d978b7 AL |
416 | * Fall through as though we're exiting a syscall. This makes a |
417 | * twisted sort of sense if we just called do_execve. | |
4d732138 | 418 | */ |
24d978b7 AL |
419 | |
420 | 1: | |
421 | movq %rsp, %rdi | |
422 | call syscall_return_slowpath /* returns with IRQs disabled */ | |
423 | TRACE_IRQS_ON /* user mode is traced as IRQS on */ | |
424 | SWAPGS | |
425 | jmp restore_regs_and_iret | |
1eeb207f DV |
426 | END(ret_from_fork) |
427 | ||
939b7871 | 428 | /* |
3304c9c3 DV |
429 | * Build the entry stubs with some assembler magic. |
430 | * We pack 1 stub into every 8-byte block. | |
939b7871 | 431 | */ |
3304c9c3 | 432 | .align 8 |
939b7871 | 433 | ENTRY(irq_entries_start) |
3304c9c3 DV |
434 | vector=FIRST_EXTERNAL_VECTOR |
435 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
4d732138 | 436 | pushq $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
437 | vector=vector+1 |
438 | jmp common_interrupt | |
3304c9c3 DV |
439 | .align 8 |
440 | .endr | |
939b7871 PA |
441 | END(irq_entries_start) |
442 | ||
d99015b1 | 443 | /* |
1da177e4 LT |
444 | * Interrupt entry/exit. |
445 | * | |
446 | * Interrupt entry points save only callee clobbered registers in fast path. | |
d99015b1 AH |
447 | * |
448 | * Entry runs with interrupts off. | |
449 | */ | |
1da177e4 | 450 | |
722024db | 451 | /* 0(%rsp): ~(interrupt number) */ |
1da177e4 | 452 | .macro interrupt func |
f6f64681 | 453 | cld |
ff467594 AL |
454 | ALLOC_PT_GPREGS_ON_STACK |
455 | SAVE_C_REGS | |
456 | SAVE_EXTRA_REGS | |
76f5df43 | 457 | |
ff467594 | 458 | testb $3, CS(%rsp) |
dde74f2e | 459 | jz 1f |
02bc7768 AL |
460 | |
461 | /* | |
462 | * IRQ from user mode. Switch to kernel gsbase and inform context | |
463 | * tracking that we're in kernel mode. | |
464 | */ | |
f6f64681 | 465 | SWAPGS |
f1075053 AL |
466 | |
467 | /* | |
468 | * We need to tell lockdep that IRQs are off. We can't do this until | |
469 | * we fix gsbase, and we should do it before enter_from_user_mode | |
470 | * (which can take locks). Since TRACE_IRQS_OFF idempotent, | |
471 | * the simplest way to handle it is to just call it twice if | |
472 | * we enter from user mode. There's no reason to optimize this since | |
473 | * TRACE_IRQS_OFF is a no-op if lockdep is off. | |
474 | */ | |
475 | TRACE_IRQS_OFF | |
476 | ||
478dc89c | 477 | CALL_enter_from_user_mode |
02bc7768 | 478 | |
76f5df43 | 479 | 1: |
f6f64681 | 480 | /* |
e90e147c | 481 | * Save previous stack pointer, optionally switch to interrupt stack. |
f6f64681 DV |
482 | * irq_count is used to check if a CPU is already on an interrupt stack |
483 | * or not. While this is essentially redundant with preempt_count it is | |
484 | * a little cheaper to use a separate counter in the PDA (short of | |
485 | * moving irq_enter into assembly, which would be too much work) | |
486 | */ | |
a586f98e | 487 | movq %rsp, %rdi |
4d732138 IM |
488 | incl PER_CPU_VAR(irq_count) |
489 | cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp | |
a586f98e | 490 | pushq %rdi |
f6f64681 DV |
491 | /* We entered an interrupt context - irqs are off: */ |
492 | TRACE_IRQS_OFF | |
493 | ||
a586f98e | 494 | call \func /* rdi points to pt_regs */ |
1da177e4 LT |
495 | .endm |
496 | ||
722024db AH |
497 | /* |
498 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
499 | * then jump to common_interrupt. | |
500 | */ | |
939b7871 PA |
501 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
502 | common_interrupt: | |
ee4eb87b | 503 | ASM_CLAC |
4d732138 | 504 | addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ |
1da177e4 | 505 | interrupt do_IRQ |
34061f13 | 506 | /* 0(%rsp): old RSP */ |
7effaa88 | 507 | ret_from_intr: |
72fe4858 | 508 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 509 | TRACE_IRQS_OFF |
4d732138 | 510 | decl PER_CPU_VAR(irq_count) |
625dbc3b | 511 | |
a2bbe750 | 512 | /* Restore saved previous stack */ |
ff467594 | 513 | popq %rsp |
625dbc3b | 514 | |
03335e95 | 515 | testb $3, CS(%rsp) |
dde74f2e | 516 | jz retint_kernel |
4d732138 | 517 | |
02bc7768 | 518 | /* Interrupt came from user space */ |
02bc7768 AL |
519 | GLOBAL(retint_user) |
520 | mov %rsp,%rdi | |
521 | call prepare_exit_to_usermode | |
2601e64d | 522 | TRACE_IRQS_IRETQ |
72fe4858 | 523 | SWAPGS |
ff467594 | 524 | jmp restore_regs_and_iret |
2601e64d | 525 | |
627276cb | 526 | /* Returning to kernel space */ |
6ba71b76 | 527 | retint_kernel: |
627276cb DV |
528 | #ifdef CONFIG_PREEMPT |
529 | /* Interrupts are off */ | |
530 | /* Check if we need preemption */ | |
4d732138 | 531 | bt $9, EFLAGS(%rsp) /* were interrupts off? */ |
6ba71b76 | 532 | jnc 1f |
4d732138 | 533 | 0: cmpl $0, PER_CPU_VAR(__preempt_count) |
36acef25 | 534 | jnz 1f |
627276cb | 535 | call preempt_schedule_irq |
36acef25 | 536 | jmp 0b |
6ba71b76 | 537 | 1: |
627276cb | 538 | #endif |
2601e64d IM |
539 | /* |
540 | * The iretq could re-enable interrupts: | |
541 | */ | |
542 | TRACE_IRQS_IRETQ | |
fffbb5dc DV |
543 | |
544 | /* | |
545 | * At this label, code paths which return to kernel and to user, | |
546 | * which come from interrupts/exception and from syscalls, merge. | |
547 | */ | |
ee08c6bd | 548 | GLOBAL(restore_regs_and_iret) |
ff467594 | 549 | RESTORE_EXTRA_REGS |
fffbb5dc | 550 | restore_c_regs_and_iret: |
76f5df43 DV |
551 | RESTORE_C_REGS |
552 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
7209a75d AL |
553 | INTERRUPT_RETURN |
554 | ||
555 | ENTRY(native_iret) | |
3891a04a PA |
556 | /* |
557 | * Are we returning to a stack segment from the LDT? Note: in | |
558 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
559 | */ | |
34273f41 | 560 | #ifdef CONFIG_X86_ESPFIX64 |
4d732138 IM |
561 | testb $4, (SS-RIP)(%rsp) |
562 | jnz native_irq_return_ldt | |
34273f41 | 563 | #endif |
3891a04a | 564 | |
af726f21 | 565 | .global native_irq_return_iret |
7209a75d | 566 | native_irq_return_iret: |
b645af2d AL |
567 | /* |
568 | * This may fault. Non-paranoid faults on return to userspace are | |
569 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
570 | * Double-faults due to espfix64 are handled in do_double_fault. | |
571 | * Other faults here are fatal. | |
572 | */ | |
1da177e4 | 573 | iretq |
3701d863 | 574 | |
34273f41 | 575 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 576 | native_irq_return_ldt: |
4d732138 IM |
577 | pushq %rax |
578 | pushq %rdi | |
3891a04a | 579 | SWAPGS |
4d732138 IM |
580 | movq PER_CPU_VAR(espfix_waddr), %rdi |
581 | movq %rax, (0*8)(%rdi) /* RAX */ | |
582 | movq (2*8)(%rsp), %rax /* RIP */ | |
583 | movq %rax, (1*8)(%rdi) | |
584 | movq (3*8)(%rsp), %rax /* CS */ | |
585 | movq %rax, (2*8)(%rdi) | |
586 | movq (4*8)(%rsp), %rax /* RFLAGS */ | |
587 | movq %rax, (3*8)(%rdi) | |
588 | movq (6*8)(%rsp), %rax /* SS */ | |
589 | movq %rax, (5*8)(%rdi) | |
590 | movq (5*8)(%rsp), %rax /* RSP */ | |
591 | movq %rax, (4*8)(%rdi) | |
592 | andl $0xffff0000, %eax | |
593 | popq %rdi | |
594 | orq PER_CPU_VAR(espfix_stack), %rax | |
3891a04a | 595 | SWAPGS |
4d732138 IM |
596 | movq %rax, %rsp |
597 | popq %rax | |
598 | jmp native_irq_return_iret | |
34273f41 | 599 | #endif |
4b787e0b | 600 | END(common_interrupt) |
3891a04a | 601 | |
1da177e4 LT |
602 | /* |
603 | * APIC interrupts. | |
0bd7b798 | 604 | */ |
cf910e83 | 605 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 606 | ENTRY(\sym) |
ee4eb87b | 607 | ASM_CLAC |
4d732138 | 608 | pushq $~(\num) |
39e95433 | 609 | .Lcommon_\sym: |
322648d1 | 610 | interrupt \do_sym |
4d732138 | 611 | jmp ret_from_intr |
322648d1 AH |
612 | END(\sym) |
613 | .endm | |
1da177e4 | 614 | |
cf910e83 SA |
615 | #ifdef CONFIG_TRACING |
616 | #define trace(sym) trace_##sym | |
617 | #define smp_trace(sym) smp_trace_##sym | |
618 | ||
619 | .macro trace_apicinterrupt num sym | |
620 | apicinterrupt3 \num trace(\sym) smp_trace(\sym) | |
621 | .endm | |
622 | #else | |
623 | .macro trace_apicinterrupt num sym do_sym | |
624 | .endm | |
625 | #endif | |
626 | ||
627 | .macro apicinterrupt num sym do_sym | |
628 | apicinterrupt3 \num \sym \do_sym | |
629 | trace_apicinterrupt \num \sym | |
630 | .endm | |
631 | ||
322648d1 | 632 | #ifdef CONFIG_SMP |
4d732138 IM |
633 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
634 | apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt | |
322648d1 | 635 | #endif |
1da177e4 | 636 | |
03b48632 | 637 | #ifdef CONFIG_X86_UV |
4d732138 | 638 | apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 639 | #endif |
4d732138 IM |
640 | |
641 | apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt | |
642 | apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 643 | |
d78f2664 | 644 | #ifdef CONFIG_HAVE_KVM |
4d732138 IM |
645 | apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
646 | apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi | |
d78f2664 YZ |
647 | #endif |
648 | ||
33e5ff63 | 649 | #ifdef CONFIG_X86_MCE_THRESHOLD |
4d732138 | 650 | apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
651 | #endif |
652 | ||
24fd78a8 | 653 | #ifdef CONFIG_X86_MCE_AMD |
4d732138 | 654 | apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt |
24fd78a8 AG |
655 | #endif |
656 | ||
33e5ff63 | 657 | #ifdef CONFIG_X86_THERMAL_VECTOR |
4d732138 | 658 | apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt |
33e5ff63 | 659 | #endif |
1812924b | 660 | |
322648d1 | 661 | #ifdef CONFIG_SMP |
4d732138 IM |
662 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt |
663 | apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt | |
664 | apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt | |
322648d1 | 665 | #endif |
1da177e4 | 666 | |
4d732138 IM |
667 | apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt |
668 | apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 669 | |
e360adbe | 670 | #ifdef CONFIG_IRQ_WORK |
4d732138 | 671 | apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt |
241771ef IM |
672 | #endif |
673 | ||
1da177e4 LT |
674 | /* |
675 | * Exception entry points. | |
0bd7b798 | 676 | */ |
9b476688 | 677 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) |
577ed45e AL |
678 | |
679 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 680 | ENTRY(\sym) |
577ed45e AL |
681 | /* Sanity check */ |
682 | .if \shift_ist != -1 && \paranoid == 0 | |
683 | .error "using shift_ist requires paranoid=1" | |
684 | .endif | |
685 | ||
ee4eb87b | 686 | ASM_CLAC |
b8b1d08b | 687 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
cb5dd2c5 AL |
688 | |
689 | .ifeq \has_error_code | |
4d732138 | 690 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
cb5dd2c5 AL |
691 | .endif |
692 | ||
76f5df43 | 693 | ALLOC_PT_GPREGS_ON_STACK |
cb5dd2c5 AL |
694 | |
695 | .if \paranoid | |
48e08d0f | 696 | .if \paranoid == 1 |
4d732138 IM |
697 | testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ |
698 | jnz 1f | |
48e08d0f | 699 | .endif |
4d732138 | 700 | call paranoid_entry |
cb5dd2c5 | 701 | .else |
4d732138 | 702 | call error_entry |
cb5dd2c5 | 703 | .endif |
ebfc453e | 704 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 705 | |
cb5dd2c5 | 706 | .if \paranoid |
577ed45e | 707 | .if \shift_ist != -1 |
4d732138 | 708 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ |
577ed45e | 709 | .else |
b8b1d08b | 710 | TRACE_IRQS_OFF |
cb5dd2c5 | 711 | .endif |
577ed45e | 712 | .endif |
cb5dd2c5 | 713 | |
4d732138 | 714 | movq %rsp, %rdi /* pt_regs pointer */ |
cb5dd2c5 AL |
715 | |
716 | .if \has_error_code | |
4d732138 IM |
717 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
718 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
cb5dd2c5 | 719 | .else |
4d732138 | 720 | xorl %esi, %esi /* no error code */ |
cb5dd2c5 AL |
721 | .endif |
722 | ||
577ed45e | 723 | .if \shift_ist != -1 |
4d732138 | 724 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
725 | .endif |
726 | ||
4d732138 | 727 | call \do_sym |
cb5dd2c5 | 728 | |
577ed45e | 729 | .if \shift_ist != -1 |
4d732138 | 730 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
731 | .endif |
732 | ||
ebfc453e | 733 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 734 | .if \paranoid |
4d732138 | 735 | jmp paranoid_exit |
cb5dd2c5 | 736 | .else |
4d732138 | 737 | jmp error_exit |
cb5dd2c5 AL |
738 | .endif |
739 | ||
48e08d0f | 740 | .if \paranoid == 1 |
48e08d0f AL |
741 | /* |
742 | * Paranoid entry from userspace. Switch stacks and treat it | |
743 | * as a normal entry. This means that paranoid handlers | |
744 | * run in real process context if user_mode(regs). | |
745 | */ | |
746 | 1: | |
4d732138 | 747 | call error_entry |
48e08d0f | 748 | |
48e08d0f | 749 | |
4d732138 IM |
750 | movq %rsp, %rdi /* pt_regs pointer */ |
751 | call sync_regs | |
752 | movq %rax, %rsp /* switch stack */ | |
48e08d0f | 753 | |
4d732138 | 754 | movq %rsp, %rdi /* pt_regs pointer */ |
48e08d0f AL |
755 | |
756 | .if \has_error_code | |
4d732138 IM |
757 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
758 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
48e08d0f | 759 | .else |
4d732138 | 760 | xorl %esi, %esi /* no error code */ |
48e08d0f AL |
761 | .endif |
762 | ||
4d732138 | 763 | call \do_sym |
48e08d0f | 764 | |
4d732138 | 765 | jmp error_exit /* %ebx: no swapgs flag */ |
48e08d0f | 766 | .endif |
ddeb8f21 | 767 | END(\sym) |
322648d1 | 768 | .endm |
b8b1d08b | 769 | |
25c74b10 | 770 | #ifdef CONFIG_TRACING |
cb5dd2c5 AL |
771 | .macro trace_idtentry sym do_sym has_error_code:req |
772 | idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code | |
773 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
774 | .endm |
775 | #else | |
cb5dd2c5 AL |
776 | .macro trace_idtentry sym do_sym has_error_code:req |
777 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
778 | .endm |
779 | #endif | |
780 | ||
4d732138 IM |
781 | idtentry divide_error do_divide_error has_error_code=0 |
782 | idtentry overflow do_overflow has_error_code=0 | |
783 | idtentry bounds do_bounds has_error_code=0 | |
784 | idtentry invalid_op do_invalid_op has_error_code=0 | |
785 | idtentry device_not_available do_device_not_available has_error_code=0 | |
786 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 | |
787 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 | |
788 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
789 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
790 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
791 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
792 | idtentry alignment_check do_alignment_check has_error_code=1 | |
793 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
794 | ||
795 | ||
796 | /* | |
797 | * Reload gs selector with exception handling | |
798 | * edi: new selector | |
799 | */ | |
9f9d489a | 800 | ENTRY(native_load_gs_index) |
131484c8 | 801 | pushfq |
b8aa287f | 802 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
9f1e87ea | 803 | SWAPGS |
0bd7b798 | 804 | gs_change: |
4d732138 IM |
805 | movl %edi, %gs |
806 | 2: mfence /* workaround */ | |
72fe4858 | 807 | SWAPGS |
131484c8 | 808 | popfq |
9f1e87ea | 809 | ret |
6efdcfaf | 810 | END(native_load_gs_index) |
0bd7b798 | 811 | |
4d732138 IM |
812 | _ASM_EXTABLE(gs_change, bad_gs) |
813 | .section .fixup, "ax" | |
1da177e4 | 814 | /* running with kernelgs */ |
0bd7b798 | 815 | bad_gs: |
4d732138 IM |
816 | SWAPGS /* switch back to user gs */ |
817 | xorl %eax, %eax | |
818 | movl %eax, %gs | |
819 | jmp 2b | |
9f1e87ea | 820 | .previous |
0bd7b798 | 821 | |
2699500b | 822 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 823 | ENTRY(do_softirq_own_stack) |
4d732138 IM |
824 | pushq %rbp |
825 | mov %rsp, %rbp | |
826 | incl PER_CPU_VAR(irq_count) | |
827 | cmove PER_CPU_VAR(irq_stack_ptr), %rsp | |
828 | push %rbp /* frame pointer backlink */ | |
829 | call __do_softirq | |
2699500b | 830 | leaveq |
4d732138 | 831 | decl PER_CPU_VAR(irq_count) |
ed6b676c | 832 | ret |
7d65f4a6 | 833 | END(do_softirq_own_stack) |
75154f40 | 834 | |
3d75e1b8 | 835 | #ifdef CONFIG_XEN |
cb5dd2c5 | 836 | idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
837 | |
838 | /* | |
9f1e87ea CG |
839 | * A note on the "critical region" in our callback handler. |
840 | * We want to avoid stacking callback handlers due to events occurring | |
841 | * during handling of the last event. To do this, we keep events disabled | |
842 | * until we've done all processing. HOWEVER, we must enable events before | |
843 | * popping the stack frame (can't be done atomically) and so it would still | |
844 | * be possible to get enough handler activations to overflow the stack. | |
845 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
846 | * like to avoid the possibility. | |
847 | * So, on entry to the handler we detect whether we interrupted an | |
848 | * existing activation in its critical region -- if so, we pop the current | |
849 | * activation and restart the handler using the previous one. | |
850 | */ | |
4d732138 IM |
851 | ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ |
852 | ||
9f1e87ea CG |
853 | /* |
854 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
855 | * see the correct pointer to the pt_regs | |
856 | */ | |
4d732138 IM |
857 | movq %rdi, %rsp /* we don't return, adjust the stack frame */ |
858 | 11: incl PER_CPU_VAR(irq_count) | |
859 | movq %rsp, %rbp | |
860 | cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp | |
861 | pushq %rbp /* frame pointer backlink */ | |
862 | call xen_evtchn_do_upcall | |
863 | popq %rsp | |
864 | decl PER_CPU_VAR(irq_count) | |
fdfd811d | 865 | #ifndef CONFIG_PREEMPT |
4d732138 | 866 | call xen_maybe_preempt_hcall |
fdfd811d | 867 | #endif |
4d732138 | 868 | jmp error_exit |
371c394a | 869 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
870 | |
871 | /* | |
9f1e87ea CG |
872 | * Hypervisor uses this for application faults while it executes. |
873 | * We get here for two reasons: | |
874 | * 1. Fault while reloading DS, ES, FS or GS | |
875 | * 2. Fault while executing IRET | |
876 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
877 | * registers that could be reloaded and zeroed the others. | |
878 | * Category 2 we fix up by killing the current process. We cannot use the | |
879 | * normal Linux return path in this case because if we use the IRET hypercall | |
880 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
881 | * We distinguish between categories by comparing each saved segment register | |
882 | * with its current contents: any discrepancy means we in category 1. | |
883 | */ | |
3d75e1b8 | 884 | ENTRY(xen_failsafe_callback) |
4d732138 IM |
885 | movl %ds, %ecx |
886 | cmpw %cx, 0x10(%rsp) | |
887 | jne 1f | |
888 | movl %es, %ecx | |
889 | cmpw %cx, 0x18(%rsp) | |
890 | jne 1f | |
891 | movl %fs, %ecx | |
892 | cmpw %cx, 0x20(%rsp) | |
893 | jne 1f | |
894 | movl %gs, %ecx | |
895 | cmpw %cx, 0x28(%rsp) | |
896 | jne 1f | |
3d75e1b8 | 897 | /* All segments match their saved values => Category 2 (Bad IRET). */ |
4d732138 IM |
898 | movq (%rsp), %rcx |
899 | movq 8(%rsp), %r11 | |
900 | addq $0x30, %rsp | |
901 | pushq $0 /* RIP */ | |
902 | pushq %r11 | |
903 | pushq %rcx | |
904 | jmp general_protection | |
3d75e1b8 | 905 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ |
4d732138 IM |
906 | movq (%rsp), %rcx |
907 | movq 8(%rsp), %r11 | |
908 | addq $0x30, %rsp | |
909 | pushq $-1 /* orig_ax = -1 => not a system call */ | |
76f5df43 DV |
910 | ALLOC_PT_GPREGS_ON_STACK |
911 | SAVE_C_REGS | |
912 | SAVE_EXTRA_REGS | |
4d732138 | 913 | jmp error_exit |
3d75e1b8 JF |
914 | END(xen_failsafe_callback) |
915 | ||
cf910e83 | 916 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
917 | xen_hvm_callback_vector xen_evtchn_do_upcall |
918 | ||
3d75e1b8 | 919 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 920 | |
bc2b0331 | 921 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 922 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 S |
923 | hyperv_callback_vector hyperv_vector_handler |
924 | #endif /* CONFIG_HYPERV */ | |
925 | ||
4d732138 IM |
926 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
927 | idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK | |
928 | idtentry stack_segment do_stack_segment has_error_code=1 | |
929 | ||
6cac5a92 | 930 | #ifdef CONFIG_XEN |
4d732138 IM |
931 | idtentry xen_debug do_debug has_error_code=0 |
932 | idtentry xen_int3 do_int3 has_error_code=0 | |
933 | idtentry xen_stack_segment do_stack_segment has_error_code=1 | |
6cac5a92 | 934 | #endif |
4d732138 IM |
935 | |
936 | idtentry general_protection do_general_protection has_error_code=1 | |
937 | trace_idtentry page_fault do_page_fault has_error_code=1 | |
938 | ||
631bc487 | 939 | #ifdef CONFIG_KVM_GUEST |
4d732138 | 940 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 941 | #endif |
4d732138 | 942 | |
ddeb8f21 | 943 | #ifdef CONFIG_X86_MCE |
4d732138 | 944 | idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip) |
ddeb8f21 AH |
945 | #endif |
946 | ||
ebfc453e DV |
947 | /* |
948 | * Save all registers in pt_regs, and switch gs if needed. | |
949 | * Use slow, but surefire "are we in kernel?" check. | |
950 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
951 | */ | |
952 | ENTRY(paranoid_entry) | |
1eeb207f DV |
953 | cld |
954 | SAVE_C_REGS 8 | |
955 | SAVE_EXTRA_REGS 8 | |
4d732138 IM |
956 | movl $1, %ebx |
957 | movl $MSR_GS_BASE, %ecx | |
1eeb207f | 958 | rdmsr |
4d732138 IM |
959 | testl %edx, %edx |
960 | js 1f /* negative -> in kernel */ | |
1eeb207f | 961 | SWAPGS |
4d732138 | 962 | xorl %ebx, %ebx |
1eeb207f | 963 | 1: ret |
ebfc453e | 964 | END(paranoid_entry) |
ddeb8f21 | 965 | |
ebfc453e DV |
966 | /* |
967 | * "Paranoid" exit path from exception stack. This is invoked | |
968 | * only on return from non-NMI IST interrupts that came | |
969 | * from kernel space. | |
970 | * | |
971 | * We may be returning to very strange contexts (e.g. very early | |
972 | * in syscall entry), so checking for preemption here would | |
973 | * be complicated. Fortunately, we there's no good reason | |
974 | * to try to handle preemption here. | |
4d732138 IM |
975 | * |
976 | * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) | |
ebfc453e | 977 | */ |
ddeb8f21 | 978 | ENTRY(paranoid_exit) |
ddeb8f21 | 979 | DISABLE_INTERRUPTS(CLBR_NONE) |
5963e317 | 980 | TRACE_IRQS_OFF_DEBUG |
4d732138 IM |
981 | testl %ebx, %ebx /* swapgs needed? */ |
982 | jnz paranoid_exit_no_swapgs | |
f2db9382 | 983 | TRACE_IRQS_IRETQ |
ddeb8f21 | 984 | SWAPGS_UNSAFE_STACK |
4d732138 | 985 | jmp paranoid_exit_restore |
0d550836 | 986 | paranoid_exit_no_swapgs: |
f2db9382 | 987 | TRACE_IRQS_IRETQ_DEBUG |
0d550836 | 988 | paranoid_exit_restore: |
76f5df43 DV |
989 | RESTORE_EXTRA_REGS |
990 | RESTORE_C_REGS | |
991 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
48e08d0f | 992 | INTERRUPT_RETURN |
ddeb8f21 AH |
993 | END(paranoid_exit) |
994 | ||
995 | /* | |
ebfc453e | 996 | * Save all registers in pt_regs, and switch gs if needed. |
539f5113 | 997 | * Return: EBX=0: came from user mode; EBX=1: otherwise |
ddeb8f21 AH |
998 | */ |
999 | ENTRY(error_entry) | |
ddeb8f21 | 1000 | cld |
76f5df43 DV |
1001 | SAVE_C_REGS 8 |
1002 | SAVE_EXTRA_REGS 8 | |
4d732138 | 1003 | xorl %ebx, %ebx |
03335e95 | 1004 | testb $3, CS+8(%rsp) |
cb6f64ed | 1005 | jz .Lerror_kernelspace |
539f5113 | 1006 | |
cb6f64ed AL |
1007 | .Lerror_entry_from_usermode_swapgs: |
1008 | /* | |
1009 | * We entered from user mode or we're pretending to have entered | |
1010 | * from user mode due to an IRET fault. | |
1011 | */ | |
ddeb8f21 | 1012 | SWAPGS |
539f5113 | 1013 | |
cb6f64ed | 1014 | .Lerror_entry_from_usermode_after_swapgs: |
f1075053 AL |
1015 | /* |
1016 | * We need to tell lockdep that IRQs are off. We can't do this until | |
1017 | * we fix gsbase, and we should do it before enter_from_user_mode | |
1018 | * (which can take locks). | |
1019 | */ | |
1020 | TRACE_IRQS_OFF | |
478dc89c | 1021 | CALL_enter_from_user_mode |
f1075053 | 1022 | ret |
02bc7768 | 1023 | |
cb6f64ed | 1024 | .Lerror_entry_done: |
ddeb8f21 AH |
1025 | TRACE_IRQS_OFF |
1026 | ret | |
ddeb8f21 | 1027 | |
ebfc453e DV |
1028 | /* |
1029 | * There are two places in the kernel that can potentially fault with | |
1030 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1031 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1032 | * for these here too. | |
1033 | */ | |
cb6f64ed | 1034 | .Lerror_kernelspace: |
4d732138 IM |
1035 | incl %ebx |
1036 | leaq native_irq_return_iret(%rip), %rcx | |
1037 | cmpq %rcx, RIP+8(%rsp) | |
cb6f64ed | 1038 | je .Lerror_bad_iret |
4d732138 IM |
1039 | movl %ecx, %eax /* zero extend */ |
1040 | cmpq %rax, RIP+8(%rsp) | |
cb6f64ed | 1041 | je .Lbstep_iret |
4d732138 | 1042 | cmpq $gs_change, RIP+8(%rsp) |
cb6f64ed | 1043 | jne .Lerror_entry_done |
539f5113 AL |
1044 | |
1045 | /* | |
1046 | * hack: gs_change can fail with user gsbase. If this happens, fix up | |
1047 | * gsbase and proceed. We'll fix up the exception and land in | |
1048 | * gs_change's error handler with kernel gsbase. | |
1049 | */ | |
cb6f64ed | 1050 | jmp .Lerror_entry_from_usermode_swapgs |
ae24ffe5 | 1051 | |
cb6f64ed | 1052 | .Lbstep_iret: |
ae24ffe5 | 1053 | /* Fix truncated RIP */ |
4d732138 | 1054 | movq %rcx, RIP+8(%rsp) |
b645af2d AL |
1055 | /* fall through */ |
1056 | ||
cb6f64ed | 1057 | .Lerror_bad_iret: |
539f5113 AL |
1058 | /* |
1059 | * We came from an IRET to user mode, so we have user gsbase. | |
1060 | * Switch to kernel gsbase: | |
1061 | */ | |
b645af2d | 1062 | SWAPGS |
539f5113 AL |
1063 | |
1064 | /* | |
1065 | * Pretend that the exception came from user mode: set up pt_regs | |
1066 | * as if we faulted immediately after IRET and clear EBX so that | |
1067 | * error_exit knows that we will be returning to user mode. | |
1068 | */ | |
4d732138 IM |
1069 | mov %rsp, %rdi |
1070 | call fixup_bad_iret | |
1071 | mov %rax, %rsp | |
539f5113 | 1072 | decl %ebx |
cb6f64ed | 1073 | jmp .Lerror_entry_from_usermode_after_swapgs |
ddeb8f21 AH |
1074 | END(error_entry) |
1075 | ||
1076 | ||
539f5113 AL |
1077 | /* |
1078 | * On entry, EBS is a "return to kernel mode" flag: | |
1079 | * 1: already in kernel mode, don't need SWAPGS | |
1080 | * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode | |
1081 | */ | |
ddeb8f21 | 1082 | ENTRY(error_exit) |
4d732138 | 1083 | movl %ebx, %eax |
ddeb8f21 AH |
1084 | DISABLE_INTERRUPTS(CLBR_NONE) |
1085 | TRACE_IRQS_OFF | |
4d732138 IM |
1086 | testl %eax, %eax |
1087 | jnz retint_kernel | |
1088 | jmp retint_user | |
ddeb8f21 AH |
1089 | END(error_exit) |
1090 | ||
0784b364 | 1091 | /* Runs on exception stack */ |
ddeb8f21 | 1092 | ENTRY(nmi) |
fc57a7c6 AL |
1093 | /* |
1094 | * Fix up the exception frame if we're on Xen. | |
1095 | * PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most | |
1096 | * one value to the stack on native, so it may clobber the rdx | |
1097 | * scratch slot, but it won't clobber any of the important | |
1098 | * slots past it. | |
1099 | * | |
1100 | * Xen is a different story, because the Xen frame itself overlaps | |
1101 | * the "NMI executing" variable. | |
1102 | */ | |
ddeb8f21 | 1103 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
fc57a7c6 | 1104 | |
3f3c8b8c SR |
1105 | /* |
1106 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1107 | * the iretq it performs will take us out of NMI context. | |
1108 | * This means that we can have nested NMIs where the next | |
1109 | * NMI is using the top of the stack of the previous NMI. We | |
1110 | * can't let it execute because the nested NMI will corrupt the | |
1111 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1112 | * anyway. | |
1113 | * | |
1114 | * To handle this case we do the following: | |
1115 | * Check the a special location on the stack that contains | |
1116 | * a variable that is set when NMIs are executing. | |
1117 | * The interrupted task's stack is also checked to see if it | |
1118 | * is an NMI stack. | |
1119 | * If the variable is not set and the stack is not the NMI | |
1120 | * stack then: | |
1121 | * o Set the special variable on the stack | |
0b22930e AL |
1122 | * o Copy the interrupt frame into an "outermost" location on the |
1123 | * stack | |
1124 | * o Copy the interrupt frame into an "iret" location on the stack | |
3f3c8b8c SR |
1125 | * o Continue processing the NMI |
1126 | * If the variable is set or the previous stack is the NMI stack: | |
0b22930e | 1127 | * o Modify the "iret" location to jump to the repeat_nmi |
3f3c8b8c SR |
1128 | * o return back to the first NMI |
1129 | * | |
1130 | * Now on exit of the first NMI, we first clear the stack variable | |
1131 | * The NMI stack will tell any nested NMIs at that point that it is | |
1132 | * nested. Then we pop the stack normally with iret, and if there was | |
1133 | * a nested NMI that updated the copy interrupt stack frame, a | |
1134 | * jump will be made to the repeat_nmi code that will handle the second | |
1135 | * NMI. | |
9b6e6a83 AL |
1136 | * |
1137 | * However, espfix prevents us from directly returning to userspace | |
1138 | * with a single IRET instruction. Similarly, IRET to user mode | |
1139 | * can fault. We therefore handle NMIs from user space like | |
1140 | * other IST entries. | |
3f3c8b8c SR |
1141 | */ |
1142 | ||
146b2b09 | 1143 | /* Use %rdx as our temp variable throughout */ |
4d732138 | 1144 | pushq %rdx |
3f3c8b8c | 1145 | |
9b6e6a83 AL |
1146 | testb $3, CS-RIP+8(%rsp) |
1147 | jz .Lnmi_from_kernel | |
1148 | ||
1149 | /* | |
1150 | * NMI from user mode. We need to run on the thread stack, but we | |
1151 | * can't go through the normal entry paths: NMIs are masked, and | |
1152 | * we don't want to enable interrupts, because then we'll end | |
1153 | * up in an awkward situation in which IRQs are on but NMIs | |
1154 | * are off. | |
83c133cf AL |
1155 | * |
1156 | * We also must not push anything to the stack before switching | |
1157 | * stacks lest we corrupt the "NMI executing" variable. | |
9b6e6a83 AL |
1158 | */ |
1159 | ||
83c133cf | 1160 | SWAPGS_UNSAFE_STACK |
9b6e6a83 AL |
1161 | cld |
1162 | movq %rsp, %rdx | |
1163 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
1164 | pushq 5*8(%rdx) /* pt_regs->ss */ | |
1165 | pushq 4*8(%rdx) /* pt_regs->rsp */ | |
1166 | pushq 3*8(%rdx) /* pt_regs->flags */ | |
1167 | pushq 2*8(%rdx) /* pt_regs->cs */ | |
1168 | pushq 1*8(%rdx) /* pt_regs->rip */ | |
1169 | pushq $-1 /* pt_regs->orig_ax */ | |
1170 | pushq %rdi /* pt_regs->di */ | |
1171 | pushq %rsi /* pt_regs->si */ | |
1172 | pushq (%rdx) /* pt_regs->dx */ | |
1173 | pushq %rcx /* pt_regs->cx */ | |
1174 | pushq %rax /* pt_regs->ax */ | |
1175 | pushq %r8 /* pt_regs->r8 */ | |
1176 | pushq %r9 /* pt_regs->r9 */ | |
1177 | pushq %r10 /* pt_regs->r10 */ | |
1178 | pushq %r11 /* pt_regs->r11 */ | |
1179 | pushq %rbx /* pt_regs->rbx */ | |
1180 | pushq %rbp /* pt_regs->rbp */ | |
1181 | pushq %r12 /* pt_regs->r12 */ | |
1182 | pushq %r13 /* pt_regs->r13 */ | |
1183 | pushq %r14 /* pt_regs->r14 */ | |
1184 | pushq %r15 /* pt_regs->r15 */ | |
1185 | ||
1186 | /* | |
1187 | * At this point we no longer need to worry about stack damage | |
1188 | * due to nesting -- we're on the normal thread stack and we're | |
1189 | * done with the NMI stack. | |
1190 | */ | |
1191 | ||
1192 | movq %rsp, %rdi | |
1193 | movq $-1, %rsi | |
1194 | call do_nmi | |
1195 | ||
45d5a168 | 1196 | /* |
9b6e6a83 AL |
1197 | * Return back to user mode. We must *not* do the normal exit |
1198 | * work, because we don't want to enable interrupts. Fortunately, | |
1199 | * do_nmi doesn't modify pt_regs. | |
45d5a168 | 1200 | */ |
9b6e6a83 AL |
1201 | SWAPGS |
1202 | jmp restore_c_regs_and_iret | |
45d5a168 | 1203 | |
9b6e6a83 | 1204 | .Lnmi_from_kernel: |
3f3c8b8c | 1205 | /* |
0b22930e AL |
1206 | * Here's what our stack frame will look like: |
1207 | * +---------------------------------------------------------+ | |
1208 | * | original SS | | |
1209 | * | original Return RSP | | |
1210 | * | original RFLAGS | | |
1211 | * | original CS | | |
1212 | * | original RIP | | |
1213 | * +---------------------------------------------------------+ | |
1214 | * | temp storage for rdx | | |
1215 | * +---------------------------------------------------------+ | |
1216 | * | "NMI executing" variable | | |
1217 | * +---------------------------------------------------------+ | |
1218 | * | iret SS } Copied from "outermost" frame | | |
1219 | * | iret Return RSP } on each loop iteration; overwritten | | |
1220 | * | iret RFLAGS } by a nested NMI to force another | | |
1221 | * | iret CS } iteration if needed. | | |
1222 | * | iret RIP } | | |
1223 | * +---------------------------------------------------------+ | |
1224 | * | outermost SS } initialized in first_nmi; | | |
1225 | * | outermost Return RSP } will not be changed before | | |
1226 | * | outermost RFLAGS } NMI processing is done. | | |
1227 | * | outermost CS } Copied to "iret" frame on each | | |
1228 | * | outermost RIP } iteration. | | |
1229 | * +---------------------------------------------------------+ | |
1230 | * | pt_regs | | |
1231 | * +---------------------------------------------------------+ | |
1232 | * | |
1233 | * The "original" frame is used by hardware. Before re-enabling | |
1234 | * NMIs, we need to be done with it, and we need to leave enough | |
1235 | * space for the asm code here. | |
1236 | * | |
1237 | * We return by executing IRET while RSP points to the "iret" frame. | |
1238 | * That will either return for real or it will loop back into NMI | |
1239 | * processing. | |
1240 | * | |
1241 | * The "outermost" frame is copied to the "iret" frame on each | |
1242 | * iteration of the loop, so each iteration starts with the "iret" | |
1243 | * frame pointing to the final return target. | |
1244 | */ | |
1245 | ||
45d5a168 | 1246 | /* |
0b22930e AL |
1247 | * Determine whether we're a nested NMI. |
1248 | * | |
a27507ca AL |
1249 | * If we interrupted kernel code between repeat_nmi and |
1250 | * end_repeat_nmi, then we are a nested NMI. We must not | |
1251 | * modify the "iret" frame because it's being written by | |
1252 | * the outer NMI. That's okay; the outer NMI handler is | |
1253 | * about to about to call do_nmi anyway, so we can just | |
1254 | * resume the outer NMI. | |
45d5a168 | 1255 | */ |
a27507ca AL |
1256 | |
1257 | movq $repeat_nmi, %rdx | |
1258 | cmpq 8(%rsp), %rdx | |
1259 | ja 1f | |
1260 | movq $end_repeat_nmi, %rdx | |
1261 | cmpq 8(%rsp), %rdx | |
1262 | ja nested_nmi_out | |
1263 | 1: | |
45d5a168 | 1264 | |
3f3c8b8c | 1265 | /* |
a27507ca | 1266 | * Now check "NMI executing". If it's set, then we're nested. |
0b22930e AL |
1267 | * This will not detect if we interrupted an outer NMI just |
1268 | * before IRET. | |
3f3c8b8c | 1269 | */ |
4d732138 IM |
1270 | cmpl $1, -8(%rsp) |
1271 | je nested_nmi | |
3f3c8b8c SR |
1272 | |
1273 | /* | |
0b22930e AL |
1274 | * Now test if the previous stack was an NMI stack. This covers |
1275 | * the case where we interrupt an outer NMI after it clears | |
810bc075 AL |
1276 | * "NMI executing" but before IRET. We need to be careful, though: |
1277 | * there is one case in which RSP could point to the NMI stack | |
1278 | * despite there being no NMI active: naughty userspace controls | |
1279 | * RSP at the very beginning of the SYSCALL targets. We can | |
1280 | * pull a fast one on naughty userspace, though: we program | |
1281 | * SYSCALL to mask DF, so userspace cannot cause DF to be set | |
1282 | * if it controls the kernel's RSP. We set DF before we clear | |
1283 | * "NMI executing". | |
3f3c8b8c | 1284 | */ |
0784b364 DV |
1285 | lea 6*8(%rsp), %rdx |
1286 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1287 | cmpq %rdx, 4*8(%rsp) | |
1288 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1289 | ja first_nmi | |
4d732138 | 1290 | |
0784b364 DV |
1291 | subq $EXCEPTION_STKSZ, %rdx |
1292 | cmpq %rdx, 4*8(%rsp) | |
1293 | /* If it is below the NMI stack, it is a normal NMI */ | |
1294 | jb first_nmi | |
810bc075 AL |
1295 | |
1296 | /* Ah, it is within the NMI stack. */ | |
1297 | ||
1298 | testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) | |
1299 | jz first_nmi /* RSP was user controlled. */ | |
1300 | ||
1301 | /* This is a nested NMI. */ | |
0784b364 | 1302 | |
3f3c8b8c SR |
1303 | nested_nmi: |
1304 | /* | |
0b22930e AL |
1305 | * Modify the "iret" frame to point to repeat_nmi, forcing another |
1306 | * iteration of NMI handling. | |
3f3c8b8c | 1307 | */ |
23a781e9 | 1308 | subq $8, %rsp |
4d732138 IM |
1309 | leaq -10*8(%rsp), %rdx |
1310 | pushq $__KERNEL_DS | |
1311 | pushq %rdx | |
131484c8 | 1312 | pushfq |
4d732138 IM |
1313 | pushq $__KERNEL_CS |
1314 | pushq $repeat_nmi | |
3f3c8b8c SR |
1315 | |
1316 | /* Put stack back */ | |
4d732138 | 1317 | addq $(6*8), %rsp |
3f3c8b8c SR |
1318 | |
1319 | nested_nmi_out: | |
4d732138 | 1320 | popq %rdx |
3f3c8b8c | 1321 | |
0b22930e | 1322 | /* We are returning to kernel mode, so this cannot result in a fault. */ |
3f3c8b8c SR |
1323 | INTERRUPT_RETURN |
1324 | ||
1325 | first_nmi: | |
0b22930e | 1326 | /* Restore rdx. */ |
4d732138 | 1327 | movq (%rsp), %rdx |
62610913 | 1328 | |
36f1a77b AL |
1329 | /* Make room for "NMI executing". */ |
1330 | pushq $0 | |
3f3c8b8c | 1331 | |
0b22930e | 1332 | /* Leave room for the "iret" frame */ |
4d732138 | 1333 | subq $(5*8), %rsp |
28696f43 | 1334 | |
0b22930e | 1335 | /* Copy the "original" frame to the "outermost" frame */ |
3f3c8b8c | 1336 | .rept 5 |
4d732138 | 1337 | pushq 11*8(%rsp) |
3f3c8b8c | 1338 | .endr |
62610913 | 1339 | |
79fb4ad6 SR |
1340 | /* Everything up to here is safe from nested NMIs */ |
1341 | ||
a97439aa AL |
1342 | #ifdef CONFIG_DEBUG_ENTRY |
1343 | /* | |
1344 | * For ease of testing, unmask NMIs right away. Disabled by | |
1345 | * default because IRET is very expensive. | |
1346 | */ | |
1347 | pushq $0 /* SS */ | |
1348 | pushq %rsp /* RSP (minus 8 because of the previous push) */ | |
1349 | addq $8, (%rsp) /* Fix up RSP */ | |
1350 | pushfq /* RFLAGS */ | |
1351 | pushq $__KERNEL_CS /* CS */ | |
1352 | pushq $1f /* RIP */ | |
1353 | INTERRUPT_RETURN /* continues at repeat_nmi below */ | |
1354 | 1: | |
1355 | #endif | |
1356 | ||
0b22930e | 1357 | repeat_nmi: |
62610913 JB |
1358 | /* |
1359 | * If there was a nested NMI, the first NMI's iret will return | |
1360 | * here. But NMIs are still enabled and we can take another | |
1361 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1362 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1363 | * it will just return, as we are about to repeat an NMI anyway. | |
1364 | * This makes it safe to copy to the stack frame that a nested | |
1365 | * NMI will update. | |
0b22930e AL |
1366 | * |
1367 | * RSP is pointing to "outermost RIP". gsbase is unknown, but, if | |
1368 | * we're repeating an NMI, gsbase has the same value that it had on | |
1369 | * the first iteration. paranoid_entry will load the kernel | |
36f1a77b AL |
1370 | * gsbase if needed before we call do_nmi. "NMI executing" |
1371 | * is zero. | |
62610913 | 1372 | */ |
36f1a77b | 1373 | movq $1, 10*8(%rsp) /* Set "NMI executing". */ |
3f3c8b8c | 1374 | |
62610913 | 1375 | /* |
0b22930e AL |
1376 | * Copy the "outermost" frame to the "iret" frame. NMIs that nest |
1377 | * here must not modify the "iret" frame while we're writing to | |
1378 | * it or it will end up containing garbage. | |
62610913 | 1379 | */ |
4d732138 | 1380 | addq $(10*8), %rsp |
3f3c8b8c | 1381 | .rept 5 |
4d732138 | 1382 | pushq -6*8(%rsp) |
3f3c8b8c | 1383 | .endr |
4d732138 | 1384 | subq $(5*8), %rsp |
62610913 | 1385 | end_repeat_nmi: |
3f3c8b8c SR |
1386 | |
1387 | /* | |
0b22930e AL |
1388 | * Everything below this point can be preempted by a nested NMI. |
1389 | * If this happens, then the inner NMI will change the "iret" | |
1390 | * frame to point back to repeat_nmi. | |
3f3c8b8c | 1391 | */ |
4d732138 | 1392 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 DV |
1393 | ALLOC_PT_GPREGS_ON_STACK |
1394 | ||
1fd466ef | 1395 | /* |
ebfc453e | 1396 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1397 | * as we should not be calling schedule in NMI context. |
1398 | * Even with normal interrupts enabled. An NMI should not be | |
1399 | * setting NEED_RESCHED or anything that normal interrupts and | |
1400 | * exceptions might do. | |
1401 | */ | |
4d732138 | 1402 | call paranoid_entry |
7fbb98c5 | 1403 | |
ddeb8f21 | 1404 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
4d732138 IM |
1405 | movq %rsp, %rdi |
1406 | movq $-1, %rsi | |
1407 | call do_nmi | |
7fbb98c5 | 1408 | |
4d732138 IM |
1409 | testl %ebx, %ebx /* swapgs needed? */ |
1410 | jnz nmi_restore | |
ddeb8f21 AH |
1411 | nmi_swapgs: |
1412 | SWAPGS_UNSAFE_STACK | |
1413 | nmi_restore: | |
76f5df43 DV |
1414 | RESTORE_EXTRA_REGS |
1415 | RESTORE_C_REGS | |
0b22930e AL |
1416 | |
1417 | /* Point RSP at the "iret" frame. */ | |
76f5df43 | 1418 | REMOVE_PT_GPREGS_FROM_STACK 6*8 |
28696f43 | 1419 | |
810bc075 AL |
1420 | /* |
1421 | * Clear "NMI executing". Set DF first so that we can easily | |
1422 | * distinguish the remaining code between here and IRET from | |
1423 | * the SYSCALL entry and exit paths. On a native kernel, we | |
1424 | * could just inspect RIP, but, on paravirt kernels, | |
1425 | * INTERRUPT_RETURN can translate into a jump into a | |
1426 | * hypercall page. | |
1427 | */ | |
1428 | std | |
1429 | movq $0, 5*8(%rsp) /* clear "NMI executing" */ | |
0b22930e AL |
1430 | |
1431 | /* | |
1432 | * INTERRUPT_RETURN reads the "iret" frame and exits the NMI | |
1433 | * stack in a single instruction. We are returning to kernel | |
1434 | * mode, so this cannot result in a fault. | |
1435 | */ | |
5ca6f70f | 1436 | INTERRUPT_RETURN |
ddeb8f21 AH |
1437 | END(nmi) |
1438 | ||
1439 | ENTRY(ignore_sysret) | |
4d732138 | 1440 | mov $-ENOSYS, %eax |
ddeb8f21 | 1441 | sysret |
ddeb8f21 | 1442 | END(ignore_sysret) |