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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/entry.S | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
4d732138 | 7 | * |
1da177e4 LT |
8 | * entry.S contains the system-call and fault low-level handling routines. |
9 | * | |
8b4777a4 AL |
10 | * Some of this is documented in Documentation/x86/entry_64.txt |
11 | * | |
0bd7b798 | 12 | * A note on terminology: |
4d732138 IM |
13 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
14 | * at the top of the kernel process stack. | |
2e91a17b AK |
15 | * |
16 | * Some macro usage: | |
4d732138 IM |
17 | * - ENTRY/END: Define functions in the symbol table. |
18 | * - TRACE_IRQ_*: Trace hardirq state for lock debugging. | |
19 | * - idtentry: Define exception entry points. | |
1da177e4 | 20 | */ |
1da177e4 LT |
21 | #include <linux/linkage.h> |
22 | #include <asm/segment.h> | |
1da177e4 LT |
23 | #include <asm/cache.h> |
24 | #include <asm/errno.h> | |
d36f9479 | 25 | #include "calling.h" |
e2d5df93 | 26 | #include <asm/asm-offsets.h> |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/unistd.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/hw_irq.h> | |
0341c14d | 31 | #include <asm/page_types.h> |
2601e64d | 32 | #include <asm/irqflags.h> |
72fe4858 | 33 | #include <asm/paravirt.h> |
9939ddaf | 34 | #include <asm/percpu.h> |
d7abc0fa | 35 | #include <asm/asm.h> |
63bcff2a | 36 | #include <asm/smap.h> |
3891a04a | 37 | #include <asm/pgtable_types.h> |
d7e7528b | 38 | #include <linux/err.h> |
1da177e4 | 39 | |
86a1c34a RM |
40 | /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ |
41 | #include <linux/elf-em.h> | |
4d732138 IM |
42 | #define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) |
43 | #define __AUDIT_ARCH_64BIT 0x80000000 | |
44 | #define __AUDIT_ARCH_LE 0x40000000 | |
ea714547 | 45 | |
4d732138 IM |
46 | .code64 |
47 | .section .entry.text, "ax" | |
16444a8a | 48 | |
72fe4858 | 49 | #ifdef CONFIG_PARAVIRT |
2be29982 | 50 | ENTRY(native_usergs_sysret64) |
72fe4858 GOC |
51 | swapgs |
52 | sysretq | |
b3baaa13 | 53 | ENDPROC(native_usergs_sysret64) |
72fe4858 GOC |
54 | #endif /* CONFIG_PARAVIRT */ |
55 | ||
f2db9382 | 56 | .macro TRACE_IRQS_IRETQ |
2601e64d | 57 | #ifdef CONFIG_TRACE_IRQFLAGS |
4d732138 IM |
58 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
59 | jnc 1f | |
2601e64d IM |
60 | TRACE_IRQS_ON |
61 | 1: | |
62 | #endif | |
63 | .endm | |
64 | ||
5963e317 SR |
65 | /* |
66 | * When dynamic function tracer is enabled it will add a breakpoint | |
67 | * to all locations that it is about to modify, sync CPUs, update | |
68 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
69 | * if lockdep is enabled, it might jump back into the debug handler | |
70 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
71 | * | |
72 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
73 | * make sure the stack pointer does not get reset back to the top | |
74 | * of the debug stack, and instead just reuses the current stack. | |
75 | */ | |
76 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
77 | ||
78 | .macro TRACE_IRQS_OFF_DEBUG | |
4d732138 | 79 | call debug_stack_set_zero |
5963e317 | 80 | TRACE_IRQS_OFF |
4d732138 | 81 | call debug_stack_reset |
5963e317 SR |
82 | .endm |
83 | ||
84 | .macro TRACE_IRQS_ON_DEBUG | |
4d732138 | 85 | call debug_stack_set_zero |
5963e317 | 86 | TRACE_IRQS_ON |
4d732138 | 87 | call debug_stack_reset |
5963e317 SR |
88 | .endm |
89 | ||
f2db9382 | 90 | .macro TRACE_IRQS_IRETQ_DEBUG |
4d732138 IM |
91 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
92 | jnc 1f | |
5963e317 SR |
93 | TRACE_IRQS_ON_DEBUG |
94 | 1: | |
95 | .endm | |
96 | ||
97 | #else | |
4d732138 IM |
98 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF |
99 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
100 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
5963e317 SR |
101 | #endif |
102 | ||
1da177e4 | 103 | /* |
4d732138 | 104 | * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 105 | * |
4d732138 | 106 | * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
b87cf63e DV |
107 | * then loads new ss, cs, and rip from previously programmed MSRs. |
108 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
109 | * are not needed). SYSCALL does not save anything on the stack | |
110 | * and does not change rsp. | |
111 | * | |
112 | * Registers on entry: | |
1da177e4 | 113 | * rax system call number |
b87cf63e DV |
114 | * rcx return address |
115 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 116 | * rdi arg0 |
1da177e4 | 117 | * rsi arg1 |
0bd7b798 | 118 | * rdx arg2 |
b87cf63e | 119 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
120 | * r8 arg4 |
121 | * r9 arg5 | |
4d732138 | 122 | * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) |
0bd7b798 | 123 | * |
1da177e4 LT |
124 | * Only called from user space. |
125 | * | |
7fcb3bc3 | 126 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
127 | * it deals with uncanonical addresses better. SYSRET has trouble |
128 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 129 | */ |
1da177e4 | 130 | |
b2502b41 | 131 | ENTRY(entry_SYSCALL_64) |
9ed8e7d8 DV |
132 | /* |
133 | * Interrupts are off on entry. | |
134 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
135 | * it is too small to ever cause noticeable irq latency. | |
136 | */ | |
72fe4858 GOC |
137 | SWAPGS_UNSAFE_STACK |
138 | /* | |
139 | * A hypervisor implementation might want to use a label | |
140 | * after the swapgs, so that it can do the swapgs | |
141 | * for the guest and jump here on syscall. | |
142 | */ | |
b2502b41 | 143 | GLOBAL(entry_SYSCALL_64_after_swapgs) |
72fe4858 | 144 | |
4d732138 IM |
145 | movq %rsp, PER_CPU_VAR(rsp_scratch) |
146 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
9ed8e7d8 DV |
147 | |
148 | /* Construct struct pt_regs on stack */ | |
4d732138 IM |
149 | pushq $__USER_DS /* pt_regs->ss */ |
150 | pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
33db1fd4 | 151 | /* |
9ed8e7d8 DV |
152 | * Re-enable interrupts. |
153 | * We use 'rsp_scratch' as a scratch space, hence irq-off block above | |
154 | * must execute atomically in the face of possible interrupt-driven | |
155 | * task preemption. We must enable interrupts only after we're done | |
156 | * with using rsp_scratch: | |
33db1fd4 DV |
157 | */ |
158 | ENABLE_INTERRUPTS(CLBR_NONE) | |
4d732138 IM |
159 | pushq %r11 /* pt_regs->flags */ |
160 | pushq $__USER_CS /* pt_regs->cs */ | |
161 | pushq %rcx /* pt_regs->ip */ | |
162 | pushq %rax /* pt_regs->orig_ax */ | |
163 | pushq %rdi /* pt_regs->di */ | |
164 | pushq %rsi /* pt_regs->si */ | |
165 | pushq %rdx /* pt_regs->dx */ | |
166 | pushq %rcx /* pt_regs->cx */ | |
167 | pushq $-ENOSYS /* pt_regs->ax */ | |
168 | pushq %r8 /* pt_regs->r8 */ | |
169 | pushq %r9 /* pt_regs->r9 */ | |
170 | pushq %r10 /* pt_regs->r10 */ | |
171 | pushq %r11 /* pt_regs->r11 */ | |
172 | sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 not saved */ | |
173 | ||
174 | testl $_TIF_WORK_SYSCALL_ENTRY, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) | |
175 | jnz tracesys | |
b2502b41 | 176 | entry_SYSCALL_64_fastpath: |
fca460f9 | 177 | #if __SYSCALL_MASK == ~0 |
4d732138 | 178 | cmpq $__NR_syscall_max, %rax |
fca460f9 | 179 | #else |
4d732138 IM |
180 | andl $__SYSCALL_MASK, %eax |
181 | cmpl $__NR_syscall_max, %eax | |
fca460f9 | 182 | #endif |
4d732138 IM |
183 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
184 | movq %r10, %rcx | |
185 | call *sys_call_table(, %rax, 8) | |
186 | movq %rax, RAX(%rsp) | |
146b2b09 | 187 | 1: |
1da177e4 | 188 | /* |
146b2b09 DV |
189 | * Syscall return path ending with SYSRET (fast path). |
190 | * Has incompletely filled pt_regs. | |
0bd7b798 | 191 | */ |
10cd706d | 192 | LOCKDEP_SYS_EXIT |
4416c5a6 DV |
193 | /* |
194 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
195 | * it is too small to ever cause noticeable irq latency. | |
196 | */ | |
72fe4858 | 197 | DISABLE_INTERRUPTS(CLBR_NONE) |
b3494a4a AL |
198 | |
199 | /* | |
200 | * We must check ti flags with interrupts (or at least preemption) | |
201 | * off because we must *never* return to userspace without | |
202 | * processing exit work that is enqueued if we're preempted here. | |
203 | * In particular, returning to userspace with any of the one-shot | |
204 | * flags (TIF_NOTIFY_RESUME, TIF_USER_RETURN_NOTIFY, etc) set is | |
205 | * very bad. | |
206 | */ | |
4d732138 IM |
207 | testl $_TIF_ALLWORK_MASK, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) |
208 | jnz int_ret_from_sys_call_irqs_off /* Go to the slow path */ | |
b3494a4a | 209 | |
29722cd4 | 210 | RESTORE_C_REGS_EXCEPT_RCX_R11 |
4d732138 IM |
211 | movq RIP(%rsp), %rcx |
212 | movq EFLAGS(%rsp), %r11 | |
213 | movq RSP(%rsp), %rsp | |
b87cf63e | 214 | /* |
4d732138 | 215 | * 64-bit SYSRET restores rip from rcx, |
b87cf63e DV |
216 | * rflags from r11 (but RF and VM bits are forced to 0), |
217 | * cs and ss are loaded from MSRs. | |
4416c5a6 | 218 | * Restoration of rflags re-enables interrupts. |
61f01dd9 AL |
219 | * |
220 | * NB: On AMD CPUs with the X86_BUG_SYSRET_SS_ATTRS bug, the ss | |
221 | * descriptor is not reinitialized. This means that we should | |
222 | * avoid SYSRET with SS == NULL, which could happen if we schedule, | |
223 | * exit the kernel, and re-enter using an interrupt vector. (All | |
224 | * interrupt entries on x86_64 set SS to NULL.) We prevent that | |
225 | * from happening by reloading SS in __switch_to. (Actually | |
226 | * detecting the failure in 64-bit userspace is tricky but can be | |
227 | * done.) | |
b87cf63e | 228 | */ |
2be29982 | 229 | USERGS_SYSRET64 |
1da177e4 | 230 | |
29ea1b25 AL |
231 | GLOBAL(int_ret_from_sys_call_irqs_off) |
232 | TRACE_IRQS_ON | |
233 | ENABLE_INTERRUPTS(CLBR_NONE) | |
234 | jmp int_ret_from_sys_call | |
235 | ||
7fcb3bc3 | 236 | /* Do syscall entry tracing */ |
0bd7b798 | 237 | tracesys: |
4d732138 IM |
238 | movq %rsp, %rdi |
239 | movl $AUDIT_ARCH_X86_64, %esi | |
240 | call syscall_trace_enter_phase1 | |
241 | test %rax, %rax | |
242 | jnz tracesys_phase2 /* if needed, run the slow path */ | |
243 | RESTORE_C_REGS_EXCEPT_RAX /* else restore clobbered regs */ | |
244 | movq ORIG_RAX(%rsp), %rax | |
245 | jmp entry_SYSCALL_64_fastpath /* and return to the fast path */ | |
1dcf74f6 AL |
246 | |
247 | tracesys_phase2: | |
76f5df43 | 248 | SAVE_EXTRA_REGS |
4d732138 IM |
249 | movq %rsp, %rdi |
250 | movl $AUDIT_ARCH_X86_64, %esi | |
251 | movq %rax, %rdx | |
252 | call syscall_trace_enter_phase2 | |
1dcf74f6 | 253 | |
d4d67150 | 254 | /* |
e90e147c | 255 | * Reload registers from stack in case ptrace changed them. |
1dcf74f6 | 256 | * We don't reload %rax because syscall_trace_entry_phase2() returned |
d4d67150 RM |
257 | * the value it wants us to use in the table lookup. |
258 | */ | |
76f5df43 DV |
259 | RESTORE_C_REGS_EXCEPT_RAX |
260 | RESTORE_EXTRA_REGS | |
fca460f9 | 261 | #if __SYSCALL_MASK == ~0 |
4d732138 | 262 | cmpq $__NR_syscall_max, %rax |
fca460f9 | 263 | #else |
4d732138 IM |
264 | andl $__SYSCALL_MASK, %eax |
265 | cmpl $__NR_syscall_max, %eax | |
fca460f9 | 266 | #endif |
4d732138 IM |
267 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
268 | movq %r10, %rcx /* fixup for C */ | |
269 | call *sys_call_table(, %rax, 8) | |
270 | movq %rax, RAX(%rsp) | |
a6de5a21 | 271 | 1: |
7fcb3bc3 | 272 | /* Use IRET because user could have changed pt_regs->foo */ |
0bd7b798 AH |
273 | |
274 | /* | |
1da177e4 | 275 | * Syscall return path ending with IRET. |
7fcb3bc3 | 276 | * Has correct iret frame. |
bcddc015 | 277 | */ |
bc8b2b92 | 278 | GLOBAL(int_ret_from_sys_call) |
76f5df43 | 279 | SAVE_EXTRA_REGS |
29ea1b25 AL |
280 | movq %rsp, %rdi |
281 | call syscall_return_slowpath /* returns with IRQs disabled */ | |
76f5df43 | 282 | RESTORE_EXTRA_REGS |
29ea1b25 | 283 | TRACE_IRQS_IRETQ /* we're about to change IF */ |
fffbb5dc DV |
284 | |
285 | /* | |
286 | * Try to use SYSRET instead of IRET if we're returning to | |
287 | * a completely clean 64-bit userspace context. | |
288 | */ | |
4d732138 IM |
289 | movq RCX(%rsp), %rcx |
290 | movq RIP(%rsp), %r11 | |
291 | cmpq %rcx, %r11 /* RCX == RIP */ | |
292 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
293 | |
294 | /* | |
295 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
296 | * in kernel space. This essentially lets the user take over | |
17be0aec | 297 | * the kernel, since userspace controls RSP. |
fffbb5dc | 298 | * |
17be0aec | 299 | * If width of "canonical tail" ever becomes variable, this will need |
fffbb5dc DV |
300 | * to be updated to remain correct on both old and new CPUs. |
301 | */ | |
302 | .ifne __VIRTUAL_MASK_SHIFT - 47 | |
303 | .error "virtual address width changed -- SYSRET checks need update" | |
304 | .endif | |
4d732138 | 305 | |
17be0aec DV |
306 | /* Change top 16 bits to be the sign-extension of 47th bit */ |
307 | shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
308 | sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
4d732138 | 309 | |
17be0aec DV |
310 | /* If this changed %rcx, it was not canonical */ |
311 | cmpq %rcx, %r11 | |
312 | jne opportunistic_sysret_failed | |
fffbb5dc | 313 | |
4d732138 IM |
314 | cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ |
315 | jne opportunistic_sysret_failed | |
fffbb5dc | 316 | |
4d732138 IM |
317 | movq R11(%rsp), %r11 |
318 | cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ | |
319 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
320 | |
321 | /* | |
322 | * SYSRET can't restore RF. SYSRET can restore TF, but unlike IRET, | |
323 | * restoring TF results in a trap from userspace immediately after | |
324 | * SYSRET. This would cause an infinite loop whenever #DB happens | |
325 | * with register state that satisfies the opportunistic SYSRET | |
326 | * conditions. For example, single-stepping this user code: | |
327 | * | |
4d732138 | 328 | * movq $stuck_here, %rcx |
fffbb5dc DV |
329 | * pushfq |
330 | * popq %r11 | |
331 | * stuck_here: | |
332 | * | |
333 | * would never get past 'stuck_here'. | |
334 | */ | |
4d732138 IM |
335 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 |
336 | jnz opportunistic_sysret_failed | |
fffbb5dc DV |
337 | |
338 | /* nothing to check for RSP */ | |
339 | ||
4d732138 IM |
340 | cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ |
341 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
342 | |
343 | /* | |
4d732138 IM |
344 | * We win! This label is here just for ease of understanding |
345 | * perf profiles. Nothing jumps here. | |
fffbb5dc DV |
346 | */ |
347 | syscall_return_via_sysret: | |
17be0aec DV |
348 | /* rcx and r11 are already restored (see code above) */ |
349 | RESTORE_C_REGS_EXCEPT_RCX_R11 | |
4d732138 | 350 | movq RSP(%rsp), %rsp |
fffbb5dc | 351 | USERGS_SYSRET64 |
fffbb5dc DV |
352 | |
353 | opportunistic_sysret_failed: | |
354 | SWAPGS | |
355 | jmp restore_c_regs_and_iret | |
b2502b41 | 356 | END(entry_SYSCALL_64) |
0bd7b798 | 357 | |
fffbb5dc | 358 | |
1d4b4b29 AV |
359 | .macro FORK_LIKE func |
360 | ENTRY(stub_\func) | |
76f5df43 | 361 | SAVE_EXTRA_REGS 8 |
4d732138 | 362 | jmp sys_\func |
1d4b4b29 AV |
363 | END(stub_\func) |
364 | .endm | |
365 | ||
366 | FORK_LIKE clone | |
367 | FORK_LIKE fork | |
368 | FORK_LIKE vfork | |
1da177e4 | 369 | |
1da177e4 | 370 | ENTRY(stub_execve) |
fc3e958a DV |
371 | call sys_execve |
372 | return_from_execve: | |
373 | testl %eax, %eax | |
374 | jz 1f | |
375 | /* exec failed, can use fast SYSRET code path in this case */ | |
376 | ret | |
377 | 1: | |
378 | /* must use IRET code path (pt_regs->cs may have changed) */ | |
379 | addq $8, %rsp | |
380 | ZERO_EXTRA_REGS | |
4d732138 | 381 | movq %rax, RAX(%rsp) |
fc3e958a | 382 | jmp int_ret_from_sys_call |
4b787e0b | 383 | END(stub_execve) |
a37f34a3 DV |
384 | /* |
385 | * Remaining execve stubs are only 7 bytes long. | |
386 | * ENTRY() often aligns to 16 bytes, which in this case has no benefits. | |
387 | */ | |
388 | .align 8 | |
389 | GLOBAL(stub_execveat) | |
fc3e958a DV |
390 | call sys_execveat |
391 | jmp return_from_execve | |
27d6ec7a DD |
392 | END(stub_execveat) |
393 | ||
8169aff6 | 394 | #if defined(CONFIG_X86_X32_ABI) |
a37f34a3 DV |
395 | .align 8 |
396 | GLOBAL(stub_x32_execve) | |
05f1752d DV |
397 | call compat_sys_execve |
398 | jmp return_from_execve | |
05f1752d | 399 | END(stub_x32_execve) |
a37f34a3 DV |
400 | .align 8 |
401 | GLOBAL(stub_x32_execveat) | |
0f90fb97 DV |
402 | call compat_sys_execveat |
403 | jmp return_from_execve | |
ac7f5dfb | 404 | END(stub_x32_execveat) |
0f90fb97 DV |
405 | #endif |
406 | ||
1da177e4 LT |
407 | /* |
408 | * sigreturn is special because it needs to restore all registers on return. | |
409 | * This cannot be done with SYSRET, so use the IRET return path instead. | |
0bd7b798 | 410 | */ |
1da177e4 | 411 | ENTRY(stub_rt_sigreturn) |
31f0119b DV |
412 | /* |
413 | * SAVE_EXTRA_REGS result is not normally needed: | |
414 | * sigreturn overwrites all pt_regs->GPREGS. | |
415 | * But sigreturn can fail (!), and there is no easy way to detect that. | |
416 | * To make sure RESTORE_EXTRA_REGS doesn't restore garbage on error, | |
417 | * we SAVE_EXTRA_REGS here. | |
418 | */ | |
419 | SAVE_EXTRA_REGS 8 | |
4d732138 | 420 | call sys_rt_sigreturn |
31f0119b DV |
421 | return_from_stub: |
422 | addq $8, %rsp | |
76f5df43 | 423 | RESTORE_EXTRA_REGS |
4d732138 IM |
424 | movq %rax, RAX(%rsp) |
425 | jmp int_ret_from_sys_call | |
4b787e0b | 426 | END(stub_rt_sigreturn) |
1da177e4 | 427 | |
c5a37394 | 428 | #ifdef CONFIG_X86_X32_ABI |
c5a37394 | 429 | ENTRY(stub_x32_rt_sigreturn) |
31f0119b | 430 | SAVE_EXTRA_REGS 8 |
4d732138 IM |
431 | call sys32_x32_rt_sigreturn |
432 | jmp return_from_stub | |
c5a37394 | 433 | END(stub_x32_rt_sigreturn) |
c5a37394 PA |
434 | #endif |
435 | ||
1eeb207f DV |
436 | /* |
437 | * A newly forked process directly context switches into this address. | |
438 | * | |
439 | * rdi: prev task we switched from | |
440 | */ | |
441 | ENTRY(ret_from_fork) | |
1eeb207f | 442 | |
4d732138 | 443 | LOCK ; btr $TIF_FORK, TI_flags(%r8) |
1eeb207f | 444 | |
4d732138 IM |
445 | pushq $0x0002 |
446 | popfq /* reset kernel eflags */ | |
1eeb207f | 447 | |
4d732138 | 448 | call schedule_tail /* rdi: 'prev' task parameter */ |
1eeb207f | 449 | |
1eeb207f DV |
450 | RESTORE_EXTRA_REGS |
451 | ||
4d732138 | 452 | testb $3, CS(%rsp) /* from kernel_thread? */ |
1eeb207f | 453 | |
1e3fbb8a AL |
454 | /* |
455 | * By the time we get here, we have no idea whether our pt_regs, | |
456 | * ti flags, and ti status came from the 64-bit SYSCALL fast path, | |
138bd56a | 457 | * the slow path, or one of the 32-bit compat paths. |
66ad4efa | 458 | * Use IRET code path to return, since it can safely handle |
1e3fbb8a AL |
459 | * all of the above. |
460 | */ | |
66ad4efa | 461 | jnz int_ret_from_sys_call |
1eeb207f | 462 | |
4d732138 IM |
463 | /* |
464 | * We came from kernel_thread | |
465 | * nb: we depend on RESTORE_EXTRA_REGS above | |
466 | */ | |
467 | movq %rbp, %rdi | |
468 | call *%rbx | |
469 | movl $0, RAX(%rsp) | |
1eeb207f | 470 | RESTORE_EXTRA_REGS |
4d732138 | 471 | jmp int_ret_from_sys_call |
1eeb207f DV |
472 | END(ret_from_fork) |
473 | ||
939b7871 | 474 | /* |
3304c9c3 DV |
475 | * Build the entry stubs with some assembler magic. |
476 | * We pack 1 stub into every 8-byte block. | |
939b7871 | 477 | */ |
3304c9c3 | 478 | .align 8 |
939b7871 | 479 | ENTRY(irq_entries_start) |
3304c9c3 DV |
480 | vector=FIRST_EXTERNAL_VECTOR |
481 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
4d732138 | 482 | pushq $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
483 | vector=vector+1 |
484 | jmp common_interrupt | |
3304c9c3 DV |
485 | .align 8 |
486 | .endr | |
939b7871 PA |
487 | END(irq_entries_start) |
488 | ||
d99015b1 | 489 | /* |
1da177e4 LT |
490 | * Interrupt entry/exit. |
491 | * | |
492 | * Interrupt entry points save only callee clobbered registers in fast path. | |
d99015b1 AH |
493 | * |
494 | * Entry runs with interrupts off. | |
495 | */ | |
1da177e4 | 496 | |
722024db | 497 | /* 0(%rsp): ~(interrupt number) */ |
1da177e4 | 498 | .macro interrupt func |
f6f64681 | 499 | cld |
ff467594 AL |
500 | ALLOC_PT_GPREGS_ON_STACK |
501 | SAVE_C_REGS | |
502 | SAVE_EXTRA_REGS | |
76f5df43 | 503 | |
ff467594 | 504 | testb $3, CS(%rsp) |
dde74f2e | 505 | jz 1f |
02bc7768 AL |
506 | |
507 | /* | |
508 | * IRQ from user mode. Switch to kernel gsbase and inform context | |
509 | * tracking that we're in kernel mode. | |
510 | */ | |
f6f64681 | 511 | SWAPGS |
02bc7768 AL |
512 | #ifdef CONFIG_CONTEXT_TRACKING |
513 | call enter_from_user_mode | |
514 | #endif | |
515 | ||
76f5df43 | 516 | 1: |
f6f64681 | 517 | /* |
e90e147c | 518 | * Save previous stack pointer, optionally switch to interrupt stack. |
f6f64681 DV |
519 | * irq_count is used to check if a CPU is already on an interrupt stack |
520 | * or not. While this is essentially redundant with preempt_count it is | |
521 | * a little cheaper to use a separate counter in the PDA (short of | |
522 | * moving irq_enter into assembly, which would be too much work) | |
523 | */ | |
a586f98e | 524 | movq %rsp, %rdi |
4d732138 IM |
525 | incl PER_CPU_VAR(irq_count) |
526 | cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp | |
a586f98e | 527 | pushq %rdi |
f6f64681 DV |
528 | /* We entered an interrupt context - irqs are off: */ |
529 | TRACE_IRQS_OFF | |
530 | ||
a586f98e | 531 | call \func /* rdi points to pt_regs */ |
1da177e4 LT |
532 | .endm |
533 | ||
722024db AH |
534 | /* |
535 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
536 | * then jump to common_interrupt. | |
537 | */ | |
939b7871 PA |
538 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
539 | common_interrupt: | |
ee4eb87b | 540 | ASM_CLAC |
4d732138 | 541 | addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ |
1da177e4 | 542 | interrupt do_IRQ |
34061f13 | 543 | /* 0(%rsp): old RSP */ |
7effaa88 | 544 | ret_from_intr: |
72fe4858 | 545 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 546 | TRACE_IRQS_OFF |
4d732138 | 547 | decl PER_CPU_VAR(irq_count) |
625dbc3b | 548 | |
a2bbe750 | 549 | /* Restore saved previous stack */ |
ff467594 | 550 | popq %rsp |
625dbc3b | 551 | |
03335e95 | 552 | testb $3, CS(%rsp) |
dde74f2e | 553 | jz retint_kernel |
4d732138 | 554 | |
02bc7768 | 555 | /* Interrupt came from user space */ |
02bc7768 AL |
556 | GLOBAL(retint_user) |
557 | mov %rsp,%rdi | |
558 | call prepare_exit_to_usermode | |
2601e64d | 559 | TRACE_IRQS_IRETQ |
72fe4858 | 560 | SWAPGS |
ff467594 | 561 | jmp restore_regs_and_iret |
2601e64d | 562 | |
627276cb | 563 | /* Returning to kernel space */ |
6ba71b76 | 564 | retint_kernel: |
627276cb DV |
565 | #ifdef CONFIG_PREEMPT |
566 | /* Interrupts are off */ | |
567 | /* Check if we need preemption */ | |
4d732138 | 568 | bt $9, EFLAGS(%rsp) /* were interrupts off? */ |
6ba71b76 | 569 | jnc 1f |
4d732138 | 570 | 0: cmpl $0, PER_CPU_VAR(__preempt_count) |
36acef25 | 571 | jnz 1f |
627276cb | 572 | call preempt_schedule_irq |
36acef25 | 573 | jmp 0b |
6ba71b76 | 574 | 1: |
627276cb | 575 | #endif |
2601e64d IM |
576 | /* |
577 | * The iretq could re-enable interrupts: | |
578 | */ | |
579 | TRACE_IRQS_IRETQ | |
fffbb5dc DV |
580 | |
581 | /* | |
582 | * At this label, code paths which return to kernel and to user, | |
583 | * which come from interrupts/exception and from syscalls, merge. | |
584 | */ | |
ff467594 AL |
585 | restore_regs_and_iret: |
586 | RESTORE_EXTRA_REGS | |
fffbb5dc | 587 | restore_c_regs_and_iret: |
76f5df43 DV |
588 | RESTORE_C_REGS |
589 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
7209a75d AL |
590 | INTERRUPT_RETURN |
591 | ||
592 | ENTRY(native_iret) | |
3891a04a PA |
593 | /* |
594 | * Are we returning to a stack segment from the LDT? Note: in | |
595 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
596 | */ | |
34273f41 | 597 | #ifdef CONFIG_X86_ESPFIX64 |
4d732138 IM |
598 | testb $4, (SS-RIP)(%rsp) |
599 | jnz native_irq_return_ldt | |
34273f41 | 600 | #endif |
3891a04a | 601 | |
af726f21 | 602 | .global native_irq_return_iret |
7209a75d | 603 | native_irq_return_iret: |
b645af2d AL |
604 | /* |
605 | * This may fault. Non-paranoid faults on return to userspace are | |
606 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
607 | * Double-faults due to espfix64 are handled in do_double_fault. | |
608 | * Other faults here are fatal. | |
609 | */ | |
1da177e4 | 610 | iretq |
3701d863 | 611 | |
34273f41 | 612 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 613 | native_irq_return_ldt: |
4d732138 IM |
614 | pushq %rax |
615 | pushq %rdi | |
3891a04a | 616 | SWAPGS |
4d732138 IM |
617 | movq PER_CPU_VAR(espfix_waddr), %rdi |
618 | movq %rax, (0*8)(%rdi) /* RAX */ | |
619 | movq (2*8)(%rsp), %rax /* RIP */ | |
620 | movq %rax, (1*8)(%rdi) | |
621 | movq (3*8)(%rsp), %rax /* CS */ | |
622 | movq %rax, (2*8)(%rdi) | |
623 | movq (4*8)(%rsp), %rax /* RFLAGS */ | |
624 | movq %rax, (3*8)(%rdi) | |
625 | movq (6*8)(%rsp), %rax /* SS */ | |
626 | movq %rax, (5*8)(%rdi) | |
627 | movq (5*8)(%rsp), %rax /* RSP */ | |
628 | movq %rax, (4*8)(%rdi) | |
629 | andl $0xffff0000, %eax | |
630 | popq %rdi | |
631 | orq PER_CPU_VAR(espfix_stack), %rax | |
3891a04a | 632 | SWAPGS |
4d732138 IM |
633 | movq %rax, %rsp |
634 | popq %rax | |
635 | jmp native_irq_return_iret | |
34273f41 | 636 | #endif |
4b787e0b | 637 | END(common_interrupt) |
3891a04a | 638 | |
1da177e4 LT |
639 | /* |
640 | * APIC interrupts. | |
0bd7b798 | 641 | */ |
cf910e83 | 642 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 643 | ENTRY(\sym) |
ee4eb87b | 644 | ASM_CLAC |
4d732138 | 645 | pushq $~(\num) |
39e95433 | 646 | .Lcommon_\sym: |
322648d1 | 647 | interrupt \do_sym |
4d732138 | 648 | jmp ret_from_intr |
322648d1 AH |
649 | END(\sym) |
650 | .endm | |
1da177e4 | 651 | |
cf910e83 SA |
652 | #ifdef CONFIG_TRACING |
653 | #define trace(sym) trace_##sym | |
654 | #define smp_trace(sym) smp_trace_##sym | |
655 | ||
656 | .macro trace_apicinterrupt num sym | |
657 | apicinterrupt3 \num trace(\sym) smp_trace(\sym) | |
658 | .endm | |
659 | #else | |
660 | .macro trace_apicinterrupt num sym do_sym | |
661 | .endm | |
662 | #endif | |
663 | ||
664 | .macro apicinterrupt num sym do_sym | |
665 | apicinterrupt3 \num \sym \do_sym | |
666 | trace_apicinterrupt \num \sym | |
667 | .endm | |
668 | ||
322648d1 | 669 | #ifdef CONFIG_SMP |
4d732138 IM |
670 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
671 | apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt | |
322648d1 | 672 | #endif |
1da177e4 | 673 | |
03b48632 | 674 | #ifdef CONFIG_X86_UV |
4d732138 | 675 | apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 676 | #endif |
4d732138 IM |
677 | |
678 | apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt | |
679 | apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 680 | |
d78f2664 | 681 | #ifdef CONFIG_HAVE_KVM |
4d732138 IM |
682 | apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
683 | apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi | |
d78f2664 YZ |
684 | #endif |
685 | ||
33e5ff63 | 686 | #ifdef CONFIG_X86_MCE_THRESHOLD |
4d732138 | 687 | apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
688 | #endif |
689 | ||
24fd78a8 | 690 | #ifdef CONFIG_X86_MCE_AMD |
4d732138 | 691 | apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt |
24fd78a8 AG |
692 | #endif |
693 | ||
33e5ff63 | 694 | #ifdef CONFIG_X86_THERMAL_VECTOR |
4d732138 | 695 | apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt |
33e5ff63 | 696 | #endif |
1812924b | 697 | |
322648d1 | 698 | #ifdef CONFIG_SMP |
4d732138 IM |
699 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt |
700 | apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt | |
701 | apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt | |
322648d1 | 702 | #endif |
1da177e4 | 703 | |
4d732138 IM |
704 | apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt |
705 | apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 706 | |
e360adbe | 707 | #ifdef CONFIG_IRQ_WORK |
4d732138 | 708 | apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt |
241771ef IM |
709 | #endif |
710 | ||
1da177e4 LT |
711 | /* |
712 | * Exception entry points. | |
0bd7b798 | 713 | */ |
9b476688 | 714 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) |
577ed45e AL |
715 | |
716 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 717 | ENTRY(\sym) |
577ed45e AL |
718 | /* Sanity check */ |
719 | .if \shift_ist != -1 && \paranoid == 0 | |
720 | .error "using shift_ist requires paranoid=1" | |
721 | .endif | |
722 | ||
ee4eb87b | 723 | ASM_CLAC |
b8b1d08b | 724 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
cb5dd2c5 AL |
725 | |
726 | .ifeq \has_error_code | |
4d732138 | 727 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
cb5dd2c5 AL |
728 | .endif |
729 | ||
76f5df43 | 730 | ALLOC_PT_GPREGS_ON_STACK |
cb5dd2c5 AL |
731 | |
732 | .if \paranoid | |
48e08d0f | 733 | .if \paranoid == 1 |
4d732138 IM |
734 | testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ |
735 | jnz 1f | |
48e08d0f | 736 | .endif |
4d732138 | 737 | call paranoid_entry |
cb5dd2c5 | 738 | .else |
4d732138 | 739 | call error_entry |
cb5dd2c5 | 740 | .endif |
ebfc453e | 741 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 742 | |
cb5dd2c5 | 743 | .if \paranoid |
577ed45e | 744 | .if \shift_ist != -1 |
4d732138 | 745 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ |
577ed45e | 746 | .else |
b8b1d08b | 747 | TRACE_IRQS_OFF |
cb5dd2c5 | 748 | .endif |
577ed45e | 749 | .endif |
cb5dd2c5 | 750 | |
4d732138 | 751 | movq %rsp, %rdi /* pt_regs pointer */ |
cb5dd2c5 AL |
752 | |
753 | .if \has_error_code | |
4d732138 IM |
754 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
755 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
cb5dd2c5 | 756 | .else |
4d732138 | 757 | xorl %esi, %esi /* no error code */ |
cb5dd2c5 AL |
758 | .endif |
759 | ||
577ed45e | 760 | .if \shift_ist != -1 |
4d732138 | 761 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
762 | .endif |
763 | ||
4d732138 | 764 | call \do_sym |
cb5dd2c5 | 765 | |
577ed45e | 766 | .if \shift_ist != -1 |
4d732138 | 767 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
768 | .endif |
769 | ||
ebfc453e | 770 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 771 | .if \paranoid |
4d732138 | 772 | jmp paranoid_exit |
cb5dd2c5 | 773 | .else |
4d732138 | 774 | jmp error_exit |
cb5dd2c5 AL |
775 | .endif |
776 | ||
48e08d0f | 777 | .if \paranoid == 1 |
48e08d0f AL |
778 | /* |
779 | * Paranoid entry from userspace. Switch stacks and treat it | |
780 | * as a normal entry. This means that paranoid handlers | |
781 | * run in real process context if user_mode(regs). | |
782 | */ | |
783 | 1: | |
4d732138 | 784 | call error_entry |
48e08d0f | 785 | |
48e08d0f | 786 | |
4d732138 IM |
787 | movq %rsp, %rdi /* pt_regs pointer */ |
788 | call sync_regs | |
789 | movq %rax, %rsp /* switch stack */ | |
48e08d0f | 790 | |
4d732138 | 791 | movq %rsp, %rdi /* pt_regs pointer */ |
48e08d0f AL |
792 | |
793 | .if \has_error_code | |
4d732138 IM |
794 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
795 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
48e08d0f | 796 | .else |
4d732138 | 797 | xorl %esi, %esi /* no error code */ |
48e08d0f AL |
798 | .endif |
799 | ||
4d732138 | 800 | call \do_sym |
48e08d0f | 801 | |
4d732138 | 802 | jmp error_exit /* %ebx: no swapgs flag */ |
48e08d0f | 803 | .endif |
ddeb8f21 | 804 | END(\sym) |
322648d1 | 805 | .endm |
b8b1d08b | 806 | |
25c74b10 | 807 | #ifdef CONFIG_TRACING |
cb5dd2c5 AL |
808 | .macro trace_idtentry sym do_sym has_error_code:req |
809 | idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code | |
810 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
811 | .endm |
812 | #else | |
cb5dd2c5 AL |
813 | .macro trace_idtentry sym do_sym has_error_code:req |
814 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
815 | .endm |
816 | #endif | |
817 | ||
4d732138 IM |
818 | idtentry divide_error do_divide_error has_error_code=0 |
819 | idtentry overflow do_overflow has_error_code=0 | |
820 | idtentry bounds do_bounds has_error_code=0 | |
821 | idtentry invalid_op do_invalid_op has_error_code=0 | |
822 | idtentry device_not_available do_device_not_available has_error_code=0 | |
823 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 | |
824 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 | |
825 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
826 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
827 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
828 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
829 | idtentry alignment_check do_alignment_check has_error_code=1 | |
830 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
831 | ||
832 | ||
833 | /* | |
834 | * Reload gs selector with exception handling | |
835 | * edi: new selector | |
836 | */ | |
9f9d489a | 837 | ENTRY(native_load_gs_index) |
131484c8 | 838 | pushfq |
b8aa287f | 839 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
9f1e87ea | 840 | SWAPGS |
0bd7b798 | 841 | gs_change: |
4d732138 IM |
842 | movl %edi, %gs |
843 | 2: mfence /* workaround */ | |
72fe4858 | 844 | SWAPGS |
131484c8 | 845 | popfq |
9f1e87ea | 846 | ret |
6efdcfaf | 847 | END(native_load_gs_index) |
0bd7b798 | 848 | |
4d732138 IM |
849 | _ASM_EXTABLE(gs_change, bad_gs) |
850 | .section .fixup, "ax" | |
1da177e4 | 851 | /* running with kernelgs */ |
0bd7b798 | 852 | bad_gs: |
4d732138 IM |
853 | SWAPGS /* switch back to user gs */ |
854 | xorl %eax, %eax | |
855 | movl %eax, %gs | |
856 | jmp 2b | |
9f1e87ea | 857 | .previous |
0bd7b798 | 858 | |
2699500b | 859 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 860 | ENTRY(do_softirq_own_stack) |
4d732138 IM |
861 | pushq %rbp |
862 | mov %rsp, %rbp | |
863 | incl PER_CPU_VAR(irq_count) | |
864 | cmove PER_CPU_VAR(irq_stack_ptr), %rsp | |
865 | push %rbp /* frame pointer backlink */ | |
866 | call __do_softirq | |
2699500b | 867 | leaveq |
4d732138 | 868 | decl PER_CPU_VAR(irq_count) |
ed6b676c | 869 | ret |
7d65f4a6 | 870 | END(do_softirq_own_stack) |
75154f40 | 871 | |
3d75e1b8 | 872 | #ifdef CONFIG_XEN |
cb5dd2c5 | 873 | idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
874 | |
875 | /* | |
9f1e87ea CG |
876 | * A note on the "critical region" in our callback handler. |
877 | * We want to avoid stacking callback handlers due to events occurring | |
878 | * during handling of the last event. To do this, we keep events disabled | |
879 | * until we've done all processing. HOWEVER, we must enable events before | |
880 | * popping the stack frame (can't be done atomically) and so it would still | |
881 | * be possible to get enough handler activations to overflow the stack. | |
882 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
883 | * like to avoid the possibility. | |
884 | * So, on entry to the handler we detect whether we interrupted an | |
885 | * existing activation in its critical region -- if so, we pop the current | |
886 | * activation and restart the handler using the previous one. | |
887 | */ | |
4d732138 IM |
888 | ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ |
889 | ||
9f1e87ea CG |
890 | /* |
891 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
892 | * see the correct pointer to the pt_regs | |
893 | */ | |
4d732138 IM |
894 | movq %rdi, %rsp /* we don't return, adjust the stack frame */ |
895 | 11: incl PER_CPU_VAR(irq_count) | |
896 | movq %rsp, %rbp | |
897 | cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp | |
898 | pushq %rbp /* frame pointer backlink */ | |
899 | call xen_evtchn_do_upcall | |
900 | popq %rsp | |
901 | decl PER_CPU_VAR(irq_count) | |
fdfd811d | 902 | #ifndef CONFIG_PREEMPT |
4d732138 | 903 | call xen_maybe_preempt_hcall |
fdfd811d | 904 | #endif |
4d732138 | 905 | jmp error_exit |
371c394a | 906 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
907 | |
908 | /* | |
9f1e87ea CG |
909 | * Hypervisor uses this for application faults while it executes. |
910 | * We get here for two reasons: | |
911 | * 1. Fault while reloading DS, ES, FS or GS | |
912 | * 2. Fault while executing IRET | |
913 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
914 | * registers that could be reloaded and zeroed the others. | |
915 | * Category 2 we fix up by killing the current process. We cannot use the | |
916 | * normal Linux return path in this case because if we use the IRET hypercall | |
917 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
918 | * We distinguish between categories by comparing each saved segment register | |
919 | * with its current contents: any discrepancy means we in category 1. | |
920 | */ | |
3d75e1b8 | 921 | ENTRY(xen_failsafe_callback) |
4d732138 IM |
922 | movl %ds, %ecx |
923 | cmpw %cx, 0x10(%rsp) | |
924 | jne 1f | |
925 | movl %es, %ecx | |
926 | cmpw %cx, 0x18(%rsp) | |
927 | jne 1f | |
928 | movl %fs, %ecx | |
929 | cmpw %cx, 0x20(%rsp) | |
930 | jne 1f | |
931 | movl %gs, %ecx | |
932 | cmpw %cx, 0x28(%rsp) | |
933 | jne 1f | |
3d75e1b8 | 934 | /* All segments match their saved values => Category 2 (Bad IRET). */ |
4d732138 IM |
935 | movq (%rsp), %rcx |
936 | movq 8(%rsp), %r11 | |
937 | addq $0x30, %rsp | |
938 | pushq $0 /* RIP */ | |
939 | pushq %r11 | |
940 | pushq %rcx | |
941 | jmp general_protection | |
3d75e1b8 | 942 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ |
4d732138 IM |
943 | movq (%rsp), %rcx |
944 | movq 8(%rsp), %r11 | |
945 | addq $0x30, %rsp | |
946 | pushq $-1 /* orig_ax = -1 => not a system call */ | |
76f5df43 DV |
947 | ALLOC_PT_GPREGS_ON_STACK |
948 | SAVE_C_REGS | |
949 | SAVE_EXTRA_REGS | |
4d732138 | 950 | jmp error_exit |
3d75e1b8 JF |
951 | END(xen_failsafe_callback) |
952 | ||
cf910e83 | 953 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
954 | xen_hvm_callback_vector xen_evtchn_do_upcall |
955 | ||
3d75e1b8 | 956 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 957 | |
bc2b0331 | 958 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 959 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 S |
960 | hyperv_callback_vector hyperv_vector_handler |
961 | #endif /* CONFIG_HYPERV */ | |
962 | ||
4d732138 IM |
963 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
964 | idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK | |
965 | idtentry stack_segment do_stack_segment has_error_code=1 | |
966 | ||
6cac5a92 | 967 | #ifdef CONFIG_XEN |
4d732138 IM |
968 | idtentry xen_debug do_debug has_error_code=0 |
969 | idtentry xen_int3 do_int3 has_error_code=0 | |
970 | idtentry xen_stack_segment do_stack_segment has_error_code=1 | |
6cac5a92 | 971 | #endif |
4d732138 IM |
972 | |
973 | idtentry general_protection do_general_protection has_error_code=1 | |
974 | trace_idtentry page_fault do_page_fault has_error_code=1 | |
975 | ||
631bc487 | 976 | #ifdef CONFIG_KVM_GUEST |
4d732138 | 977 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 978 | #endif |
4d732138 | 979 | |
ddeb8f21 | 980 | #ifdef CONFIG_X86_MCE |
4d732138 | 981 | idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip) |
ddeb8f21 AH |
982 | #endif |
983 | ||
ebfc453e DV |
984 | /* |
985 | * Save all registers in pt_regs, and switch gs if needed. | |
986 | * Use slow, but surefire "are we in kernel?" check. | |
987 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
988 | */ | |
989 | ENTRY(paranoid_entry) | |
1eeb207f DV |
990 | cld |
991 | SAVE_C_REGS 8 | |
992 | SAVE_EXTRA_REGS 8 | |
4d732138 IM |
993 | movl $1, %ebx |
994 | movl $MSR_GS_BASE, %ecx | |
1eeb207f | 995 | rdmsr |
4d732138 IM |
996 | testl %edx, %edx |
997 | js 1f /* negative -> in kernel */ | |
1eeb207f | 998 | SWAPGS |
4d732138 | 999 | xorl %ebx, %ebx |
1eeb207f | 1000 | 1: ret |
ebfc453e | 1001 | END(paranoid_entry) |
ddeb8f21 | 1002 | |
ebfc453e DV |
1003 | /* |
1004 | * "Paranoid" exit path from exception stack. This is invoked | |
1005 | * only on return from non-NMI IST interrupts that came | |
1006 | * from kernel space. | |
1007 | * | |
1008 | * We may be returning to very strange contexts (e.g. very early | |
1009 | * in syscall entry), so checking for preemption here would | |
1010 | * be complicated. Fortunately, we there's no good reason | |
1011 | * to try to handle preemption here. | |
4d732138 IM |
1012 | * |
1013 | * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) | |
ebfc453e | 1014 | */ |
ddeb8f21 | 1015 | ENTRY(paranoid_exit) |
ddeb8f21 | 1016 | DISABLE_INTERRUPTS(CLBR_NONE) |
5963e317 | 1017 | TRACE_IRQS_OFF_DEBUG |
4d732138 IM |
1018 | testl %ebx, %ebx /* swapgs needed? */ |
1019 | jnz paranoid_exit_no_swapgs | |
f2db9382 | 1020 | TRACE_IRQS_IRETQ |
ddeb8f21 | 1021 | SWAPGS_UNSAFE_STACK |
4d732138 | 1022 | jmp paranoid_exit_restore |
0d550836 | 1023 | paranoid_exit_no_swapgs: |
f2db9382 | 1024 | TRACE_IRQS_IRETQ_DEBUG |
0d550836 | 1025 | paranoid_exit_restore: |
76f5df43 DV |
1026 | RESTORE_EXTRA_REGS |
1027 | RESTORE_C_REGS | |
1028 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
48e08d0f | 1029 | INTERRUPT_RETURN |
ddeb8f21 AH |
1030 | END(paranoid_exit) |
1031 | ||
1032 | /* | |
ebfc453e | 1033 | * Save all registers in pt_regs, and switch gs if needed. |
539f5113 | 1034 | * Return: EBX=0: came from user mode; EBX=1: otherwise |
ddeb8f21 AH |
1035 | */ |
1036 | ENTRY(error_entry) | |
ddeb8f21 | 1037 | cld |
76f5df43 DV |
1038 | SAVE_C_REGS 8 |
1039 | SAVE_EXTRA_REGS 8 | |
4d732138 | 1040 | xorl %ebx, %ebx |
03335e95 | 1041 | testb $3, CS+8(%rsp) |
cb6f64ed | 1042 | jz .Lerror_kernelspace |
539f5113 | 1043 | |
cb6f64ed AL |
1044 | .Lerror_entry_from_usermode_swapgs: |
1045 | /* | |
1046 | * We entered from user mode or we're pretending to have entered | |
1047 | * from user mode due to an IRET fault. | |
1048 | */ | |
ddeb8f21 | 1049 | SWAPGS |
539f5113 | 1050 | |
cb6f64ed | 1051 | .Lerror_entry_from_usermode_after_swapgs: |
02bc7768 AL |
1052 | #ifdef CONFIG_CONTEXT_TRACKING |
1053 | call enter_from_user_mode | |
1054 | #endif | |
1055 | ||
cb6f64ed | 1056 | .Lerror_entry_done: |
02bc7768 | 1057 | |
ddeb8f21 AH |
1058 | TRACE_IRQS_OFF |
1059 | ret | |
ddeb8f21 | 1060 | |
ebfc453e DV |
1061 | /* |
1062 | * There are two places in the kernel that can potentially fault with | |
1063 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1064 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1065 | * for these here too. | |
1066 | */ | |
cb6f64ed | 1067 | .Lerror_kernelspace: |
4d732138 IM |
1068 | incl %ebx |
1069 | leaq native_irq_return_iret(%rip), %rcx | |
1070 | cmpq %rcx, RIP+8(%rsp) | |
cb6f64ed | 1071 | je .Lerror_bad_iret |
4d732138 IM |
1072 | movl %ecx, %eax /* zero extend */ |
1073 | cmpq %rax, RIP+8(%rsp) | |
cb6f64ed | 1074 | je .Lbstep_iret |
4d732138 | 1075 | cmpq $gs_change, RIP+8(%rsp) |
cb6f64ed | 1076 | jne .Lerror_entry_done |
539f5113 AL |
1077 | |
1078 | /* | |
1079 | * hack: gs_change can fail with user gsbase. If this happens, fix up | |
1080 | * gsbase and proceed. We'll fix up the exception and land in | |
1081 | * gs_change's error handler with kernel gsbase. | |
1082 | */ | |
cb6f64ed | 1083 | jmp .Lerror_entry_from_usermode_swapgs |
ae24ffe5 | 1084 | |
cb6f64ed | 1085 | .Lbstep_iret: |
ae24ffe5 | 1086 | /* Fix truncated RIP */ |
4d732138 | 1087 | movq %rcx, RIP+8(%rsp) |
b645af2d AL |
1088 | /* fall through */ |
1089 | ||
cb6f64ed | 1090 | .Lerror_bad_iret: |
539f5113 AL |
1091 | /* |
1092 | * We came from an IRET to user mode, so we have user gsbase. | |
1093 | * Switch to kernel gsbase: | |
1094 | */ | |
b645af2d | 1095 | SWAPGS |
539f5113 AL |
1096 | |
1097 | /* | |
1098 | * Pretend that the exception came from user mode: set up pt_regs | |
1099 | * as if we faulted immediately after IRET and clear EBX so that | |
1100 | * error_exit knows that we will be returning to user mode. | |
1101 | */ | |
4d732138 IM |
1102 | mov %rsp, %rdi |
1103 | call fixup_bad_iret | |
1104 | mov %rax, %rsp | |
539f5113 | 1105 | decl %ebx |
cb6f64ed | 1106 | jmp .Lerror_entry_from_usermode_after_swapgs |
ddeb8f21 AH |
1107 | END(error_entry) |
1108 | ||
1109 | ||
539f5113 AL |
1110 | /* |
1111 | * On entry, EBS is a "return to kernel mode" flag: | |
1112 | * 1: already in kernel mode, don't need SWAPGS | |
1113 | * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode | |
1114 | */ | |
ddeb8f21 | 1115 | ENTRY(error_exit) |
4d732138 | 1116 | movl %ebx, %eax |
ddeb8f21 AH |
1117 | DISABLE_INTERRUPTS(CLBR_NONE) |
1118 | TRACE_IRQS_OFF | |
4d732138 IM |
1119 | testl %eax, %eax |
1120 | jnz retint_kernel | |
1121 | jmp retint_user | |
ddeb8f21 AH |
1122 | END(error_exit) |
1123 | ||
0784b364 | 1124 | /* Runs on exception stack */ |
ddeb8f21 | 1125 | ENTRY(nmi) |
fc57a7c6 AL |
1126 | /* |
1127 | * Fix up the exception frame if we're on Xen. | |
1128 | * PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most | |
1129 | * one value to the stack on native, so it may clobber the rdx | |
1130 | * scratch slot, but it won't clobber any of the important | |
1131 | * slots past it. | |
1132 | * | |
1133 | * Xen is a different story, because the Xen frame itself overlaps | |
1134 | * the "NMI executing" variable. | |
1135 | */ | |
ddeb8f21 | 1136 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
fc57a7c6 | 1137 | |
3f3c8b8c SR |
1138 | /* |
1139 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1140 | * the iretq it performs will take us out of NMI context. | |
1141 | * This means that we can have nested NMIs where the next | |
1142 | * NMI is using the top of the stack of the previous NMI. We | |
1143 | * can't let it execute because the nested NMI will corrupt the | |
1144 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1145 | * anyway. | |
1146 | * | |
1147 | * To handle this case we do the following: | |
1148 | * Check the a special location on the stack that contains | |
1149 | * a variable that is set when NMIs are executing. | |
1150 | * The interrupted task's stack is also checked to see if it | |
1151 | * is an NMI stack. | |
1152 | * If the variable is not set and the stack is not the NMI | |
1153 | * stack then: | |
1154 | * o Set the special variable on the stack | |
0b22930e AL |
1155 | * o Copy the interrupt frame into an "outermost" location on the |
1156 | * stack | |
1157 | * o Copy the interrupt frame into an "iret" location on the stack | |
3f3c8b8c SR |
1158 | * o Continue processing the NMI |
1159 | * If the variable is set or the previous stack is the NMI stack: | |
0b22930e | 1160 | * o Modify the "iret" location to jump to the repeat_nmi |
3f3c8b8c SR |
1161 | * o return back to the first NMI |
1162 | * | |
1163 | * Now on exit of the first NMI, we first clear the stack variable | |
1164 | * The NMI stack will tell any nested NMIs at that point that it is | |
1165 | * nested. Then we pop the stack normally with iret, and if there was | |
1166 | * a nested NMI that updated the copy interrupt stack frame, a | |
1167 | * jump will be made to the repeat_nmi code that will handle the second | |
1168 | * NMI. | |
9b6e6a83 AL |
1169 | * |
1170 | * However, espfix prevents us from directly returning to userspace | |
1171 | * with a single IRET instruction. Similarly, IRET to user mode | |
1172 | * can fault. We therefore handle NMIs from user space like | |
1173 | * other IST entries. | |
3f3c8b8c SR |
1174 | */ |
1175 | ||
146b2b09 | 1176 | /* Use %rdx as our temp variable throughout */ |
4d732138 | 1177 | pushq %rdx |
3f3c8b8c | 1178 | |
9b6e6a83 AL |
1179 | testb $3, CS-RIP+8(%rsp) |
1180 | jz .Lnmi_from_kernel | |
1181 | ||
1182 | /* | |
1183 | * NMI from user mode. We need to run on the thread stack, but we | |
1184 | * can't go through the normal entry paths: NMIs are masked, and | |
1185 | * we don't want to enable interrupts, because then we'll end | |
1186 | * up in an awkward situation in which IRQs are on but NMIs | |
1187 | * are off. | |
83c133cf AL |
1188 | * |
1189 | * We also must not push anything to the stack before switching | |
1190 | * stacks lest we corrupt the "NMI executing" variable. | |
9b6e6a83 AL |
1191 | */ |
1192 | ||
83c133cf | 1193 | SWAPGS_UNSAFE_STACK |
9b6e6a83 AL |
1194 | cld |
1195 | movq %rsp, %rdx | |
1196 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
1197 | pushq 5*8(%rdx) /* pt_regs->ss */ | |
1198 | pushq 4*8(%rdx) /* pt_regs->rsp */ | |
1199 | pushq 3*8(%rdx) /* pt_regs->flags */ | |
1200 | pushq 2*8(%rdx) /* pt_regs->cs */ | |
1201 | pushq 1*8(%rdx) /* pt_regs->rip */ | |
1202 | pushq $-1 /* pt_regs->orig_ax */ | |
1203 | pushq %rdi /* pt_regs->di */ | |
1204 | pushq %rsi /* pt_regs->si */ | |
1205 | pushq (%rdx) /* pt_regs->dx */ | |
1206 | pushq %rcx /* pt_regs->cx */ | |
1207 | pushq %rax /* pt_regs->ax */ | |
1208 | pushq %r8 /* pt_regs->r8 */ | |
1209 | pushq %r9 /* pt_regs->r9 */ | |
1210 | pushq %r10 /* pt_regs->r10 */ | |
1211 | pushq %r11 /* pt_regs->r11 */ | |
1212 | pushq %rbx /* pt_regs->rbx */ | |
1213 | pushq %rbp /* pt_regs->rbp */ | |
1214 | pushq %r12 /* pt_regs->r12 */ | |
1215 | pushq %r13 /* pt_regs->r13 */ | |
1216 | pushq %r14 /* pt_regs->r14 */ | |
1217 | pushq %r15 /* pt_regs->r15 */ | |
1218 | ||
1219 | /* | |
1220 | * At this point we no longer need to worry about stack damage | |
1221 | * due to nesting -- we're on the normal thread stack and we're | |
1222 | * done with the NMI stack. | |
1223 | */ | |
1224 | ||
1225 | movq %rsp, %rdi | |
1226 | movq $-1, %rsi | |
1227 | call do_nmi | |
1228 | ||
45d5a168 | 1229 | /* |
9b6e6a83 AL |
1230 | * Return back to user mode. We must *not* do the normal exit |
1231 | * work, because we don't want to enable interrupts. Fortunately, | |
1232 | * do_nmi doesn't modify pt_regs. | |
45d5a168 | 1233 | */ |
9b6e6a83 AL |
1234 | SWAPGS |
1235 | jmp restore_c_regs_and_iret | |
45d5a168 | 1236 | |
9b6e6a83 | 1237 | .Lnmi_from_kernel: |
3f3c8b8c | 1238 | /* |
0b22930e AL |
1239 | * Here's what our stack frame will look like: |
1240 | * +---------------------------------------------------------+ | |
1241 | * | original SS | | |
1242 | * | original Return RSP | | |
1243 | * | original RFLAGS | | |
1244 | * | original CS | | |
1245 | * | original RIP | | |
1246 | * +---------------------------------------------------------+ | |
1247 | * | temp storage for rdx | | |
1248 | * +---------------------------------------------------------+ | |
1249 | * | "NMI executing" variable | | |
1250 | * +---------------------------------------------------------+ | |
1251 | * | iret SS } Copied from "outermost" frame | | |
1252 | * | iret Return RSP } on each loop iteration; overwritten | | |
1253 | * | iret RFLAGS } by a nested NMI to force another | | |
1254 | * | iret CS } iteration if needed. | | |
1255 | * | iret RIP } | | |
1256 | * +---------------------------------------------------------+ | |
1257 | * | outermost SS } initialized in first_nmi; | | |
1258 | * | outermost Return RSP } will not be changed before | | |
1259 | * | outermost RFLAGS } NMI processing is done. | | |
1260 | * | outermost CS } Copied to "iret" frame on each | | |
1261 | * | outermost RIP } iteration. | | |
1262 | * +---------------------------------------------------------+ | |
1263 | * | pt_regs | | |
1264 | * +---------------------------------------------------------+ | |
1265 | * | |
1266 | * The "original" frame is used by hardware. Before re-enabling | |
1267 | * NMIs, we need to be done with it, and we need to leave enough | |
1268 | * space for the asm code here. | |
1269 | * | |
1270 | * We return by executing IRET while RSP points to the "iret" frame. | |
1271 | * That will either return for real or it will loop back into NMI | |
1272 | * processing. | |
1273 | * | |
1274 | * The "outermost" frame is copied to the "iret" frame on each | |
1275 | * iteration of the loop, so each iteration starts with the "iret" | |
1276 | * frame pointing to the final return target. | |
1277 | */ | |
1278 | ||
45d5a168 | 1279 | /* |
0b22930e AL |
1280 | * Determine whether we're a nested NMI. |
1281 | * | |
a27507ca AL |
1282 | * If we interrupted kernel code between repeat_nmi and |
1283 | * end_repeat_nmi, then we are a nested NMI. We must not | |
1284 | * modify the "iret" frame because it's being written by | |
1285 | * the outer NMI. That's okay; the outer NMI handler is | |
1286 | * about to about to call do_nmi anyway, so we can just | |
1287 | * resume the outer NMI. | |
45d5a168 | 1288 | */ |
a27507ca AL |
1289 | |
1290 | movq $repeat_nmi, %rdx | |
1291 | cmpq 8(%rsp), %rdx | |
1292 | ja 1f | |
1293 | movq $end_repeat_nmi, %rdx | |
1294 | cmpq 8(%rsp), %rdx | |
1295 | ja nested_nmi_out | |
1296 | 1: | |
45d5a168 | 1297 | |
3f3c8b8c | 1298 | /* |
a27507ca | 1299 | * Now check "NMI executing". If it's set, then we're nested. |
0b22930e AL |
1300 | * This will not detect if we interrupted an outer NMI just |
1301 | * before IRET. | |
3f3c8b8c | 1302 | */ |
4d732138 IM |
1303 | cmpl $1, -8(%rsp) |
1304 | je nested_nmi | |
3f3c8b8c SR |
1305 | |
1306 | /* | |
0b22930e AL |
1307 | * Now test if the previous stack was an NMI stack. This covers |
1308 | * the case where we interrupt an outer NMI after it clears | |
810bc075 AL |
1309 | * "NMI executing" but before IRET. We need to be careful, though: |
1310 | * there is one case in which RSP could point to the NMI stack | |
1311 | * despite there being no NMI active: naughty userspace controls | |
1312 | * RSP at the very beginning of the SYSCALL targets. We can | |
1313 | * pull a fast one on naughty userspace, though: we program | |
1314 | * SYSCALL to mask DF, so userspace cannot cause DF to be set | |
1315 | * if it controls the kernel's RSP. We set DF before we clear | |
1316 | * "NMI executing". | |
3f3c8b8c | 1317 | */ |
0784b364 DV |
1318 | lea 6*8(%rsp), %rdx |
1319 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1320 | cmpq %rdx, 4*8(%rsp) | |
1321 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1322 | ja first_nmi | |
4d732138 | 1323 | |
0784b364 DV |
1324 | subq $EXCEPTION_STKSZ, %rdx |
1325 | cmpq %rdx, 4*8(%rsp) | |
1326 | /* If it is below the NMI stack, it is a normal NMI */ | |
1327 | jb first_nmi | |
810bc075 AL |
1328 | |
1329 | /* Ah, it is within the NMI stack. */ | |
1330 | ||
1331 | testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) | |
1332 | jz first_nmi /* RSP was user controlled. */ | |
1333 | ||
1334 | /* This is a nested NMI. */ | |
0784b364 | 1335 | |
3f3c8b8c SR |
1336 | nested_nmi: |
1337 | /* | |
0b22930e AL |
1338 | * Modify the "iret" frame to point to repeat_nmi, forcing another |
1339 | * iteration of NMI handling. | |
3f3c8b8c | 1340 | */ |
23a781e9 | 1341 | subq $8, %rsp |
4d732138 IM |
1342 | leaq -10*8(%rsp), %rdx |
1343 | pushq $__KERNEL_DS | |
1344 | pushq %rdx | |
131484c8 | 1345 | pushfq |
4d732138 IM |
1346 | pushq $__KERNEL_CS |
1347 | pushq $repeat_nmi | |
3f3c8b8c SR |
1348 | |
1349 | /* Put stack back */ | |
4d732138 | 1350 | addq $(6*8), %rsp |
3f3c8b8c SR |
1351 | |
1352 | nested_nmi_out: | |
4d732138 | 1353 | popq %rdx |
3f3c8b8c | 1354 | |
0b22930e | 1355 | /* We are returning to kernel mode, so this cannot result in a fault. */ |
3f3c8b8c SR |
1356 | INTERRUPT_RETURN |
1357 | ||
1358 | first_nmi: | |
0b22930e | 1359 | /* Restore rdx. */ |
4d732138 | 1360 | movq (%rsp), %rdx |
62610913 | 1361 | |
36f1a77b AL |
1362 | /* Make room for "NMI executing". */ |
1363 | pushq $0 | |
3f3c8b8c | 1364 | |
0b22930e | 1365 | /* Leave room for the "iret" frame */ |
4d732138 | 1366 | subq $(5*8), %rsp |
28696f43 | 1367 | |
0b22930e | 1368 | /* Copy the "original" frame to the "outermost" frame */ |
3f3c8b8c | 1369 | .rept 5 |
4d732138 | 1370 | pushq 11*8(%rsp) |
3f3c8b8c | 1371 | .endr |
62610913 | 1372 | |
79fb4ad6 SR |
1373 | /* Everything up to here is safe from nested NMIs */ |
1374 | ||
a97439aa AL |
1375 | #ifdef CONFIG_DEBUG_ENTRY |
1376 | /* | |
1377 | * For ease of testing, unmask NMIs right away. Disabled by | |
1378 | * default because IRET is very expensive. | |
1379 | */ | |
1380 | pushq $0 /* SS */ | |
1381 | pushq %rsp /* RSP (minus 8 because of the previous push) */ | |
1382 | addq $8, (%rsp) /* Fix up RSP */ | |
1383 | pushfq /* RFLAGS */ | |
1384 | pushq $__KERNEL_CS /* CS */ | |
1385 | pushq $1f /* RIP */ | |
1386 | INTERRUPT_RETURN /* continues at repeat_nmi below */ | |
1387 | 1: | |
1388 | #endif | |
1389 | ||
0b22930e | 1390 | repeat_nmi: |
62610913 JB |
1391 | /* |
1392 | * If there was a nested NMI, the first NMI's iret will return | |
1393 | * here. But NMIs are still enabled and we can take another | |
1394 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1395 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1396 | * it will just return, as we are about to repeat an NMI anyway. | |
1397 | * This makes it safe to copy to the stack frame that a nested | |
1398 | * NMI will update. | |
0b22930e AL |
1399 | * |
1400 | * RSP is pointing to "outermost RIP". gsbase is unknown, but, if | |
1401 | * we're repeating an NMI, gsbase has the same value that it had on | |
1402 | * the first iteration. paranoid_entry will load the kernel | |
36f1a77b AL |
1403 | * gsbase if needed before we call do_nmi. "NMI executing" |
1404 | * is zero. | |
62610913 | 1405 | */ |
36f1a77b | 1406 | movq $1, 10*8(%rsp) /* Set "NMI executing". */ |
3f3c8b8c | 1407 | |
62610913 | 1408 | /* |
0b22930e AL |
1409 | * Copy the "outermost" frame to the "iret" frame. NMIs that nest |
1410 | * here must not modify the "iret" frame while we're writing to | |
1411 | * it or it will end up containing garbage. | |
62610913 | 1412 | */ |
4d732138 | 1413 | addq $(10*8), %rsp |
3f3c8b8c | 1414 | .rept 5 |
4d732138 | 1415 | pushq -6*8(%rsp) |
3f3c8b8c | 1416 | .endr |
4d732138 | 1417 | subq $(5*8), %rsp |
62610913 | 1418 | end_repeat_nmi: |
3f3c8b8c SR |
1419 | |
1420 | /* | |
0b22930e AL |
1421 | * Everything below this point can be preempted by a nested NMI. |
1422 | * If this happens, then the inner NMI will change the "iret" | |
1423 | * frame to point back to repeat_nmi. | |
3f3c8b8c | 1424 | */ |
4d732138 | 1425 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 DV |
1426 | ALLOC_PT_GPREGS_ON_STACK |
1427 | ||
1fd466ef | 1428 | /* |
ebfc453e | 1429 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1430 | * as we should not be calling schedule in NMI context. |
1431 | * Even with normal interrupts enabled. An NMI should not be | |
1432 | * setting NEED_RESCHED or anything that normal interrupts and | |
1433 | * exceptions might do. | |
1434 | */ | |
4d732138 | 1435 | call paranoid_entry |
7fbb98c5 | 1436 | |
ddeb8f21 | 1437 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
4d732138 IM |
1438 | movq %rsp, %rdi |
1439 | movq $-1, %rsi | |
1440 | call do_nmi | |
7fbb98c5 | 1441 | |
4d732138 IM |
1442 | testl %ebx, %ebx /* swapgs needed? */ |
1443 | jnz nmi_restore | |
ddeb8f21 AH |
1444 | nmi_swapgs: |
1445 | SWAPGS_UNSAFE_STACK | |
1446 | nmi_restore: | |
76f5df43 DV |
1447 | RESTORE_EXTRA_REGS |
1448 | RESTORE_C_REGS | |
0b22930e AL |
1449 | |
1450 | /* Point RSP at the "iret" frame. */ | |
76f5df43 | 1451 | REMOVE_PT_GPREGS_FROM_STACK 6*8 |
28696f43 | 1452 | |
810bc075 AL |
1453 | /* |
1454 | * Clear "NMI executing". Set DF first so that we can easily | |
1455 | * distinguish the remaining code between here and IRET from | |
1456 | * the SYSCALL entry and exit paths. On a native kernel, we | |
1457 | * could just inspect RIP, but, on paravirt kernels, | |
1458 | * INTERRUPT_RETURN can translate into a jump into a | |
1459 | * hypercall page. | |
1460 | */ | |
1461 | std | |
1462 | movq $0, 5*8(%rsp) /* clear "NMI executing" */ | |
0b22930e AL |
1463 | |
1464 | /* | |
1465 | * INTERRUPT_RETURN reads the "iret" frame and exits the NMI | |
1466 | * stack in a single instruction. We are returning to kernel | |
1467 | * mode, so this cannot result in a fault. | |
1468 | */ | |
5ca6f70f | 1469 | INTERRUPT_RETURN |
ddeb8f21 AH |
1470 | END(nmi) |
1471 | ||
1472 | ENTRY(ignore_sysret) | |
4d732138 | 1473 | mov $-ENOSYS, %eax |
ddeb8f21 | 1474 | sysret |
ddeb8f21 | 1475 | END(ignore_sysret) |