]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * linux/arch/x86_64/entry.S | |
4 | * | |
5 | * Copyright (C) 1991, 1992 Linus Torvalds | |
6 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
7 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
4d732138 | 8 | * |
1da177e4 LT |
9 | * entry.S contains the system-call and fault low-level handling routines. |
10 | * | |
8b4777a4 AL |
11 | * Some of this is documented in Documentation/x86/entry_64.txt |
12 | * | |
0bd7b798 | 13 | * A note on terminology: |
4d732138 IM |
14 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
15 | * at the top of the kernel process stack. | |
2e91a17b AK |
16 | * |
17 | * Some macro usage: | |
4d732138 IM |
18 | * - ENTRY/END: Define functions in the symbol table. |
19 | * - TRACE_IRQ_*: Trace hardirq state for lock debugging. | |
20 | * - idtentry: Define exception entry points. | |
1da177e4 | 21 | */ |
1da177e4 LT |
22 | #include <linux/linkage.h> |
23 | #include <asm/segment.h> | |
1da177e4 LT |
24 | #include <asm/cache.h> |
25 | #include <asm/errno.h> | |
e2d5df93 | 26 | #include <asm/asm-offsets.h> |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/unistd.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/hw_irq.h> | |
0341c14d | 31 | #include <asm/page_types.h> |
2601e64d | 32 | #include <asm/irqflags.h> |
72fe4858 | 33 | #include <asm/paravirt.h> |
9939ddaf | 34 | #include <asm/percpu.h> |
d7abc0fa | 35 | #include <asm/asm.h> |
63bcff2a | 36 | #include <asm/smap.h> |
3891a04a | 37 | #include <asm/pgtable_types.h> |
784d5699 | 38 | #include <asm/export.h> |
8c1f7558 | 39 | #include <asm/frame.h> |
2641f08b | 40 | #include <asm/nospec-branch.h> |
d7e7528b | 41 | #include <linux/err.h> |
1da177e4 | 42 | |
6fd166aa PZ |
43 | #include "calling.h" |
44 | ||
4d732138 IM |
45 | .code64 |
46 | .section .entry.text, "ax" | |
16444a8a | 47 | |
72fe4858 | 48 | #ifdef CONFIG_PARAVIRT |
2be29982 | 49 | ENTRY(native_usergs_sysret64) |
8c1f7558 | 50 | UNWIND_HINT_EMPTY |
72fe4858 GOC |
51 | swapgs |
52 | sysretq | |
8c1f7558 | 53 | END(native_usergs_sysret64) |
72fe4858 GOC |
54 | #endif /* CONFIG_PARAVIRT */ |
55 | ||
ca37e57b | 56 | .macro TRACE_IRQS_FLAGS flags:req |
2601e64d | 57 | #ifdef CONFIG_TRACE_IRQFLAGS |
ca37e57b | 58 | bt $9, \flags /* interrupts off? */ |
4d732138 | 59 | jnc 1f |
2601e64d IM |
60 | TRACE_IRQS_ON |
61 | 1: | |
62 | #endif | |
63 | .endm | |
64 | ||
ca37e57b AL |
65 | .macro TRACE_IRQS_IRETQ |
66 | TRACE_IRQS_FLAGS EFLAGS(%rsp) | |
67 | .endm | |
68 | ||
5963e317 SR |
69 | /* |
70 | * When dynamic function tracer is enabled it will add a breakpoint | |
71 | * to all locations that it is about to modify, sync CPUs, update | |
72 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
73 | * if lockdep is enabled, it might jump back into the debug handler | |
74 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
75 | * | |
76 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
77 | * make sure the stack pointer does not get reset back to the top | |
78 | * of the debug stack, and instead just reuses the current stack. | |
79 | */ | |
80 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
81 | ||
82 | .macro TRACE_IRQS_OFF_DEBUG | |
4d732138 | 83 | call debug_stack_set_zero |
5963e317 | 84 | TRACE_IRQS_OFF |
4d732138 | 85 | call debug_stack_reset |
5963e317 SR |
86 | .endm |
87 | ||
88 | .macro TRACE_IRQS_ON_DEBUG | |
4d732138 | 89 | call debug_stack_set_zero |
5963e317 | 90 | TRACE_IRQS_ON |
4d732138 | 91 | call debug_stack_reset |
5963e317 SR |
92 | .endm |
93 | ||
f2db9382 | 94 | .macro TRACE_IRQS_IRETQ_DEBUG |
4d732138 IM |
95 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
96 | jnc 1f | |
5963e317 SR |
97 | TRACE_IRQS_ON_DEBUG |
98 | 1: | |
99 | .endm | |
100 | ||
101 | #else | |
4d732138 IM |
102 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF |
103 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
104 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
5963e317 SR |
105 | #endif |
106 | ||
1da177e4 | 107 | /* |
4d732138 | 108 | * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 109 | * |
fda57b22 AL |
110 | * This is the only entry point used for 64-bit system calls. The |
111 | * hardware interface is reasonably well designed and the register to | |
112 | * argument mapping Linux uses fits well with the registers that are | |
113 | * available when SYSCALL is used. | |
114 | * | |
115 | * SYSCALL instructions can be found inlined in libc implementations as | |
116 | * well as some other programs and libraries. There are also a handful | |
117 | * of SYSCALL instructions in the vDSO used, for example, as a | |
118 | * clock_gettimeofday fallback. | |
119 | * | |
4d732138 | 120 | * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
b87cf63e DV |
121 | * then loads new ss, cs, and rip from previously programmed MSRs. |
122 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
123 | * are not needed). SYSCALL does not save anything on the stack | |
124 | * and does not change rsp. | |
125 | * | |
126 | * Registers on entry: | |
1da177e4 | 127 | * rax system call number |
b87cf63e DV |
128 | * rcx return address |
129 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 130 | * rdi arg0 |
1da177e4 | 131 | * rsi arg1 |
0bd7b798 | 132 | * rdx arg2 |
b87cf63e | 133 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
134 | * r8 arg4 |
135 | * r9 arg5 | |
4d732138 | 136 | * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) |
0bd7b798 | 137 | * |
1da177e4 LT |
138 | * Only called from user space. |
139 | * | |
7fcb3bc3 | 140 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
141 | * it deals with uncanonical addresses better. SYSRET has trouble |
142 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 143 | */ |
1da177e4 | 144 | |
3386bc8a AL |
145 | .pushsection .entry_trampoline, "ax" |
146 | ||
147 | /* | |
148 | * The code in here gets remapped into cpu_entry_area's trampoline. This means | |
149 | * that the assembler and linker have the wrong idea as to where this code | |
150 | * lives (and, in fact, it's mapped more than once, so it's not even at a | |
151 | * fixed address). So we can't reference any symbols outside the entry | |
152 | * trampoline and expect it to work. | |
153 | * | |
154 | * Instead, we carefully abuse %rip-relative addressing. | |
155 | * _entry_trampoline(%rip) refers to the start of the remapped) entry | |
156 | * trampoline. We can thus find cpu_entry_area with this macro: | |
157 | */ | |
158 | ||
159 | #define CPU_ENTRY_AREA \ | |
160 | _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) | |
161 | ||
162 | /* The top word of the SYSENTER stack is hot and is usable as scratch space. */ | |
4fe2d8b1 DH |
163 | #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ |
164 | SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA | |
3386bc8a AL |
165 | |
166 | ENTRY(entry_SYSCALL_64_trampoline) | |
167 | UNWIND_HINT_EMPTY | |
168 | swapgs | |
169 | ||
170 | /* Stash the user RSP. */ | |
171 | movq %rsp, RSP_SCRATCH | |
172 | ||
8a09317b DH |
173 | /* Note: using %rsp as a scratch reg. */ |
174 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp | |
175 | ||
3386bc8a AL |
176 | /* Load the top of the task stack into RSP */ |
177 | movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp | |
178 | ||
179 | /* Start building the simulated IRET frame. */ | |
180 | pushq $__USER_DS /* pt_regs->ss */ | |
181 | pushq RSP_SCRATCH /* pt_regs->sp */ | |
182 | pushq %r11 /* pt_regs->flags */ | |
183 | pushq $__USER_CS /* pt_regs->cs */ | |
184 | pushq %rcx /* pt_regs->ip */ | |
185 | ||
186 | /* | |
187 | * x86 lacks a near absolute jump, and we can't jump to the real | |
188 | * entry text with a relative jump. We could push the target | |
189 | * address and then use retq, but this destroys the pipeline on | |
190 | * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, | |
191 | * spill RDI and restore it in a second-stage trampoline. | |
192 | */ | |
193 | pushq %rdi | |
194 | movq $entry_SYSCALL_64_stage2, %rdi | |
2641f08b | 195 | JMP_NOSPEC %rdi |
3386bc8a AL |
196 | END(entry_SYSCALL_64_trampoline) |
197 | ||
198 | .popsection | |
199 | ||
200 | ENTRY(entry_SYSCALL_64_stage2) | |
201 | UNWIND_HINT_EMPTY | |
202 | popq %rdi | |
203 | jmp entry_SYSCALL_64_after_hwframe | |
204 | END(entry_SYSCALL_64_stage2) | |
205 | ||
b2502b41 | 206 | ENTRY(entry_SYSCALL_64) |
8c1f7558 | 207 | UNWIND_HINT_EMPTY |
9ed8e7d8 DV |
208 | /* |
209 | * Interrupts are off on entry. | |
210 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
211 | * it is too small to ever cause noticeable irq latency. | |
212 | */ | |
72fe4858 | 213 | |
8a9949bc | 214 | swapgs |
8a09317b | 215 | /* |
14b1fcc6 | 216 | * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it |
8a09317b DH |
217 | * is not required to switch CR3. |
218 | */ | |
4d732138 IM |
219 | movq %rsp, PER_CPU_VAR(rsp_scratch) |
220 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
9ed8e7d8 DV |
221 | |
222 | /* Construct struct pt_regs on stack */ | |
4d732138 IM |
223 | pushq $__USER_DS /* pt_regs->ss */ |
224 | pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
4d732138 IM |
225 | pushq %r11 /* pt_regs->flags */ |
226 | pushq $__USER_CS /* pt_regs->cs */ | |
227 | pushq %rcx /* pt_regs->ip */ | |
8a9949bc | 228 | GLOBAL(entry_SYSCALL_64_after_hwframe) |
4d732138 | 229 | pushq %rax /* pt_regs->orig_ax */ |
30907fd1 DB |
230 | |
231 | PUSH_AND_CLEAR_REGS rax=$-ENOSYS | |
4d732138 | 232 | |
548c3050 AL |
233 | TRACE_IRQS_OFF |
234 | ||
1e423bff | 235 | /* IRQs are off. */ |
29ea1b25 | 236 | movq %rsp, %rdi |
1e423bff AL |
237 | call do_syscall_64 /* returns with IRQs disabled */ |
238 | ||
29ea1b25 | 239 | TRACE_IRQS_IRETQ /* we're about to change IF */ |
fffbb5dc DV |
240 | |
241 | /* | |
242 | * Try to use SYSRET instead of IRET if we're returning to | |
8a055d7f AL |
243 | * a completely clean 64-bit userspace context. If we're not, |
244 | * go to the slow exit path. | |
fffbb5dc | 245 | */ |
4d732138 IM |
246 | movq RCX(%rsp), %rcx |
247 | movq RIP(%rsp), %r11 | |
8a055d7f AL |
248 | |
249 | cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ | |
250 | jne swapgs_restore_regs_and_return_to_usermode | |
fffbb5dc DV |
251 | |
252 | /* | |
253 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
254 | * in kernel space. This essentially lets the user take over | |
17be0aec | 255 | * the kernel, since userspace controls RSP. |
fffbb5dc | 256 | * |
17be0aec | 257 | * If width of "canonical tail" ever becomes variable, this will need |
fffbb5dc | 258 | * to be updated to remain correct on both old and new CPUs. |
361b4b58 | 259 | * |
cbe0317b KS |
260 | * Change top bits to match most significant bit (47th or 56th bit |
261 | * depending on paging mode) in the address. | |
fffbb5dc | 262 | */ |
17be0aec DV |
263 | shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx |
264 | sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
4d732138 | 265 | |
17be0aec DV |
266 | /* If this changed %rcx, it was not canonical */ |
267 | cmpq %rcx, %r11 | |
8a055d7f | 268 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc | 269 | |
4d732138 | 270 | cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ |
8a055d7f | 271 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc | 272 | |
4d732138 IM |
273 | movq R11(%rsp), %r11 |
274 | cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ | |
8a055d7f | 275 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
276 | |
277 | /* | |
3e035305 BP |
278 | * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot |
279 | * restore RF properly. If the slowpath sets it for whatever reason, we | |
280 | * need to restore it correctly. | |
281 | * | |
282 | * SYSRET can restore TF, but unlike IRET, restoring TF results in a | |
283 | * trap from userspace immediately after SYSRET. This would cause an | |
284 | * infinite loop whenever #DB happens with register state that satisfies | |
285 | * the opportunistic SYSRET conditions. For example, single-stepping | |
286 | * this user code: | |
fffbb5dc | 287 | * |
4d732138 | 288 | * movq $stuck_here, %rcx |
fffbb5dc DV |
289 | * pushfq |
290 | * popq %r11 | |
291 | * stuck_here: | |
292 | * | |
293 | * would never get past 'stuck_here'. | |
294 | */ | |
4d732138 | 295 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 |
8a055d7f | 296 | jnz swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
297 | |
298 | /* nothing to check for RSP */ | |
299 | ||
4d732138 | 300 | cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ |
8a055d7f | 301 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
302 | |
303 | /* | |
4d732138 IM |
304 | * We win! This label is here just for ease of understanding |
305 | * perf profiles. Nothing jumps here. | |
fffbb5dc DV |
306 | */ |
307 | syscall_return_via_sysret: | |
17be0aec | 308 | /* rcx and r11 are already restored (see code above) */ |
8c1f7558 | 309 | UNWIND_HINT_EMPTY |
502af0d7 | 310 | POP_REGS pop_rdi=0 skip_r11rcx=1 |
3e3b9293 AL |
311 | |
312 | /* | |
313 | * Now all regs are restored except RSP and RDI. | |
314 | * Save old stack pointer and switch to trampoline stack. | |
315 | */ | |
316 | movq %rsp, %rdi | |
c482feef | 317 | movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp |
3e3b9293 AL |
318 | |
319 | pushq RSP-RDI(%rdi) /* RSP */ | |
320 | pushq (%rdi) /* RDI */ | |
321 | ||
322 | /* | |
323 | * We are on the trampoline stack. All regs except RDI are live. | |
324 | * We can do future final exit work right here. | |
325 | */ | |
6fd166aa | 326 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
3e3b9293 | 327 | |
4fbb3910 | 328 | popq %rdi |
3e3b9293 | 329 | popq %rsp |
fffbb5dc | 330 | USERGS_SYSRET64 |
b2502b41 | 331 | END(entry_SYSCALL_64) |
0bd7b798 | 332 | |
0100301b BG |
333 | /* |
334 | * %rdi: prev task | |
335 | * %rsi: next task | |
336 | */ | |
337 | ENTRY(__switch_to_asm) | |
8c1f7558 | 338 | UNWIND_HINT_FUNC |
0100301b BG |
339 | /* |
340 | * Save callee-saved registers | |
341 | * This must match the order in inactive_task_frame | |
342 | */ | |
343 | pushq %rbp | |
344 | pushq %rbx | |
345 | pushq %r12 | |
346 | pushq %r13 | |
347 | pushq %r14 | |
348 | pushq %r15 | |
349 | ||
350 | /* switch stack */ | |
351 | movq %rsp, TASK_threadsp(%rdi) | |
352 | movq TASK_threadsp(%rsi), %rsp | |
353 | ||
354 | #ifdef CONFIG_CC_STACKPROTECTOR | |
355 | movq TASK_stack_canary(%rsi), %rbx | |
356 | movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset | |
357 | #endif | |
358 | ||
c995efd5 DW |
359 | #ifdef CONFIG_RETPOLINE |
360 | /* | |
361 | * When switching from a shallower to a deeper call stack | |
362 | * the RSB may either underflow or use entries populated | |
363 | * with userspace addresses. On CPUs where those concerns | |
364 | * exist, overwrite the RSB with entries which capture | |
365 | * speculative execution to prevent attack. | |
366 | */ | |
d1c99108 | 367 | FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW |
c995efd5 DW |
368 | #endif |
369 | ||
0100301b BG |
370 | /* restore callee-saved registers */ |
371 | popq %r15 | |
372 | popq %r14 | |
373 | popq %r13 | |
374 | popq %r12 | |
375 | popq %rbx | |
376 | popq %rbp | |
377 | ||
378 | jmp __switch_to | |
379 | END(__switch_to_asm) | |
380 | ||
1eeb207f DV |
381 | /* |
382 | * A newly forked process directly context switches into this address. | |
383 | * | |
0100301b | 384 | * rax: prev task we switched from |
616d2483 BG |
385 | * rbx: kernel thread func (NULL for user thread) |
386 | * r12: kernel thread arg | |
1eeb207f DV |
387 | */ |
388 | ENTRY(ret_from_fork) | |
8c1f7558 | 389 | UNWIND_HINT_EMPTY |
0100301b | 390 | movq %rax, %rdi |
ebd57499 | 391 | call schedule_tail /* rdi: 'prev' task parameter */ |
1eeb207f | 392 | |
ebd57499 JP |
393 | testq %rbx, %rbx /* from kernel_thread? */ |
394 | jnz 1f /* kernel threads are uncommon */ | |
24d978b7 | 395 | |
616d2483 | 396 | 2: |
8c1f7558 | 397 | UNWIND_HINT_REGS |
ebd57499 | 398 | movq %rsp, %rdi |
24d978b7 AL |
399 | call syscall_return_slowpath /* returns with IRQs disabled */ |
400 | TRACE_IRQS_ON /* user mode is traced as IRQS on */ | |
8a055d7f | 401 | jmp swapgs_restore_regs_and_return_to_usermode |
616d2483 BG |
402 | |
403 | 1: | |
404 | /* kernel thread */ | |
405 | movq %r12, %rdi | |
2641f08b | 406 | CALL_NOSPEC %rbx |
616d2483 BG |
407 | /* |
408 | * A kernel thread is allowed to return here after successfully | |
409 | * calling do_execve(). Exit to userspace to complete the execve() | |
410 | * syscall. | |
411 | */ | |
412 | movq $0, RAX(%rsp) | |
413 | jmp 2b | |
1eeb207f DV |
414 | END(ret_from_fork) |
415 | ||
939b7871 | 416 | /* |
3304c9c3 DV |
417 | * Build the entry stubs with some assembler magic. |
418 | * We pack 1 stub into every 8-byte block. | |
939b7871 | 419 | */ |
3304c9c3 | 420 | .align 8 |
939b7871 | 421 | ENTRY(irq_entries_start) |
3304c9c3 DV |
422 | vector=FIRST_EXTERNAL_VECTOR |
423 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
8c1f7558 | 424 | UNWIND_HINT_IRET_REGS |
4d732138 | 425 | pushq $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 | 426 | jmp common_interrupt |
3304c9c3 | 427 | .align 8 |
8c1f7558 | 428 | vector=vector+1 |
3304c9c3 | 429 | .endr |
939b7871 PA |
430 | END(irq_entries_start) |
431 | ||
1d3e53e8 AL |
432 | .macro DEBUG_ENTRY_ASSERT_IRQS_OFF |
433 | #ifdef CONFIG_DEBUG_ENTRY | |
e17f8234 BO |
434 | pushq %rax |
435 | SAVE_FLAGS(CLBR_RAX) | |
436 | testl $X86_EFLAGS_IF, %eax | |
1d3e53e8 AL |
437 | jz .Lokay_\@ |
438 | ud2 | |
439 | .Lokay_\@: | |
e17f8234 | 440 | popq %rax |
1d3e53e8 AL |
441 | #endif |
442 | .endm | |
443 | ||
444 | /* | |
445 | * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers | |
446 | * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. | |
447 | * Requires kernel GSBASE. | |
448 | * | |
449 | * The invariant is that, if irq_count != -1, then the IRQ stack is in use. | |
450 | */ | |
8c1f7558 | 451 | .macro ENTER_IRQ_STACK regs=1 old_rsp |
1d3e53e8 AL |
452 | DEBUG_ENTRY_ASSERT_IRQS_OFF |
453 | movq %rsp, \old_rsp | |
8c1f7558 JP |
454 | |
455 | .if \regs | |
456 | UNWIND_HINT_REGS base=\old_rsp | |
457 | .endif | |
458 | ||
1d3e53e8 | 459 | incl PER_CPU_VAR(irq_count) |
29955909 | 460 | jnz .Lirq_stack_push_old_rsp_\@ |
1d3e53e8 AL |
461 | |
462 | /* | |
463 | * Right now, if we just incremented irq_count to zero, we've | |
464 | * claimed the IRQ stack but we haven't switched to it yet. | |
465 | * | |
466 | * If anything is added that can interrupt us here without using IST, | |
467 | * it must be *extremely* careful to limit its stack usage. This | |
468 | * could include kprobes and a hypothetical future IST-less #DB | |
469 | * handler. | |
29955909 AL |
470 | * |
471 | * The OOPS unwinder relies on the word at the top of the IRQ | |
472 | * stack linking back to the previous RSP for the entire time we're | |
473 | * on the IRQ stack. For this to work reliably, we need to write | |
474 | * it before we actually move ourselves to the IRQ stack. | |
475 | */ | |
476 | ||
477 | movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) | |
478 | movq PER_CPU_VAR(irq_stack_ptr), %rsp | |
479 | ||
480 | #ifdef CONFIG_DEBUG_ENTRY | |
481 | /* | |
482 | * If the first movq above becomes wrong due to IRQ stack layout | |
483 | * changes, the only way we'll notice is if we try to unwind right | |
484 | * here. Assert that we set up the stack right to catch this type | |
485 | * of bug quickly. | |
1d3e53e8 | 486 | */ |
29955909 AL |
487 | cmpq -8(%rsp), \old_rsp |
488 | je .Lirq_stack_okay\@ | |
489 | ud2 | |
490 | .Lirq_stack_okay\@: | |
491 | #endif | |
1d3e53e8 | 492 | |
29955909 | 493 | .Lirq_stack_push_old_rsp_\@: |
1d3e53e8 | 494 | pushq \old_rsp |
8c1f7558 JP |
495 | |
496 | .if \regs | |
497 | UNWIND_HINT_REGS indirect=1 | |
498 | .endif | |
1d3e53e8 AL |
499 | .endm |
500 | ||
501 | /* | |
502 | * Undoes ENTER_IRQ_STACK. | |
503 | */ | |
8c1f7558 | 504 | .macro LEAVE_IRQ_STACK regs=1 |
1d3e53e8 AL |
505 | DEBUG_ENTRY_ASSERT_IRQS_OFF |
506 | /* We need to be off the IRQ stack before decrementing irq_count. */ | |
507 | popq %rsp | |
508 | ||
8c1f7558 JP |
509 | .if \regs |
510 | UNWIND_HINT_REGS | |
511 | .endif | |
512 | ||
1d3e53e8 AL |
513 | /* |
514 | * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming | |
515 | * the irq stack but we're not on it. | |
516 | */ | |
517 | ||
518 | decl PER_CPU_VAR(irq_count) | |
519 | .endm | |
520 | ||
d99015b1 | 521 | /* |
1da177e4 LT |
522 | * Interrupt entry/exit. |
523 | * | |
524 | * Interrupt entry points save only callee clobbered registers in fast path. | |
d99015b1 AH |
525 | * |
526 | * Entry runs with interrupts off. | |
527 | */ | |
1da177e4 | 528 | |
722024db | 529 | /* 0(%rsp): ~(interrupt number) */ |
1da177e4 | 530 | .macro interrupt func |
f6f64681 | 531 | cld |
7f2590a1 AL |
532 | |
533 | testb $3, CS-ORIG_RAX(%rsp) | |
534 | jz 1f | |
535 | SWAPGS | |
536 | call switch_to_thread_stack | |
537 | 1: | |
538 | ||
3f01daec | 539 | PUSH_AND_CLEAR_REGS |
946c1911 | 540 | ENCODE_FRAME_POINTER |
76f5df43 | 541 | |
ff467594 | 542 | testb $3, CS(%rsp) |
dde74f2e | 543 | jz 1f |
02bc7768 AL |
544 | |
545 | /* | |
7f2590a1 AL |
546 | * IRQ from user mode. |
547 | * | |
f1075053 AL |
548 | * We need to tell lockdep that IRQs are off. We can't do this until |
549 | * we fix gsbase, and we should do it before enter_from_user_mode | |
550 | * (which can take locks). Since TRACE_IRQS_OFF idempotent, | |
551 | * the simplest way to handle it is to just call it twice if | |
552 | * we enter from user mode. There's no reason to optimize this since | |
553 | * TRACE_IRQS_OFF is a no-op if lockdep is off. | |
554 | */ | |
555 | TRACE_IRQS_OFF | |
556 | ||
478dc89c | 557 | CALL_enter_from_user_mode |
02bc7768 | 558 | |
76f5df43 | 559 | 1: |
1d3e53e8 | 560 | ENTER_IRQ_STACK old_rsp=%rdi |
f6f64681 DV |
561 | /* We entered an interrupt context - irqs are off: */ |
562 | TRACE_IRQS_OFF | |
563 | ||
a586f98e | 564 | call \func /* rdi points to pt_regs */ |
1da177e4 LT |
565 | .endm |
566 | ||
722024db AH |
567 | /* |
568 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
569 | * then jump to common_interrupt. | |
570 | */ | |
939b7871 PA |
571 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
572 | common_interrupt: | |
ee4eb87b | 573 | ASM_CLAC |
4d732138 | 574 | addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ |
1da177e4 | 575 | interrupt do_IRQ |
34061f13 | 576 | /* 0(%rsp): old RSP */ |
7effaa88 | 577 | ret_from_intr: |
2140a994 | 578 | DISABLE_INTERRUPTS(CLBR_ANY) |
2601e64d | 579 | TRACE_IRQS_OFF |
625dbc3b | 580 | |
1d3e53e8 | 581 | LEAVE_IRQ_STACK |
625dbc3b | 582 | |
03335e95 | 583 | testb $3, CS(%rsp) |
dde74f2e | 584 | jz retint_kernel |
4d732138 | 585 | |
02bc7768 | 586 | /* Interrupt came from user space */ |
02bc7768 AL |
587 | GLOBAL(retint_user) |
588 | mov %rsp,%rdi | |
589 | call prepare_exit_to_usermode | |
2601e64d | 590 | TRACE_IRQS_IRETQ |
26c4ef9c | 591 | |
8a055d7f | 592 | GLOBAL(swapgs_restore_regs_and_return_to_usermode) |
26c4ef9c AL |
593 | #ifdef CONFIG_DEBUG_ENTRY |
594 | /* Assert that pt_regs indicates user mode. */ | |
1e4c4f61 | 595 | testb $3, CS(%rsp) |
26c4ef9c AL |
596 | jnz 1f |
597 | ud2 | |
598 | 1: | |
599 | #endif | |
502af0d7 | 600 | POP_REGS pop_rdi=0 |
3e3b9293 AL |
601 | |
602 | /* | |
603 | * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. | |
604 | * Save old stack pointer and switch to trampoline stack. | |
605 | */ | |
606 | movq %rsp, %rdi | |
c482feef | 607 | movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp |
3e3b9293 AL |
608 | |
609 | /* Copy the IRET frame to the trampoline stack. */ | |
610 | pushq 6*8(%rdi) /* SS */ | |
611 | pushq 5*8(%rdi) /* RSP */ | |
612 | pushq 4*8(%rdi) /* EFLAGS */ | |
613 | pushq 3*8(%rdi) /* CS */ | |
614 | pushq 2*8(%rdi) /* RIP */ | |
615 | ||
616 | /* Push user RDI on the trampoline stack. */ | |
617 | pushq (%rdi) | |
618 | ||
619 | /* | |
620 | * We are on the trampoline stack. All regs except RDI are live. | |
621 | * We can do future final exit work right here. | |
622 | */ | |
623 | ||
6fd166aa | 624 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
8a09317b | 625 | |
3e3b9293 AL |
626 | /* Restore RDI. */ |
627 | popq %rdi | |
628 | SWAPGS | |
26c4ef9c AL |
629 | INTERRUPT_RETURN |
630 | ||
2601e64d | 631 | |
627276cb | 632 | /* Returning to kernel space */ |
6ba71b76 | 633 | retint_kernel: |
627276cb DV |
634 | #ifdef CONFIG_PREEMPT |
635 | /* Interrupts are off */ | |
636 | /* Check if we need preemption */ | |
4d732138 | 637 | bt $9, EFLAGS(%rsp) /* were interrupts off? */ |
6ba71b76 | 638 | jnc 1f |
4d732138 | 639 | 0: cmpl $0, PER_CPU_VAR(__preempt_count) |
36acef25 | 640 | jnz 1f |
627276cb | 641 | call preempt_schedule_irq |
36acef25 | 642 | jmp 0b |
6ba71b76 | 643 | 1: |
627276cb | 644 | #endif |
2601e64d IM |
645 | /* |
646 | * The iretq could re-enable interrupts: | |
647 | */ | |
648 | TRACE_IRQS_IRETQ | |
fffbb5dc | 649 | |
26c4ef9c AL |
650 | GLOBAL(restore_regs_and_return_to_kernel) |
651 | #ifdef CONFIG_DEBUG_ENTRY | |
652 | /* Assert that pt_regs indicates kernel mode. */ | |
1e4c4f61 | 653 | testb $3, CS(%rsp) |
26c4ef9c AL |
654 | jz 1f |
655 | ud2 | |
656 | 1: | |
657 | #endif | |
502af0d7 | 658 | POP_REGS |
e872045b | 659 | addq $8, %rsp /* skip regs->orig_ax */ |
10bcc80e MD |
660 | /* |
661 | * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization | |
662 | * when returning from IPI handler. | |
663 | */ | |
7209a75d AL |
664 | INTERRUPT_RETURN |
665 | ||
666 | ENTRY(native_iret) | |
8c1f7558 | 667 | UNWIND_HINT_IRET_REGS |
3891a04a PA |
668 | /* |
669 | * Are we returning to a stack segment from the LDT? Note: in | |
670 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
671 | */ | |
34273f41 | 672 | #ifdef CONFIG_X86_ESPFIX64 |
4d732138 IM |
673 | testb $4, (SS-RIP)(%rsp) |
674 | jnz native_irq_return_ldt | |
34273f41 | 675 | #endif |
3891a04a | 676 | |
af726f21 | 677 | .global native_irq_return_iret |
7209a75d | 678 | native_irq_return_iret: |
b645af2d AL |
679 | /* |
680 | * This may fault. Non-paranoid faults on return to userspace are | |
681 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
682 | * Double-faults due to espfix64 are handled in do_double_fault. | |
683 | * Other faults here are fatal. | |
684 | */ | |
1da177e4 | 685 | iretq |
3701d863 | 686 | |
34273f41 | 687 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 688 | native_irq_return_ldt: |
85063fac AL |
689 | /* |
690 | * We are running with user GSBASE. All GPRs contain their user | |
691 | * values. We have a percpu ESPFIX stack that is eight slots | |
692 | * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom | |
693 | * of the ESPFIX stack. | |
694 | * | |
695 | * We clobber RAX and RDI in this code. We stash RDI on the | |
696 | * normal stack and RAX on the ESPFIX stack. | |
697 | * | |
698 | * The ESPFIX stack layout we set up looks like this: | |
699 | * | |
700 | * --- top of ESPFIX stack --- | |
701 | * SS | |
702 | * RSP | |
703 | * RFLAGS | |
704 | * CS | |
705 | * RIP <-- RSP points here when we're done | |
706 | * RAX <-- espfix_waddr points here | |
707 | * --- bottom of ESPFIX stack --- | |
708 | */ | |
709 | ||
710 | pushq %rdi /* Stash user RDI */ | |
8a09317b DH |
711 | SWAPGS /* to kernel GS */ |
712 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ | |
713 | ||
4d732138 | 714 | movq PER_CPU_VAR(espfix_waddr), %rdi |
85063fac AL |
715 | movq %rax, (0*8)(%rdi) /* user RAX */ |
716 | movq (1*8)(%rsp), %rax /* user RIP */ | |
4d732138 | 717 | movq %rax, (1*8)(%rdi) |
85063fac | 718 | movq (2*8)(%rsp), %rax /* user CS */ |
4d732138 | 719 | movq %rax, (2*8)(%rdi) |
85063fac | 720 | movq (3*8)(%rsp), %rax /* user RFLAGS */ |
4d732138 | 721 | movq %rax, (3*8)(%rdi) |
85063fac | 722 | movq (5*8)(%rsp), %rax /* user SS */ |
4d732138 | 723 | movq %rax, (5*8)(%rdi) |
85063fac | 724 | movq (4*8)(%rsp), %rax /* user RSP */ |
4d732138 | 725 | movq %rax, (4*8)(%rdi) |
85063fac AL |
726 | /* Now RAX == RSP. */ |
727 | ||
728 | andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ | |
85063fac AL |
729 | |
730 | /* | |
731 | * espfix_stack[31:16] == 0. The page tables are set up such that | |
732 | * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of | |
733 | * espfix_waddr for any X. That is, there are 65536 RO aliases of | |
734 | * the same page. Set up RSP so that RSP[31:16] contains the | |
735 | * respective 16 bits of the /userspace/ RSP and RSP nonetheless | |
736 | * still points to an RO alias of the ESPFIX stack. | |
737 | */ | |
4d732138 | 738 | orq PER_CPU_VAR(espfix_stack), %rax |
8a09317b | 739 | |
6fd166aa | 740 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
8a09317b DH |
741 | SWAPGS /* to user GS */ |
742 | popq %rdi /* Restore user RDI */ | |
743 | ||
4d732138 | 744 | movq %rax, %rsp |
8c1f7558 | 745 | UNWIND_HINT_IRET_REGS offset=8 |
85063fac AL |
746 | |
747 | /* | |
748 | * At this point, we cannot write to the stack any more, but we can | |
749 | * still read. | |
750 | */ | |
751 | popq %rax /* Restore user RAX */ | |
752 | ||
753 | /* | |
754 | * RSP now points to an ordinary IRET frame, except that the page | |
755 | * is read-only and RSP[31:16] are preloaded with the userspace | |
756 | * values. We can now IRET back to userspace. | |
757 | */ | |
4d732138 | 758 | jmp native_irq_return_iret |
34273f41 | 759 | #endif |
4b787e0b | 760 | END(common_interrupt) |
3891a04a | 761 | |
1da177e4 LT |
762 | /* |
763 | * APIC interrupts. | |
0bd7b798 | 764 | */ |
cf910e83 | 765 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 766 | ENTRY(\sym) |
8c1f7558 | 767 | UNWIND_HINT_IRET_REGS |
ee4eb87b | 768 | ASM_CLAC |
4d732138 | 769 | pushq $~(\num) |
39e95433 | 770 | .Lcommon_\sym: |
322648d1 | 771 | interrupt \do_sym |
4d732138 | 772 | jmp ret_from_intr |
322648d1 AH |
773 | END(\sym) |
774 | .endm | |
1da177e4 | 775 | |
469f0023 | 776 | /* Make sure APIC interrupt handlers end up in the irqentry section: */ |
229a7186 MH |
777 | #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" |
778 | #define POP_SECTION_IRQENTRY .popsection | |
469f0023 | 779 | |
cf910e83 | 780 | .macro apicinterrupt num sym do_sym |
469f0023 | 781 | PUSH_SECTION_IRQENTRY |
cf910e83 | 782 | apicinterrupt3 \num \sym \do_sym |
469f0023 | 783 | POP_SECTION_IRQENTRY |
cf910e83 SA |
784 | .endm |
785 | ||
322648d1 | 786 | #ifdef CONFIG_SMP |
4d732138 IM |
787 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
788 | apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt | |
322648d1 | 789 | #endif |
1da177e4 | 790 | |
03b48632 | 791 | #ifdef CONFIG_X86_UV |
4d732138 | 792 | apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 793 | #endif |
4d732138 IM |
794 | |
795 | apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt | |
796 | apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 797 | |
d78f2664 | 798 | #ifdef CONFIG_HAVE_KVM |
4d732138 IM |
799 | apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
800 | apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi | |
210f84b0 | 801 | apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi |
d78f2664 YZ |
802 | #endif |
803 | ||
33e5ff63 | 804 | #ifdef CONFIG_X86_MCE_THRESHOLD |
4d732138 | 805 | apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
806 | #endif |
807 | ||
24fd78a8 | 808 | #ifdef CONFIG_X86_MCE_AMD |
4d732138 | 809 | apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt |
24fd78a8 AG |
810 | #endif |
811 | ||
33e5ff63 | 812 | #ifdef CONFIG_X86_THERMAL_VECTOR |
4d732138 | 813 | apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt |
33e5ff63 | 814 | #endif |
1812924b | 815 | |
322648d1 | 816 | #ifdef CONFIG_SMP |
4d732138 IM |
817 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt |
818 | apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt | |
819 | apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt | |
322648d1 | 820 | #endif |
1da177e4 | 821 | |
4d732138 IM |
822 | apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt |
823 | apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 824 | |
e360adbe | 825 | #ifdef CONFIG_IRQ_WORK |
4d732138 | 826 | apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt |
241771ef IM |
827 | #endif |
828 | ||
1da177e4 LT |
829 | /* |
830 | * Exception entry points. | |
0bd7b798 | 831 | */ |
c482feef | 832 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) |
577ed45e | 833 | |
7f2590a1 AL |
834 | /* |
835 | * Switch to the thread stack. This is called with the IRET frame and | |
836 | * orig_ax on the stack. (That is, RDI..R12 are not on the stack and | |
837 | * space has not been allocated for them.) | |
838 | */ | |
839 | ENTRY(switch_to_thread_stack) | |
840 | UNWIND_HINT_FUNC | |
841 | ||
842 | pushq %rdi | |
8a09317b DH |
843 | /* Need to switch before accessing the thread stack. */ |
844 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi | |
7f2590a1 AL |
845 | movq %rsp, %rdi |
846 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
847 | UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI | |
848 | ||
849 | pushq 7*8(%rdi) /* regs->ss */ | |
850 | pushq 6*8(%rdi) /* regs->rsp */ | |
851 | pushq 5*8(%rdi) /* regs->eflags */ | |
852 | pushq 4*8(%rdi) /* regs->cs */ | |
853 | pushq 3*8(%rdi) /* regs->ip */ | |
854 | pushq 2*8(%rdi) /* regs->orig_ax */ | |
855 | pushq 8(%rdi) /* return address */ | |
856 | UNWIND_HINT_FUNC | |
857 | ||
858 | movq (%rdi), %rdi | |
859 | ret | |
860 | END(switch_to_thread_stack) | |
577ed45e AL |
861 | |
862 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 863 | ENTRY(\sym) |
98990a33 | 864 | UNWIND_HINT_IRET_REGS offset=\has_error_code*8 |
8c1f7558 | 865 | |
577ed45e AL |
866 | /* Sanity check */ |
867 | .if \shift_ist != -1 && \paranoid == 0 | |
868 | .error "using shift_ist requires paranoid=1" | |
869 | .endif | |
870 | ||
ee4eb87b | 871 | ASM_CLAC |
cb5dd2c5 | 872 | |
82c62fa0 | 873 | .if \has_error_code == 0 |
4d732138 | 874 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
cb5dd2c5 AL |
875 | .endif |
876 | ||
7f2590a1 | 877 | .if \paranoid < 2 |
9e809d15 | 878 | testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ |
7f2590a1 | 879 | jnz .Lfrom_usermode_switch_stack_\@ |
48e08d0f | 880 | .endif |
7f2590a1 AL |
881 | |
882 | .if \paranoid | |
4d732138 | 883 | call paranoid_entry |
cb5dd2c5 | 884 | .else |
4d732138 | 885 | call error_entry |
cb5dd2c5 | 886 | .endif |
8c1f7558 | 887 | UNWIND_HINT_REGS |
ebfc453e | 888 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 889 | |
cb5dd2c5 | 890 | .if \paranoid |
577ed45e | 891 | .if \shift_ist != -1 |
4d732138 | 892 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ |
577ed45e | 893 | .else |
b8b1d08b | 894 | TRACE_IRQS_OFF |
cb5dd2c5 | 895 | .endif |
577ed45e | 896 | .endif |
cb5dd2c5 | 897 | |
4d732138 | 898 | movq %rsp, %rdi /* pt_regs pointer */ |
cb5dd2c5 AL |
899 | |
900 | .if \has_error_code | |
4d732138 IM |
901 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
902 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
cb5dd2c5 | 903 | .else |
4d732138 | 904 | xorl %esi, %esi /* no error code */ |
cb5dd2c5 AL |
905 | .endif |
906 | ||
577ed45e | 907 | .if \shift_ist != -1 |
4d732138 | 908 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
909 | .endif |
910 | ||
4d732138 | 911 | call \do_sym |
cb5dd2c5 | 912 | |
577ed45e | 913 | .if \shift_ist != -1 |
4d732138 | 914 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
915 | .endif |
916 | ||
ebfc453e | 917 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 918 | .if \paranoid |
4d732138 | 919 | jmp paranoid_exit |
cb5dd2c5 | 920 | .else |
4d732138 | 921 | jmp error_exit |
cb5dd2c5 AL |
922 | .endif |
923 | ||
7f2590a1 | 924 | .if \paranoid < 2 |
48e08d0f | 925 | /* |
7f2590a1 | 926 | * Entry from userspace. Switch stacks and treat it |
48e08d0f AL |
927 | * as a normal entry. This means that paranoid handlers |
928 | * run in real process context if user_mode(regs). | |
929 | */ | |
7f2590a1 | 930 | .Lfrom_usermode_switch_stack_\@: |
4d732138 | 931 | call error_entry |
48e08d0f | 932 | |
4d732138 | 933 | movq %rsp, %rdi /* pt_regs pointer */ |
48e08d0f AL |
934 | |
935 | .if \has_error_code | |
4d732138 IM |
936 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
937 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
48e08d0f | 938 | .else |
4d732138 | 939 | xorl %esi, %esi /* no error code */ |
48e08d0f AL |
940 | .endif |
941 | ||
4d732138 | 942 | call \do_sym |
48e08d0f | 943 | |
4d732138 | 944 | jmp error_exit /* %ebx: no swapgs flag */ |
48e08d0f | 945 | .endif |
ddeb8f21 | 946 | END(\sym) |
322648d1 | 947 | .endm |
b8b1d08b | 948 | |
4d732138 IM |
949 | idtentry divide_error do_divide_error has_error_code=0 |
950 | idtentry overflow do_overflow has_error_code=0 | |
951 | idtentry bounds do_bounds has_error_code=0 | |
952 | idtentry invalid_op do_invalid_op has_error_code=0 | |
953 | idtentry device_not_available do_device_not_available has_error_code=0 | |
954 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 | |
955 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 | |
956 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
957 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
958 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
959 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
960 | idtentry alignment_check do_alignment_check has_error_code=1 | |
961 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
962 | ||
963 | ||
964 | /* | |
965 | * Reload gs selector with exception handling | |
966 | * edi: new selector | |
967 | */ | |
9f9d489a | 968 | ENTRY(native_load_gs_index) |
8c1f7558 | 969 | FRAME_BEGIN |
131484c8 | 970 | pushfq |
b8aa287f | 971 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
ca37e57b | 972 | TRACE_IRQS_OFF |
9f1e87ea | 973 | SWAPGS |
42c748bb | 974 | .Lgs_change: |
4d732138 | 975 | movl %edi, %gs |
96e5d28a | 976 | 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE |
72fe4858 | 977 | SWAPGS |
ca37e57b | 978 | TRACE_IRQS_FLAGS (%rsp) |
131484c8 | 979 | popfq |
8c1f7558 | 980 | FRAME_END |
9f1e87ea | 981 | ret |
8c1f7558 | 982 | ENDPROC(native_load_gs_index) |
784d5699 | 983 | EXPORT_SYMBOL(native_load_gs_index) |
0bd7b798 | 984 | |
42c748bb | 985 | _ASM_EXTABLE(.Lgs_change, bad_gs) |
4d732138 | 986 | .section .fixup, "ax" |
1da177e4 | 987 | /* running with kernelgs */ |
0bd7b798 | 988 | bad_gs: |
4d732138 | 989 | SWAPGS /* switch back to user gs */ |
b038c842 AL |
990 | .macro ZAP_GS |
991 | /* This can't be a string because the preprocessor needs to see it. */ | |
992 | movl $__USER_DS, %eax | |
993 | movl %eax, %gs | |
994 | .endm | |
995 | ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG | |
4d732138 IM |
996 | xorl %eax, %eax |
997 | movl %eax, %gs | |
998 | jmp 2b | |
9f1e87ea | 999 | .previous |
0bd7b798 | 1000 | |
2699500b | 1001 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 1002 | ENTRY(do_softirq_own_stack) |
4d732138 IM |
1003 | pushq %rbp |
1004 | mov %rsp, %rbp | |
8c1f7558 | 1005 | ENTER_IRQ_STACK regs=0 old_rsp=%r11 |
4d732138 | 1006 | call __do_softirq |
8c1f7558 | 1007 | LEAVE_IRQ_STACK regs=0 |
2699500b | 1008 | leaveq |
ed6b676c | 1009 | ret |
8c1f7558 | 1010 | ENDPROC(do_softirq_own_stack) |
75154f40 | 1011 | |
3d75e1b8 | 1012 | #ifdef CONFIG_XEN |
5878d5d6 | 1013 | idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
1014 | |
1015 | /* | |
9f1e87ea CG |
1016 | * A note on the "critical region" in our callback handler. |
1017 | * We want to avoid stacking callback handlers due to events occurring | |
1018 | * during handling of the last event. To do this, we keep events disabled | |
1019 | * until we've done all processing. HOWEVER, we must enable events before | |
1020 | * popping the stack frame (can't be done atomically) and so it would still | |
1021 | * be possible to get enough handler activations to overflow the stack. | |
1022 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
1023 | * like to avoid the possibility. | |
1024 | * So, on entry to the handler we detect whether we interrupted an | |
1025 | * existing activation in its critical region -- if so, we pop the current | |
1026 | * activation and restart the handler using the previous one. | |
1027 | */ | |
4d732138 IM |
1028 | ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ |
1029 | ||
9f1e87ea CG |
1030 | /* |
1031 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
1032 | * see the correct pointer to the pt_regs | |
1033 | */ | |
8c1f7558 | 1034 | UNWIND_HINT_FUNC |
4d732138 | 1035 | movq %rdi, %rsp /* we don't return, adjust the stack frame */ |
8c1f7558 | 1036 | UNWIND_HINT_REGS |
1d3e53e8 AL |
1037 | |
1038 | ENTER_IRQ_STACK old_rsp=%r10 | |
4d732138 | 1039 | call xen_evtchn_do_upcall |
1d3e53e8 AL |
1040 | LEAVE_IRQ_STACK |
1041 | ||
fdfd811d | 1042 | #ifndef CONFIG_PREEMPT |
4d732138 | 1043 | call xen_maybe_preempt_hcall |
fdfd811d | 1044 | #endif |
4d732138 | 1045 | jmp error_exit |
371c394a | 1046 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
1047 | |
1048 | /* | |
9f1e87ea CG |
1049 | * Hypervisor uses this for application faults while it executes. |
1050 | * We get here for two reasons: | |
1051 | * 1. Fault while reloading DS, ES, FS or GS | |
1052 | * 2. Fault while executing IRET | |
1053 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
1054 | * registers that could be reloaded and zeroed the others. | |
1055 | * Category 2 we fix up by killing the current process. We cannot use the | |
1056 | * normal Linux return path in this case because if we use the IRET hypercall | |
1057 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
1058 | * We distinguish between categories by comparing each saved segment register | |
1059 | * with its current contents: any discrepancy means we in category 1. | |
1060 | */ | |
3d75e1b8 | 1061 | ENTRY(xen_failsafe_callback) |
8c1f7558 | 1062 | UNWIND_HINT_EMPTY |
4d732138 IM |
1063 | movl %ds, %ecx |
1064 | cmpw %cx, 0x10(%rsp) | |
1065 | jne 1f | |
1066 | movl %es, %ecx | |
1067 | cmpw %cx, 0x18(%rsp) | |
1068 | jne 1f | |
1069 | movl %fs, %ecx | |
1070 | cmpw %cx, 0x20(%rsp) | |
1071 | jne 1f | |
1072 | movl %gs, %ecx | |
1073 | cmpw %cx, 0x28(%rsp) | |
1074 | jne 1f | |
3d75e1b8 | 1075 | /* All segments match their saved values => Category 2 (Bad IRET). */ |
4d732138 IM |
1076 | movq (%rsp), %rcx |
1077 | movq 8(%rsp), %r11 | |
1078 | addq $0x30, %rsp | |
1079 | pushq $0 /* RIP */ | |
8c1f7558 | 1080 | UNWIND_HINT_IRET_REGS offset=8 |
4d732138 | 1081 | jmp general_protection |
3d75e1b8 | 1082 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ |
4d732138 IM |
1083 | movq (%rsp), %rcx |
1084 | movq 8(%rsp), %r11 | |
1085 | addq $0x30, %rsp | |
8c1f7558 | 1086 | UNWIND_HINT_IRET_REGS |
4d732138 | 1087 | pushq $-1 /* orig_ax = -1 => not a system call */ |
3f01daec | 1088 | PUSH_AND_CLEAR_REGS |
946c1911 | 1089 | ENCODE_FRAME_POINTER |
4d732138 | 1090 | jmp error_exit |
3d75e1b8 JF |
1091 | END(xen_failsafe_callback) |
1092 | ||
cf910e83 | 1093 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
1094 | xen_hvm_callback_vector xen_evtchn_do_upcall |
1095 | ||
3d75e1b8 | 1096 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 1097 | |
bc2b0331 | 1098 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 1099 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 | 1100 | hyperv_callback_vector hyperv_vector_handler |
93286261 VK |
1101 | |
1102 | apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ | |
1103 | hyperv_reenlightenment_vector hyperv_reenlightenment_intr | |
bc2b0331 S |
1104 | #endif /* CONFIG_HYPERV */ |
1105 | ||
4d732138 IM |
1106 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
1107 | idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK | |
1108 | idtentry stack_segment do_stack_segment has_error_code=1 | |
1109 | ||
6cac5a92 | 1110 | #ifdef CONFIG_XEN |
43e41110 | 1111 | idtentry xennmi do_nmi has_error_code=0 |
5878d5d6 JG |
1112 | idtentry xendebug do_debug has_error_code=0 |
1113 | idtentry xenint3 do_int3 has_error_code=0 | |
6cac5a92 | 1114 | #endif |
4d732138 IM |
1115 | |
1116 | idtentry general_protection do_general_protection has_error_code=1 | |
11a7ffb0 | 1117 | idtentry page_fault do_page_fault has_error_code=1 |
4d732138 | 1118 | |
631bc487 | 1119 | #ifdef CONFIG_KVM_GUEST |
4d732138 | 1120 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 1121 | #endif |
4d732138 | 1122 | |
ddeb8f21 | 1123 | #ifdef CONFIG_X86_MCE |
6f41c34d | 1124 | idtentry machine_check do_mce has_error_code=0 paranoid=1 |
ddeb8f21 AH |
1125 | #endif |
1126 | ||
ebfc453e | 1127 | /* |
9e809d15 | 1128 | * Save all registers in pt_regs, and switch gs if needed. |
ebfc453e DV |
1129 | * Use slow, but surefire "are we in kernel?" check. |
1130 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
1131 | */ | |
1132 | ENTRY(paranoid_entry) | |
8c1f7558 | 1133 | UNWIND_HINT_FUNC |
1eeb207f | 1134 | cld |
9e809d15 DB |
1135 | PUSH_AND_CLEAR_REGS save_ret=1 |
1136 | ENCODE_FRAME_POINTER 8 | |
4d732138 IM |
1137 | movl $1, %ebx |
1138 | movl $MSR_GS_BASE, %ecx | |
1eeb207f | 1139 | rdmsr |
4d732138 IM |
1140 | testl %edx, %edx |
1141 | js 1f /* negative -> in kernel */ | |
1eeb207f | 1142 | SWAPGS |
4d732138 | 1143 | xorl %ebx, %ebx |
8a09317b DH |
1144 | |
1145 | 1: | |
1146 | SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 | |
1147 | ||
1148 | ret | |
ebfc453e | 1149 | END(paranoid_entry) |
ddeb8f21 | 1150 | |
ebfc453e DV |
1151 | /* |
1152 | * "Paranoid" exit path from exception stack. This is invoked | |
1153 | * only on return from non-NMI IST interrupts that came | |
1154 | * from kernel space. | |
1155 | * | |
1156 | * We may be returning to very strange contexts (e.g. very early | |
1157 | * in syscall entry), so checking for preemption here would | |
1158 | * be complicated. Fortunately, we there's no good reason | |
1159 | * to try to handle preemption here. | |
4d732138 IM |
1160 | * |
1161 | * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) | |
ebfc453e | 1162 | */ |
ddeb8f21 | 1163 | ENTRY(paranoid_exit) |
8c1f7558 | 1164 | UNWIND_HINT_REGS |
2140a994 | 1165 | DISABLE_INTERRUPTS(CLBR_ANY) |
5963e317 | 1166 | TRACE_IRQS_OFF_DEBUG |
4d732138 | 1167 | testl %ebx, %ebx /* swapgs needed? */ |
e5317832 | 1168 | jnz .Lparanoid_exit_no_swapgs |
f2db9382 | 1169 | TRACE_IRQS_IRETQ |
21e94459 | 1170 | RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 |
ddeb8f21 | 1171 | SWAPGS_UNSAFE_STACK |
e5317832 AL |
1172 | jmp .Lparanoid_exit_restore |
1173 | .Lparanoid_exit_no_swapgs: | |
f2db9382 | 1174 | TRACE_IRQS_IRETQ_DEBUG |
e4865757 | 1175 | RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 |
e5317832 AL |
1176 | .Lparanoid_exit_restore: |
1177 | jmp restore_regs_and_return_to_kernel | |
ddeb8f21 AH |
1178 | END(paranoid_exit) |
1179 | ||
1180 | /* | |
9e809d15 | 1181 | * Save all registers in pt_regs, and switch GS if needed. |
539f5113 | 1182 | * Return: EBX=0: came from user mode; EBX=1: otherwise |
ddeb8f21 AH |
1183 | */ |
1184 | ENTRY(error_entry) | |
9e809d15 | 1185 | UNWIND_HINT_FUNC |
ddeb8f21 | 1186 | cld |
9e809d15 DB |
1187 | PUSH_AND_CLEAR_REGS save_ret=1 |
1188 | ENCODE_FRAME_POINTER 8 | |
03335e95 | 1189 | testb $3, CS+8(%rsp) |
cb6f64ed | 1190 | jz .Lerror_kernelspace |
539f5113 | 1191 | |
cb6f64ed AL |
1192 | /* |
1193 | * We entered from user mode or we're pretending to have entered | |
1194 | * from user mode due to an IRET fault. | |
1195 | */ | |
ddeb8f21 | 1196 | SWAPGS |
8a09317b DH |
1197 | /* We have user CR3. Change to kernel CR3. */ |
1198 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax | |
539f5113 | 1199 | |
cb6f64ed | 1200 | .Lerror_entry_from_usermode_after_swapgs: |
7f2590a1 AL |
1201 | /* Put us onto the real thread stack. */ |
1202 | popq %r12 /* save return addr in %12 */ | |
1203 | movq %rsp, %rdi /* arg0 = pt_regs pointer */ | |
1204 | call sync_regs | |
1205 | movq %rax, %rsp /* switch stack */ | |
1206 | ENCODE_FRAME_POINTER | |
1207 | pushq %r12 | |
1208 | ||
f1075053 AL |
1209 | /* |
1210 | * We need to tell lockdep that IRQs are off. We can't do this until | |
1211 | * we fix gsbase, and we should do it before enter_from_user_mode | |
1212 | * (which can take locks). | |
1213 | */ | |
1214 | TRACE_IRQS_OFF | |
478dc89c | 1215 | CALL_enter_from_user_mode |
f1075053 | 1216 | ret |
02bc7768 | 1217 | |
cb6f64ed | 1218 | .Lerror_entry_done: |
ddeb8f21 AH |
1219 | TRACE_IRQS_OFF |
1220 | ret | |
ddeb8f21 | 1221 | |
ebfc453e DV |
1222 | /* |
1223 | * There are two places in the kernel that can potentially fault with | |
1224 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1225 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1226 | * for these here too. | |
1227 | */ | |
cb6f64ed | 1228 | .Lerror_kernelspace: |
4d732138 IM |
1229 | incl %ebx |
1230 | leaq native_irq_return_iret(%rip), %rcx | |
1231 | cmpq %rcx, RIP+8(%rsp) | |
cb6f64ed | 1232 | je .Lerror_bad_iret |
4d732138 IM |
1233 | movl %ecx, %eax /* zero extend */ |
1234 | cmpq %rax, RIP+8(%rsp) | |
cb6f64ed | 1235 | je .Lbstep_iret |
42c748bb | 1236 | cmpq $.Lgs_change, RIP+8(%rsp) |
cb6f64ed | 1237 | jne .Lerror_entry_done |
539f5113 AL |
1238 | |
1239 | /* | |
42c748bb | 1240 | * hack: .Lgs_change can fail with user gsbase. If this happens, fix up |
539f5113 | 1241 | * gsbase and proceed. We'll fix up the exception and land in |
42c748bb | 1242 | * .Lgs_change's error handler with kernel gsbase. |
539f5113 | 1243 | */ |
2fa5f04f | 1244 | SWAPGS |
8a09317b | 1245 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
2fa5f04f | 1246 | jmp .Lerror_entry_done |
ae24ffe5 | 1247 | |
cb6f64ed | 1248 | .Lbstep_iret: |
ae24ffe5 | 1249 | /* Fix truncated RIP */ |
4d732138 | 1250 | movq %rcx, RIP+8(%rsp) |
b645af2d AL |
1251 | /* fall through */ |
1252 | ||
cb6f64ed | 1253 | .Lerror_bad_iret: |
539f5113 | 1254 | /* |
8a09317b DH |
1255 | * We came from an IRET to user mode, so we have user |
1256 | * gsbase and CR3. Switch to kernel gsbase and CR3: | |
539f5113 | 1257 | */ |
b645af2d | 1258 | SWAPGS |
8a09317b | 1259 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
539f5113 AL |
1260 | |
1261 | /* | |
1262 | * Pretend that the exception came from user mode: set up pt_regs | |
1263 | * as if we faulted immediately after IRET and clear EBX so that | |
1264 | * error_exit knows that we will be returning to user mode. | |
1265 | */ | |
4d732138 IM |
1266 | mov %rsp, %rdi |
1267 | call fixup_bad_iret | |
1268 | mov %rax, %rsp | |
539f5113 | 1269 | decl %ebx |
cb6f64ed | 1270 | jmp .Lerror_entry_from_usermode_after_swapgs |
ddeb8f21 AH |
1271 | END(error_entry) |
1272 | ||
1273 | ||
539f5113 | 1274 | /* |
75ca5b22 | 1275 | * On entry, EBX is a "return to kernel mode" flag: |
539f5113 AL |
1276 | * 1: already in kernel mode, don't need SWAPGS |
1277 | * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode | |
1278 | */ | |
ddeb8f21 | 1279 | ENTRY(error_exit) |
8c1f7558 | 1280 | UNWIND_HINT_REGS |
2140a994 | 1281 | DISABLE_INTERRUPTS(CLBR_ANY) |
ddeb8f21 | 1282 | TRACE_IRQS_OFF |
2140a994 | 1283 | testl %ebx, %ebx |
4d732138 IM |
1284 | jnz retint_kernel |
1285 | jmp retint_user | |
ddeb8f21 AH |
1286 | END(error_exit) |
1287 | ||
929bacec AL |
1288 | /* |
1289 | * Runs on exception stack. Xen PV does not go through this path at all, | |
1290 | * so we can use real assembly here. | |
8a09317b DH |
1291 | * |
1292 | * Registers: | |
1293 | * %r14: Used to save/restore the CR3 of the interrupted context | |
1294 | * when PAGE_TABLE_ISOLATION is in use. Do not clobber. | |
929bacec | 1295 | */ |
ddeb8f21 | 1296 | ENTRY(nmi) |
8c1f7558 | 1297 | UNWIND_HINT_IRET_REGS |
929bacec | 1298 | |
3f3c8b8c SR |
1299 | /* |
1300 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1301 | * the iretq it performs will take us out of NMI context. | |
1302 | * This means that we can have nested NMIs where the next | |
1303 | * NMI is using the top of the stack of the previous NMI. We | |
1304 | * can't let it execute because the nested NMI will corrupt the | |
1305 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1306 | * anyway. | |
1307 | * | |
1308 | * To handle this case we do the following: | |
1309 | * Check the a special location on the stack that contains | |
1310 | * a variable that is set when NMIs are executing. | |
1311 | * The interrupted task's stack is also checked to see if it | |
1312 | * is an NMI stack. | |
1313 | * If the variable is not set and the stack is not the NMI | |
1314 | * stack then: | |
1315 | * o Set the special variable on the stack | |
0b22930e AL |
1316 | * o Copy the interrupt frame into an "outermost" location on the |
1317 | * stack | |
1318 | * o Copy the interrupt frame into an "iret" location on the stack | |
3f3c8b8c SR |
1319 | * o Continue processing the NMI |
1320 | * If the variable is set or the previous stack is the NMI stack: | |
0b22930e | 1321 | * o Modify the "iret" location to jump to the repeat_nmi |
3f3c8b8c SR |
1322 | * o return back to the first NMI |
1323 | * | |
1324 | * Now on exit of the first NMI, we first clear the stack variable | |
1325 | * The NMI stack will tell any nested NMIs at that point that it is | |
1326 | * nested. Then we pop the stack normally with iret, and if there was | |
1327 | * a nested NMI that updated the copy interrupt stack frame, a | |
1328 | * jump will be made to the repeat_nmi code that will handle the second | |
1329 | * NMI. | |
9b6e6a83 AL |
1330 | * |
1331 | * However, espfix prevents us from directly returning to userspace | |
1332 | * with a single IRET instruction. Similarly, IRET to user mode | |
1333 | * can fault. We therefore handle NMIs from user space like | |
1334 | * other IST entries. | |
3f3c8b8c SR |
1335 | */ |
1336 | ||
e93c1730 AL |
1337 | ASM_CLAC |
1338 | ||
146b2b09 | 1339 | /* Use %rdx as our temp variable throughout */ |
4d732138 | 1340 | pushq %rdx |
3f3c8b8c | 1341 | |
9b6e6a83 AL |
1342 | testb $3, CS-RIP+8(%rsp) |
1343 | jz .Lnmi_from_kernel | |
1344 | ||
1345 | /* | |
1346 | * NMI from user mode. We need to run on the thread stack, but we | |
1347 | * can't go through the normal entry paths: NMIs are masked, and | |
1348 | * we don't want to enable interrupts, because then we'll end | |
1349 | * up in an awkward situation in which IRQs are on but NMIs | |
1350 | * are off. | |
83c133cf AL |
1351 | * |
1352 | * We also must not push anything to the stack before switching | |
1353 | * stacks lest we corrupt the "NMI executing" variable. | |
9b6e6a83 AL |
1354 | */ |
1355 | ||
929bacec | 1356 | swapgs |
9b6e6a83 | 1357 | cld |
8a09317b | 1358 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx |
9b6e6a83 AL |
1359 | movq %rsp, %rdx |
1360 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
8c1f7558 | 1361 | UNWIND_HINT_IRET_REGS base=%rdx offset=8 |
9b6e6a83 AL |
1362 | pushq 5*8(%rdx) /* pt_regs->ss */ |
1363 | pushq 4*8(%rdx) /* pt_regs->rsp */ | |
1364 | pushq 3*8(%rdx) /* pt_regs->flags */ | |
1365 | pushq 2*8(%rdx) /* pt_regs->cs */ | |
1366 | pushq 1*8(%rdx) /* pt_regs->rip */ | |
8c1f7558 | 1367 | UNWIND_HINT_IRET_REGS |
9b6e6a83 | 1368 | pushq $-1 /* pt_regs->orig_ax */ |
30907fd1 | 1369 | PUSH_AND_CLEAR_REGS rdx=(%rdx) |
946c1911 | 1370 | ENCODE_FRAME_POINTER |
9b6e6a83 AL |
1371 | |
1372 | /* | |
1373 | * At this point we no longer need to worry about stack damage | |
1374 | * due to nesting -- we're on the normal thread stack and we're | |
1375 | * done with the NMI stack. | |
1376 | */ | |
1377 | ||
1378 | movq %rsp, %rdi | |
1379 | movq $-1, %rsi | |
1380 | call do_nmi | |
1381 | ||
45d5a168 | 1382 | /* |
9b6e6a83 | 1383 | * Return back to user mode. We must *not* do the normal exit |
946c1911 | 1384 | * work, because we don't want to enable interrupts. |
45d5a168 | 1385 | */ |
8a055d7f | 1386 | jmp swapgs_restore_regs_and_return_to_usermode |
45d5a168 | 1387 | |
9b6e6a83 | 1388 | .Lnmi_from_kernel: |
3f3c8b8c | 1389 | /* |
0b22930e AL |
1390 | * Here's what our stack frame will look like: |
1391 | * +---------------------------------------------------------+ | |
1392 | * | original SS | | |
1393 | * | original Return RSP | | |
1394 | * | original RFLAGS | | |
1395 | * | original CS | | |
1396 | * | original RIP | | |
1397 | * +---------------------------------------------------------+ | |
1398 | * | temp storage for rdx | | |
1399 | * +---------------------------------------------------------+ | |
1400 | * | "NMI executing" variable | | |
1401 | * +---------------------------------------------------------+ | |
1402 | * | iret SS } Copied from "outermost" frame | | |
1403 | * | iret Return RSP } on each loop iteration; overwritten | | |
1404 | * | iret RFLAGS } by a nested NMI to force another | | |
1405 | * | iret CS } iteration if needed. | | |
1406 | * | iret RIP } | | |
1407 | * +---------------------------------------------------------+ | |
1408 | * | outermost SS } initialized in first_nmi; | | |
1409 | * | outermost Return RSP } will not be changed before | | |
1410 | * | outermost RFLAGS } NMI processing is done. | | |
1411 | * | outermost CS } Copied to "iret" frame on each | | |
1412 | * | outermost RIP } iteration. | | |
1413 | * +---------------------------------------------------------+ | |
1414 | * | pt_regs | | |
1415 | * +---------------------------------------------------------+ | |
1416 | * | |
1417 | * The "original" frame is used by hardware. Before re-enabling | |
1418 | * NMIs, we need to be done with it, and we need to leave enough | |
1419 | * space for the asm code here. | |
1420 | * | |
1421 | * We return by executing IRET while RSP points to the "iret" frame. | |
1422 | * That will either return for real or it will loop back into NMI | |
1423 | * processing. | |
1424 | * | |
1425 | * The "outermost" frame is copied to the "iret" frame on each | |
1426 | * iteration of the loop, so each iteration starts with the "iret" | |
1427 | * frame pointing to the final return target. | |
1428 | */ | |
1429 | ||
45d5a168 | 1430 | /* |
0b22930e AL |
1431 | * Determine whether we're a nested NMI. |
1432 | * | |
a27507ca AL |
1433 | * If we interrupted kernel code between repeat_nmi and |
1434 | * end_repeat_nmi, then we are a nested NMI. We must not | |
1435 | * modify the "iret" frame because it's being written by | |
1436 | * the outer NMI. That's okay; the outer NMI handler is | |
1437 | * about to about to call do_nmi anyway, so we can just | |
1438 | * resume the outer NMI. | |
45d5a168 | 1439 | */ |
a27507ca AL |
1440 | |
1441 | movq $repeat_nmi, %rdx | |
1442 | cmpq 8(%rsp), %rdx | |
1443 | ja 1f | |
1444 | movq $end_repeat_nmi, %rdx | |
1445 | cmpq 8(%rsp), %rdx | |
1446 | ja nested_nmi_out | |
1447 | 1: | |
45d5a168 | 1448 | |
3f3c8b8c | 1449 | /* |
a27507ca | 1450 | * Now check "NMI executing". If it's set, then we're nested. |
0b22930e AL |
1451 | * This will not detect if we interrupted an outer NMI just |
1452 | * before IRET. | |
3f3c8b8c | 1453 | */ |
4d732138 IM |
1454 | cmpl $1, -8(%rsp) |
1455 | je nested_nmi | |
3f3c8b8c SR |
1456 | |
1457 | /* | |
0b22930e AL |
1458 | * Now test if the previous stack was an NMI stack. This covers |
1459 | * the case where we interrupt an outer NMI after it clears | |
810bc075 AL |
1460 | * "NMI executing" but before IRET. We need to be careful, though: |
1461 | * there is one case in which RSP could point to the NMI stack | |
1462 | * despite there being no NMI active: naughty userspace controls | |
1463 | * RSP at the very beginning of the SYSCALL targets. We can | |
1464 | * pull a fast one on naughty userspace, though: we program | |
1465 | * SYSCALL to mask DF, so userspace cannot cause DF to be set | |
1466 | * if it controls the kernel's RSP. We set DF before we clear | |
1467 | * "NMI executing". | |
3f3c8b8c | 1468 | */ |
0784b364 DV |
1469 | lea 6*8(%rsp), %rdx |
1470 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1471 | cmpq %rdx, 4*8(%rsp) | |
1472 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1473 | ja first_nmi | |
4d732138 | 1474 | |
0784b364 DV |
1475 | subq $EXCEPTION_STKSZ, %rdx |
1476 | cmpq %rdx, 4*8(%rsp) | |
1477 | /* If it is below the NMI stack, it is a normal NMI */ | |
1478 | jb first_nmi | |
810bc075 AL |
1479 | |
1480 | /* Ah, it is within the NMI stack. */ | |
1481 | ||
1482 | testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) | |
1483 | jz first_nmi /* RSP was user controlled. */ | |
1484 | ||
1485 | /* This is a nested NMI. */ | |
0784b364 | 1486 | |
3f3c8b8c SR |
1487 | nested_nmi: |
1488 | /* | |
0b22930e AL |
1489 | * Modify the "iret" frame to point to repeat_nmi, forcing another |
1490 | * iteration of NMI handling. | |
3f3c8b8c | 1491 | */ |
23a781e9 | 1492 | subq $8, %rsp |
4d732138 IM |
1493 | leaq -10*8(%rsp), %rdx |
1494 | pushq $__KERNEL_DS | |
1495 | pushq %rdx | |
131484c8 | 1496 | pushfq |
4d732138 IM |
1497 | pushq $__KERNEL_CS |
1498 | pushq $repeat_nmi | |
3f3c8b8c SR |
1499 | |
1500 | /* Put stack back */ | |
4d732138 | 1501 | addq $(6*8), %rsp |
3f3c8b8c SR |
1502 | |
1503 | nested_nmi_out: | |
4d732138 | 1504 | popq %rdx |
3f3c8b8c | 1505 | |
0b22930e | 1506 | /* We are returning to kernel mode, so this cannot result in a fault. */ |
929bacec | 1507 | iretq |
3f3c8b8c SR |
1508 | |
1509 | first_nmi: | |
0b22930e | 1510 | /* Restore rdx. */ |
4d732138 | 1511 | movq (%rsp), %rdx |
62610913 | 1512 | |
36f1a77b AL |
1513 | /* Make room for "NMI executing". */ |
1514 | pushq $0 | |
3f3c8b8c | 1515 | |
0b22930e | 1516 | /* Leave room for the "iret" frame */ |
4d732138 | 1517 | subq $(5*8), %rsp |
28696f43 | 1518 | |
0b22930e | 1519 | /* Copy the "original" frame to the "outermost" frame */ |
3f3c8b8c | 1520 | .rept 5 |
4d732138 | 1521 | pushq 11*8(%rsp) |
3f3c8b8c | 1522 | .endr |
8c1f7558 | 1523 | UNWIND_HINT_IRET_REGS |
62610913 | 1524 | |
79fb4ad6 SR |
1525 | /* Everything up to here is safe from nested NMIs */ |
1526 | ||
a97439aa AL |
1527 | #ifdef CONFIG_DEBUG_ENTRY |
1528 | /* | |
1529 | * For ease of testing, unmask NMIs right away. Disabled by | |
1530 | * default because IRET is very expensive. | |
1531 | */ | |
1532 | pushq $0 /* SS */ | |
1533 | pushq %rsp /* RSP (minus 8 because of the previous push) */ | |
1534 | addq $8, (%rsp) /* Fix up RSP */ | |
1535 | pushfq /* RFLAGS */ | |
1536 | pushq $__KERNEL_CS /* CS */ | |
1537 | pushq $1f /* RIP */ | |
929bacec | 1538 | iretq /* continues at repeat_nmi below */ |
8c1f7558 | 1539 | UNWIND_HINT_IRET_REGS |
a97439aa AL |
1540 | 1: |
1541 | #endif | |
1542 | ||
0b22930e | 1543 | repeat_nmi: |
62610913 JB |
1544 | /* |
1545 | * If there was a nested NMI, the first NMI's iret will return | |
1546 | * here. But NMIs are still enabled and we can take another | |
1547 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1548 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1549 | * it will just return, as we are about to repeat an NMI anyway. | |
1550 | * This makes it safe to copy to the stack frame that a nested | |
1551 | * NMI will update. | |
0b22930e AL |
1552 | * |
1553 | * RSP is pointing to "outermost RIP". gsbase is unknown, but, if | |
1554 | * we're repeating an NMI, gsbase has the same value that it had on | |
1555 | * the first iteration. paranoid_entry will load the kernel | |
36f1a77b AL |
1556 | * gsbase if needed before we call do_nmi. "NMI executing" |
1557 | * is zero. | |
62610913 | 1558 | */ |
36f1a77b | 1559 | movq $1, 10*8(%rsp) /* Set "NMI executing". */ |
3f3c8b8c | 1560 | |
62610913 | 1561 | /* |
0b22930e AL |
1562 | * Copy the "outermost" frame to the "iret" frame. NMIs that nest |
1563 | * here must not modify the "iret" frame while we're writing to | |
1564 | * it or it will end up containing garbage. | |
62610913 | 1565 | */ |
4d732138 | 1566 | addq $(10*8), %rsp |
3f3c8b8c | 1567 | .rept 5 |
4d732138 | 1568 | pushq -6*8(%rsp) |
3f3c8b8c | 1569 | .endr |
4d732138 | 1570 | subq $(5*8), %rsp |
62610913 | 1571 | end_repeat_nmi: |
3f3c8b8c SR |
1572 | |
1573 | /* | |
0b22930e AL |
1574 | * Everything below this point can be preempted by a nested NMI. |
1575 | * If this happens, then the inner NMI will change the "iret" | |
1576 | * frame to point back to repeat_nmi. | |
3f3c8b8c | 1577 | */ |
4d732138 | 1578 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 | 1579 | |
1fd466ef | 1580 | /* |
ebfc453e | 1581 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1582 | * as we should not be calling schedule in NMI context. |
1583 | * Even with normal interrupts enabled. An NMI should not be | |
1584 | * setting NEED_RESCHED or anything that normal interrupts and | |
1585 | * exceptions might do. | |
1586 | */ | |
4d732138 | 1587 | call paranoid_entry |
8c1f7558 | 1588 | UNWIND_HINT_REGS |
7fbb98c5 | 1589 | |
ddeb8f21 | 1590 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
4d732138 IM |
1591 | movq %rsp, %rdi |
1592 | movq $-1, %rsi | |
1593 | call do_nmi | |
7fbb98c5 | 1594 | |
21e94459 | 1595 | RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 |
8a09317b | 1596 | |
4d732138 IM |
1597 | testl %ebx, %ebx /* swapgs needed? */ |
1598 | jnz nmi_restore | |
ddeb8f21 AH |
1599 | nmi_swapgs: |
1600 | SWAPGS_UNSAFE_STACK | |
1601 | nmi_restore: | |
502af0d7 | 1602 | POP_REGS |
0b22930e | 1603 | |
471ee483 AL |
1604 | /* |
1605 | * Skip orig_ax and the "outermost" frame to point RSP at the "iret" | |
1606 | * at the "iret" frame. | |
1607 | */ | |
1608 | addq $6*8, %rsp | |
28696f43 | 1609 | |
810bc075 AL |
1610 | /* |
1611 | * Clear "NMI executing". Set DF first so that we can easily | |
1612 | * distinguish the remaining code between here and IRET from | |
929bacec AL |
1613 | * the SYSCALL entry and exit paths. |
1614 | * | |
1615 | * We arguably should just inspect RIP instead, but I (Andy) wrote | |
1616 | * this code when I had the misapprehension that Xen PV supported | |
1617 | * NMIs, and Xen PV would break that approach. | |
810bc075 AL |
1618 | */ |
1619 | std | |
1620 | movq $0, 5*8(%rsp) /* clear "NMI executing" */ | |
0b22930e AL |
1621 | |
1622 | /* | |
929bacec AL |
1623 | * iretq reads the "iret" frame and exits the NMI stack in a |
1624 | * single instruction. We are returning to kernel mode, so this | |
1625 | * cannot result in a fault. Similarly, we don't need to worry | |
1626 | * about espfix64 on the way back to kernel mode. | |
0b22930e | 1627 | */ |
929bacec | 1628 | iretq |
ddeb8f21 AH |
1629 | END(nmi) |
1630 | ||
1631 | ENTRY(ignore_sysret) | |
8c1f7558 | 1632 | UNWIND_HINT_EMPTY |
4d732138 | 1633 | mov $-ENOSYS, %eax |
ddeb8f21 | 1634 | sysret |
ddeb8f21 | 1635 | END(ignore_sysret) |
2deb4be2 AL |
1636 | |
1637 | ENTRY(rewind_stack_do_exit) | |
8c1f7558 | 1638 | UNWIND_HINT_FUNC |
2deb4be2 AL |
1639 | /* Prevent any naive code from trying to unwind to our caller. */ |
1640 | xorl %ebp, %ebp | |
1641 | ||
1642 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rax | |
8c1f7558 JP |
1643 | leaq -PTREGS_SIZE(%rax), %rsp |
1644 | UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE | |
2deb4be2 AL |
1645 | |
1646 | call do_exit | |
2deb4be2 | 1647 | END(rewind_stack_do_exit) |