]>
Commit | Line | Data |
---|---|---|
a7e3ed1e | 1 | /* |
efc9f05d SE |
2 | * Per core/cpu state |
3 | * | |
4 | * Used to coordinate shared registers between HT threads or | |
5 | * among events on a single PMU. | |
a7e3ed1e | 6 | */ |
de0428a7 | 7 | |
c767a54b JP |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
9 | ||
de0428a7 KW |
10 | #include <linux/stddef.h> |
11 | #include <linux/types.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/slab.h> | |
69c60c88 | 14 | #include <linux/export.h> |
aacfbe6a | 15 | #include <linux/nmi.h> |
de0428a7 | 16 | |
3a632cb2 | 17 | #include <asm/cpufeature.h> |
de0428a7 | 18 | #include <asm/hardirq.h> |
ef5f9f47 | 19 | #include <asm/intel-family.h> |
de0428a7 KW |
20 | #include <asm/apic.h> |
21 | ||
27f6d22b | 22 | #include "../perf_event.h" |
a7e3ed1e | 23 | |
f22f54f4 | 24 | /* |
b622d644 | 25 | * Intel PerfMon, used on Core and later. |
f22f54f4 | 26 | */ |
ec75a716 | 27 | static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = |
f22f54f4 | 28 | { |
c3b7cdf1 PE |
29 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
30 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
31 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
32 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
33 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
34 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
35 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
36 | [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ | |
f22f54f4 PZ |
37 | }; |
38 | ||
5c543e3c | 39 | static struct event_constraint intel_core_event_constraints[] __read_mostly = |
f22f54f4 PZ |
40 | { |
41 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
42 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
43 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
44 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
45 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
46 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ | |
47 | EVENT_CONSTRAINT_END | |
48 | }; | |
49 | ||
5c543e3c | 50 | static struct event_constraint intel_core2_event_constraints[] __read_mostly = |
f22f54f4 | 51 | { |
b622d644 PZ |
52 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
53 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 54 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
55 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
56 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
57 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
58 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
59 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
60 | INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ | |
61 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
62 | INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ | |
b622d644 | 63 | INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ |
f22f54f4 PZ |
64 | INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ |
65 | EVENT_CONSTRAINT_END | |
66 | }; | |
67 | ||
5c543e3c | 68 | static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = |
f22f54f4 | 69 | { |
b622d644 PZ |
70 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
71 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 72 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
73 | INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ |
74 | INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ | |
75 | INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ | |
76 | INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ | |
77 | INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ | |
78 | INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ | |
79 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ | |
80 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
81 | EVENT_CONSTRAINT_END | |
82 | }; | |
83 | ||
5c543e3c | 84 | static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = |
a7e3ed1e | 85 | { |
53ad0447 YZ |
86 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
87 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), | |
f20093ee | 88 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), |
a7e3ed1e AK |
89 | EVENT_EXTRA_END |
90 | }; | |
91 | ||
5c543e3c | 92 | static struct event_constraint intel_westmere_event_constraints[] __read_mostly = |
f22f54f4 | 93 | { |
b622d644 PZ |
94 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
95 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 96 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
97 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ |
98 | INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ | |
99 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
d1100770 | 100 | INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ |
f22f54f4 PZ |
101 | EVENT_CONSTRAINT_END |
102 | }; | |
103 | ||
5c543e3c | 104 | static struct event_constraint intel_snb_event_constraints[] __read_mostly = |
b06b3d49 LM |
105 | { |
106 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
107 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 108 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
fd4a5aef SE |
109 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ |
110 | INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ | |
111 | INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
112 | INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ | |
b06b3d49 | 113 | INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ |
b06b3d49 LM |
114 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ |
115 | INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ | |
f8378f52 AK |
116 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ |
117 | INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
93fcf72c | 118 | |
9010ae4a SE |
119 | /* |
120 | * When HT is off these events can only run on the bottom 4 counters | |
121 | * When HT is on, they are impacted by the HT bug and require EXCL access | |
122 | */ | |
93fcf72c MD |
123 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ |
124 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
125 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
126 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
127 | ||
b06b3d49 LM |
128 | EVENT_CONSTRAINT_END |
129 | }; | |
130 | ||
69943182 SE |
131 | static struct event_constraint intel_ivb_event_constraints[] __read_mostly = |
132 | { | |
133 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
134 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
135 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
136 | INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ | |
137 | INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ | |
138 | INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ | |
6113af14 | 139 | INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ |
69943182 SE |
140 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ |
141 | INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ | |
142 | INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ | |
143 | INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
144 | INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ | |
145 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ | |
93fcf72c | 146 | |
9010ae4a SE |
147 | /* |
148 | * When HT is off these events can only run on the bottom 4 counters | |
149 | * When HT is on, they are impacted by the HT bug and require EXCL access | |
150 | */ | |
93fcf72c MD |
151 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ |
152 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
153 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
154 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
155 | ||
69943182 SE |
156 | EVENT_CONSTRAINT_END |
157 | }; | |
158 | ||
5c543e3c | 159 | static struct extra_reg intel_westmere_extra_regs[] __read_mostly = |
a7e3ed1e | 160 | { |
53ad0447 YZ |
161 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
162 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), | |
163 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), | |
f20093ee | 164 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), |
a7e3ed1e AK |
165 | EVENT_EXTRA_END |
166 | }; | |
167 | ||
0af3ac1f AK |
168 | static struct event_constraint intel_v1_event_constraints[] __read_mostly = |
169 | { | |
170 | EVENT_CONSTRAINT_END | |
171 | }; | |
172 | ||
5c543e3c | 173 | static struct event_constraint intel_gen_event_constraints[] __read_mostly = |
f22f54f4 | 174 | { |
b622d644 PZ |
175 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
176 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 177 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
178 | EVENT_CONSTRAINT_END |
179 | }; | |
180 | ||
1fa64180 YZ |
181 | static struct event_constraint intel_slm_event_constraints[] __read_mostly = |
182 | { | |
183 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
184 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
1fa64180 YZ |
185 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ |
186 | EVENT_CONSTRAINT_END | |
187 | }; | |
188 | ||
20f36278 | 189 | static struct event_constraint intel_skl_event_constraints[] = { |
9a92e16f AK |
190 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
191 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
192 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
193 | INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ | |
9010ae4a SE |
194 | |
195 | /* | |
196 | * when HT is off, these can only run on the bottom 4 counters | |
197 | */ | |
198 | INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ | |
199 | INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ | |
200 | INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ | |
201 | INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ | |
202 | INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ | |
203 | ||
9a92e16f AK |
204 | EVENT_CONSTRAINT_END |
205 | }; | |
206 | ||
1e7b9390 | 207 | static struct extra_reg intel_knl_extra_regs[] __read_mostly = { |
9c489fce LO |
208 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), |
209 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), | |
1e7b9390 HC |
210 | EVENT_EXTRA_END |
211 | }; | |
212 | ||
ee89cbc2 | 213 | static struct extra_reg intel_snb_extra_regs[] __read_mostly = { |
53ad0447 YZ |
214 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
215 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), | |
216 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), | |
f20093ee | 217 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), |
f1923820 SE |
218 | EVENT_EXTRA_END |
219 | }; | |
220 | ||
221 | static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { | |
53ad0447 YZ |
222 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
223 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), | |
224 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), | |
f1a52789 | 225 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), |
ee89cbc2 SE |
226 | EVENT_EXTRA_END |
227 | }; | |
228 | ||
9a92e16f AK |
229 | static struct extra_reg intel_skl_extra_regs[] __read_mostly = { |
230 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), | |
231 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), | |
232 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), | |
dfe1f3cb AK |
233 | /* |
234 | * Note the low 8 bits eventsel code is not a continuous field, containing | |
235 | * some #GPing bits. These are masked out. | |
236 | */ | |
237 | INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), | |
9a92e16f AK |
238 | EVENT_EXTRA_END |
239 | }; | |
240 | ||
7f2ee91f IM |
241 | EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); |
242 | EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); | |
243 | EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); | |
f20093ee | 244 | |
20f36278 | 245 | static struct attribute *nhm_events_attrs[] = { |
f20093ee SE |
246 | EVENT_PTR(mem_ld_nhm), |
247 | NULL, | |
248 | }; | |
249 | ||
a39fcae7 AK |
250 | /* |
251 | * topdown events for Intel Core CPUs. | |
252 | * | |
253 | * The events are all in slots, which is a free slot in a 4 wide | |
254 | * pipeline. Some events are already reported in slots, for cycle | |
255 | * events we multiply by the pipeline width (4). | |
256 | * | |
257 | * With Hyper Threading on, topdown metrics are either summed or averaged | |
258 | * between the threads of a core: (count_t0 + count_t1). | |
259 | * | |
260 | * For the average case the metric is always scaled to pipeline width, | |
261 | * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) | |
262 | */ | |
263 | ||
264 | EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, | |
265 | "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ | |
266 | "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ | |
267 | EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); | |
268 | EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, | |
269 | "event=0xe,umask=0x1"); /* uops_issued.any */ | |
270 | EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, | |
271 | "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ | |
272 | EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, | |
273 | "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ | |
274 | EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, | |
275 | "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ | |
276 | "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ | |
277 | EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, | |
278 | "4", "2"); | |
279 | ||
20f36278 | 280 | static struct attribute *snb_events_attrs[] = { |
f20093ee | 281 | EVENT_PTR(mem_ld_snb), |
9ad64c0f | 282 | EVENT_PTR(mem_st_snb), |
a39fcae7 AK |
283 | EVENT_PTR(td_slots_issued), |
284 | EVENT_PTR(td_slots_retired), | |
285 | EVENT_PTR(td_fetch_bubbles), | |
286 | EVENT_PTR(td_total_slots), | |
287 | EVENT_PTR(td_total_slots_scale), | |
288 | EVENT_PTR(td_recovery_bubbles), | |
289 | EVENT_PTR(td_recovery_bubbles_scale), | |
f20093ee SE |
290 | NULL, |
291 | }; | |
292 | ||
3a632cb2 AK |
293 | static struct event_constraint intel_hsw_event_constraints[] = { |
294 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
295 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
296 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
e0fbac1c | 297 | INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ |
3a632cb2 AK |
298 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ |
299 | INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ | |
300 | /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
c420f19b | 301 | INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), |
3a632cb2 | 302 | /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ |
c420f19b | 303 | INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), |
3a632cb2 | 304 | /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ |
c420f19b | 305 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), |
93fcf72c | 306 | |
9010ae4a SE |
307 | /* |
308 | * When HT is off these events can only run on the bottom 4 counters | |
309 | * When HT is on, they are impacted by the HT bug and require EXCL access | |
310 | */ | |
93fcf72c MD |
311 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ |
312 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
313 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
314 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
315 | ||
3a632cb2 AK |
316 | EVENT_CONSTRAINT_END |
317 | }; | |
318 | ||
20f36278 | 319 | static struct event_constraint intel_bdw_event_constraints[] = { |
91f1b705 AK |
320 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
321 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
322 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
323 | INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ | |
b7883a1c | 324 | INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ |
9010ae4a SE |
325 | /* |
326 | * when HT is off, these can only run on the bottom 4 counters | |
327 | */ | |
328 | INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ | |
329 | INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ | |
330 | INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ | |
331 | INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ | |
91f1b705 AK |
332 | EVENT_CONSTRAINT_END |
333 | }; | |
334 | ||
f22f54f4 PZ |
335 | static u64 intel_pmu_event_map(int hw_event) |
336 | { | |
337 | return intel_perfmon_event_map[hw_event]; | |
338 | } | |
339 | ||
9a92e16f AK |
340 | /* |
341 | * Notes on the events: | |
342 | * - data reads do not include code reads (comparable to earlier tables) | |
343 | * - data counts include speculative execution (except L1 write, dtlb, bpu) | |
344 | * - remote node access includes remote memory, remote cache, remote mmio. | |
345 | * - prefetches are not included in the counts. | |
346 | * - icache miss does not include decoded icache | |
347 | */ | |
348 | ||
349 | #define SKL_DEMAND_DATA_RD BIT_ULL(0) | |
350 | #define SKL_DEMAND_RFO BIT_ULL(1) | |
351 | #define SKL_ANY_RESPONSE BIT_ULL(16) | |
352 | #define SKL_SUPPLIER_NONE BIT_ULL(17) | |
353 | #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) | |
354 | #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) | |
355 | #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) | |
356 | #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) | |
357 | #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ | |
358 | SKL_L3_MISS_REMOTE_HOP0_DRAM| \ | |
359 | SKL_L3_MISS_REMOTE_HOP1_DRAM| \ | |
360 | SKL_L3_MISS_REMOTE_HOP2P_DRAM) | |
361 | #define SKL_SPL_HIT BIT_ULL(30) | |
362 | #define SKL_SNOOP_NONE BIT_ULL(31) | |
363 | #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) | |
364 | #define SKL_SNOOP_MISS BIT_ULL(33) | |
365 | #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) | |
366 | #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) | |
367 | #define SKL_SNOOP_HITM BIT_ULL(36) | |
368 | #define SKL_SNOOP_NON_DRAM BIT_ULL(37) | |
369 | #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ | |
370 | SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ | |
371 | SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ | |
372 | SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) | |
373 | #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD | |
374 | #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ | |
375 | SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ | |
376 | SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ | |
377 | SKL_SNOOP_HITM|SKL_SPL_HIT) | |
378 | #define SKL_DEMAND_WRITE SKL_DEMAND_RFO | |
379 | #define SKL_LLC_ACCESS SKL_ANY_RESPONSE | |
380 | #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ | |
381 | SKL_L3_MISS_REMOTE_HOP1_DRAM| \ | |
382 | SKL_L3_MISS_REMOTE_HOP2P_DRAM) | |
383 | ||
384 | static __initconst const u64 skl_hw_cache_event_ids | |
385 | [PERF_COUNT_HW_CACHE_MAX] | |
386 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
387 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
388 | { | |
389 | [ C(L1D ) ] = { | |
390 | [ C(OP_READ) ] = { | |
391 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ | |
392 | [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ | |
393 | }, | |
394 | [ C(OP_WRITE) ] = { | |
395 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ | |
396 | [ C(RESULT_MISS) ] = 0x0, | |
397 | }, | |
398 | [ C(OP_PREFETCH) ] = { | |
399 | [ C(RESULT_ACCESS) ] = 0x0, | |
400 | [ C(RESULT_MISS) ] = 0x0, | |
401 | }, | |
402 | }, | |
403 | [ C(L1I ) ] = { | |
404 | [ C(OP_READ) ] = { | |
405 | [ C(RESULT_ACCESS) ] = 0x0, | |
406 | [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ | |
407 | }, | |
408 | [ C(OP_WRITE) ] = { | |
409 | [ C(RESULT_ACCESS) ] = -1, | |
410 | [ C(RESULT_MISS) ] = -1, | |
411 | }, | |
412 | [ C(OP_PREFETCH) ] = { | |
413 | [ C(RESULT_ACCESS) ] = 0x0, | |
414 | [ C(RESULT_MISS) ] = 0x0, | |
415 | }, | |
416 | }, | |
417 | [ C(LL ) ] = { | |
418 | [ C(OP_READ) ] = { | |
419 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
420 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
421 | }, | |
422 | [ C(OP_WRITE) ] = { | |
423 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
424 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
425 | }, | |
426 | [ C(OP_PREFETCH) ] = { | |
427 | [ C(RESULT_ACCESS) ] = 0x0, | |
428 | [ C(RESULT_MISS) ] = 0x0, | |
429 | }, | |
430 | }, | |
431 | [ C(DTLB) ] = { | |
432 | [ C(OP_READ) ] = { | |
433 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ | |
fb3a5055 | 434 | [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ |
9a92e16f AK |
435 | }, |
436 | [ C(OP_WRITE) ] = { | |
437 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ | |
fb3a5055 | 438 | [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ |
9a92e16f AK |
439 | }, |
440 | [ C(OP_PREFETCH) ] = { | |
441 | [ C(RESULT_ACCESS) ] = 0x0, | |
442 | [ C(RESULT_MISS) ] = 0x0, | |
443 | }, | |
444 | }, | |
445 | [ C(ITLB) ] = { | |
446 | [ C(OP_READ) ] = { | |
447 | [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ | |
448 | [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ | |
449 | }, | |
450 | [ C(OP_WRITE) ] = { | |
451 | [ C(RESULT_ACCESS) ] = -1, | |
452 | [ C(RESULT_MISS) ] = -1, | |
453 | }, | |
454 | [ C(OP_PREFETCH) ] = { | |
455 | [ C(RESULT_ACCESS) ] = -1, | |
456 | [ C(RESULT_MISS) ] = -1, | |
457 | }, | |
458 | }, | |
459 | [ C(BPU ) ] = { | |
460 | [ C(OP_READ) ] = { | |
461 | [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
462 | [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
463 | }, | |
464 | [ C(OP_WRITE) ] = { | |
465 | [ C(RESULT_ACCESS) ] = -1, | |
466 | [ C(RESULT_MISS) ] = -1, | |
467 | }, | |
468 | [ C(OP_PREFETCH) ] = { | |
469 | [ C(RESULT_ACCESS) ] = -1, | |
470 | [ C(RESULT_MISS) ] = -1, | |
471 | }, | |
472 | }, | |
473 | [ C(NODE) ] = { | |
474 | [ C(OP_READ) ] = { | |
475 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
476 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
477 | }, | |
478 | [ C(OP_WRITE) ] = { | |
479 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
480 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
481 | }, | |
482 | [ C(OP_PREFETCH) ] = { | |
483 | [ C(RESULT_ACCESS) ] = 0x0, | |
484 | [ C(RESULT_MISS) ] = 0x0, | |
485 | }, | |
486 | }, | |
487 | }; | |
488 | ||
489 | static __initconst const u64 skl_hw_cache_extra_regs | |
490 | [PERF_COUNT_HW_CACHE_MAX] | |
491 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
492 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
493 | { | |
494 | [ C(LL ) ] = { | |
495 | [ C(OP_READ) ] = { | |
496 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| | |
497 | SKL_LLC_ACCESS|SKL_ANY_SNOOP, | |
498 | [ C(RESULT_MISS) ] = SKL_DEMAND_READ| | |
499 | SKL_L3_MISS|SKL_ANY_SNOOP| | |
500 | SKL_SUPPLIER_NONE, | |
501 | }, | |
502 | [ C(OP_WRITE) ] = { | |
503 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| | |
504 | SKL_LLC_ACCESS|SKL_ANY_SNOOP, | |
505 | [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| | |
506 | SKL_L3_MISS|SKL_ANY_SNOOP| | |
507 | SKL_SUPPLIER_NONE, | |
508 | }, | |
509 | [ C(OP_PREFETCH) ] = { | |
510 | [ C(RESULT_ACCESS) ] = 0x0, | |
511 | [ C(RESULT_MISS) ] = 0x0, | |
512 | }, | |
513 | }, | |
514 | [ C(NODE) ] = { | |
515 | [ C(OP_READ) ] = { | |
516 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| | |
517 | SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, | |
518 | [ C(RESULT_MISS) ] = SKL_DEMAND_READ| | |
519 | SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, | |
520 | }, | |
521 | [ C(OP_WRITE) ] = { | |
522 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| | |
523 | SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, | |
524 | [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| | |
525 | SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, | |
526 | }, | |
527 | [ C(OP_PREFETCH) ] = { | |
528 | [ C(RESULT_ACCESS) ] = 0x0, | |
529 | [ C(RESULT_MISS) ] = 0x0, | |
530 | }, | |
531 | }, | |
532 | }; | |
533 | ||
74e6543f YZ |
534 | #define SNB_DMND_DATA_RD (1ULL << 0) |
535 | #define SNB_DMND_RFO (1ULL << 1) | |
536 | #define SNB_DMND_IFETCH (1ULL << 2) | |
537 | #define SNB_DMND_WB (1ULL << 3) | |
538 | #define SNB_PF_DATA_RD (1ULL << 4) | |
539 | #define SNB_PF_RFO (1ULL << 5) | |
540 | #define SNB_PF_IFETCH (1ULL << 6) | |
541 | #define SNB_LLC_DATA_RD (1ULL << 7) | |
542 | #define SNB_LLC_RFO (1ULL << 8) | |
543 | #define SNB_LLC_IFETCH (1ULL << 9) | |
544 | #define SNB_BUS_LOCKS (1ULL << 10) | |
545 | #define SNB_STRM_ST (1ULL << 11) | |
546 | #define SNB_OTHER (1ULL << 15) | |
547 | #define SNB_RESP_ANY (1ULL << 16) | |
548 | #define SNB_NO_SUPP (1ULL << 17) | |
549 | #define SNB_LLC_HITM (1ULL << 18) | |
550 | #define SNB_LLC_HITE (1ULL << 19) | |
551 | #define SNB_LLC_HITS (1ULL << 20) | |
552 | #define SNB_LLC_HITF (1ULL << 21) | |
553 | #define SNB_LOCAL (1ULL << 22) | |
554 | #define SNB_REMOTE (0xffULL << 23) | |
555 | #define SNB_SNP_NONE (1ULL << 31) | |
556 | #define SNB_SNP_NOT_NEEDED (1ULL << 32) | |
557 | #define SNB_SNP_MISS (1ULL << 33) | |
558 | #define SNB_NO_FWD (1ULL << 34) | |
559 | #define SNB_SNP_FWD (1ULL << 35) | |
560 | #define SNB_HITM (1ULL << 36) | |
561 | #define SNB_NON_DRAM (1ULL << 37) | |
562 | ||
563 | #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) | |
564 | #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) | |
565 | #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) | |
566 | ||
567 | #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ | |
568 | SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ | |
569 | SNB_HITM) | |
570 | ||
571 | #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) | |
572 | #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) | |
573 | ||
574 | #define SNB_L3_ACCESS SNB_RESP_ANY | |
575 | #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) | |
576 | ||
577 | static __initconst const u64 snb_hw_cache_extra_regs | |
578 | [PERF_COUNT_HW_CACHE_MAX] | |
579 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
580 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
581 | { | |
582 | [ C(LL ) ] = { | |
583 | [ C(OP_READ) ] = { | |
584 | [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, | |
585 | [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, | |
586 | }, | |
587 | [ C(OP_WRITE) ] = { | |
588 | [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, | |
589 | [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, | |
590 | }, | |
591 | [ C(OP_PREFETCH) ] = { | |
592 | [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, | |
593 | [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, | |
594 | }, | |
595 | }, | |
596 | [ C(NODE) ] = { | |
597 | [ C(OP_READ) ] = { | |
598 | [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, | |
599 | [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, | |
600 | }, | |
601 | [ C(OP_WRITE) ] = { | |
602 | [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, | |
603 | [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, | |
604 | }, | |
605 | [ C(OP_PREFETCH) ] = { | |
606 | [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, | |
607 | [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, | |
608 | }, | |
609 | }, | |
610 | }; | |
611 | ||
b06b3d49 LM |
612 | static __initconst const u64 snb_hw_cache_event_ids |
613 | [PERF_COUNT_HW_CACHE_MAX] | |
614 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
615 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
616 | { | |
617 | [ C(L1D) ] = { | |
618 | [ C(OP_READ) ] = { | |
619 | [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ | |
620 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ | |
621 | }, | |
622 | [ C(OP_WRITE) ] = { | |
623 | [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ | |
624 | [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ | |
625 | }, | |
626 | [ C(OP_PREFETCH) ] = { | |
627 | [ C(RESULT_ACCESS) ] = 0x0, | |
628 | [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ | |
629 | }, | |
630 | }, | |
631 | [ C(L1I ) ] = { | |
632 | [ C(OP_READ) ] = { | |
633 | [ C(RESULT_ACCESS) ] = 0x0, | |
634 | [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ | |
635 | }, | |
636 | [ C(OP_WRITE) ] = { | |
637 | [ C(RESULT_ACCESS) ] = -1, | |
638 | [ C(RESULT_MISS) ] = -1, | |
639 | }, | |
640 | [ C(OP_PREFETCH) ] = { | |
641 | [ C(RESULT_ACCESS) ] = 0x0, | |
642 | [ C(RESULT_MISS) ] = 0x0, | |
643 | }, | |
644 | }, | |
645 | [ C(LL ) ] = { | |
b06b3d49 | 646 | [ C(OP_READ) ] = { |
63b6a675 | 647 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
b06b3d49 | 648 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
649 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
650 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
651 | }, |
652 | [ C(OP_WRITE) ] = { | |
63b6a675 | 653 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
b06b3d49 | 654 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
655 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ |
656 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
657 | }, |
658 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 659 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
b06b3d49 | 660 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
661 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
662 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
663 | }, |
664 | }, | |
665 | [ C(DTLB) ] = { | |
666 | [ C(OP_READ) ] = { | |
667 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ | |
668 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ | |
669 | }, | |
670 | [ C(OP_WRITE) ] = { | |
671 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ | |
672 | [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ | |
673 | }, | |
674 | [ C(OP_PREFETCH) ] = { | |
675 | [ C(RESULT_ACCESS) ] = 0x0, | |
676 | [ C(RESULT_MISS) ] = 0x0, | |
677 | }, | |
678 | }, | |
679 | [ C(ITLB) ] = { | |
680 | [ C(OP_READ) ] = { | |
681 | [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ | |
682 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ | |
683 | }, | |
684 | [ C(OP_WRITE) ] = { | |
685 | [ C(RESULT_ACCESS) ] = -1, | |
686 | [ C(RESULT_MISS) ] = -1, | |
687 | }, | |
688 | [ C(OP_PREFETCH) ] = { | |
689 | [ C(RESULT_ACCESS) ] = -1, | |
690 | [ C(RESULT_MISS) ] = -1, | |
691 | }, | |
692 | }, | |
693 | [ C(BPU ) ] = { | |
694 | [ C(OP_READ) ] = { | |
695 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
696 | [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
697 | }, | |
698 | [ C(OP_WRITE) ] = { | |
699 | [ C(RESULT_ACCESS) ] = -1, | |
700 | [ C(RESULT_MISS) ] = -1, | |
701 | }, | |
702 | [ C(OP_PREFETCH) ] = { | |
703 | [ C(RESULT_ACCESS) ] = -1, | |
704 | [ C(RESULT_MISS) ] = -1, | |
705 | }, | |
706 | }, | |
89d6c0b5 PZ |
707 | [ C(NODE) ] = { |
708 | [ C(OP_READ) ] = { | |
74e6543f YZ |
709 | [ C(RESULT_ACCESS) ] = 0x01b7, |
710 | [ C(RESULT_MISS) ] = 0x01b7, | |
89d6c0b5 PZ |
711 | }, |
712 | [ C(OP_WRITE) ] = { | |
74e6543f YZ |
713 | [ C(RESULT_ACCESS) ] = 0x01b7, |
714 | [ C(RESULT_MISS) ] = 0x01b7, | |
89d6c0b5 PZ |
715 | }, |
716 | [ C(OP_PREFETCH) ] = { | |
74e6543f YZ |
717 | [ C(RESULT_ACCESS) ] = 0x01b7, |
718 | [ C(RESULT_MISS) ] = 0x01b7, | |
89d6c0b5 PZ |
719 | }, |
720 | }, | |
721 | ||
b06b3d49 LM |
722 | }; |
723 | ||
0f1b5ca2 AK |
724 | /* |
725 | * Notes on the events: | |
726 | * - data reads do not include code reads (comparable to earlier tables) | |
727 | * - data counts include speculative execution (except L1 write, dtlb, bpu) | |
728 | * - remote node access includes remote memory, remote cache, remote mmio. | |
729 | * - prefetches are not included in the counts because they are not | |
730 | * reliably counted. | |
731 | */ | |
732 | ||
733 | #define HSW_DEMAND_DATA_RD BIT_ULL(0) | |
734 | #define HSW_DEMAND_RFO BIT_ULL(1) | |
735 | #define HSW_ANY_RESPONSE BIT_ULL(16) | |
736 | #define HSW_SUPPLIER_NONE BIT_ULL(17) | |
737 | #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) | |
738 | #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) | |
739 | #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) | |
740 | #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) | |
741 | #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ | |
742 | HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ | |
743 | HSW_L3_MISS_REMOTE_HOP2P) | |
744 | #define HSW_SNOOP_NONE BIT_ULL(31) | |
745 | #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) | |
746 | #define HSW_SNOOP_MISS BIT_ULL(33) | |
747 | #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) | |
748 | #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) | |
749 | #define HSW_SNOOP_HITM BIT_ULL(36) | |
750 | #define HSW_SNOOP_NON_DRAM BIT_ULL(37) | |
751 | #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ | |
752 | HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ | |
753 | HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ | |
754 | HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) | |
755 | #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) | |
756 | #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD | |
757 | #define HSW_DEMAND_WRITE HSW_DEMAND_RFO | |
758 | #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ | |
759 | HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) | |
760 | #define HSW_LLC_ACCESS HSW_ANY_RESPONSE | |
761 | ||
91f1b705 AK |
762 | #define BDW_L3_MISS_LOCAL BIT(26) |
763 | #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ | |
764 | HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ | |
765 | HSW_L3_MISS_REMOTE_HOP2P) | |
766 | ||
767 | ||
0f1b5ca2 AK |
768 | static __initconst const u64 hsw_hw_cache_event_ids |
769 | [PERF_COUNT_HW_CACHE_MAX] | |
770 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
771 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
772 | { | |
773 | [ C(L1D ) ] = { | |
774 | [ C(OP_READ) ] = { | |
775 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
776 | [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ | |
777 | }, | |
778 | [ C(OP_WRITE) ] = { | |
779 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
780 | [ C(RESULT_MISS) ] = 0x0, | |
781 | }, | |
782 | [ C(OP_PREFETCH) ] = { | |
783 | [ C(RESULT_ACCESS) ] = 0x0, | |
784 | [ C(RESULT_MISS) ] = 0x0, | |
785 | }, | |
786 | }, | |
787 | [ C(L1I ) ] = { | |
788 | [ C(OP_READ) ] = { | |
789 | [ C(RESULT_ACCESS) ] = 0x0, | |
790 | [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ | |
791 | }, | |
792 | [ C(OP_WRITE) ] = { | |
793 | [ C(RESULT_ACCESS) ] = -1, | |
794 | [ C(RESULT_MISS) ] = -1, | |
795 | }, | |
796 | [ C(OP_PREFETCH) ] = { | |
797 | [ C(RESULT_ACCESS) ] = 0x0, | |
798 | [ C(RESULT_MISS) ] = 0x0, | |
799 | }, | |
800 | }, | |
801 | [ C(LL ) ] = { | |
802 | [ C(OP_READ) ] = { | |
803 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
804 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
805 | }, | |
806 | [ C(OP_WRITE) ] = { | |
807 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
808 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
809 | }, | |
810 | [ C(OP_PREFETCH) ] = { | |
811 | [ C(RESULT_ACCESS) ] = 0x0, | |
812 | [ C(RESULT_MISS) ] = 0x0, | |
813 | }, | |
814 | }, | |
815 | [ C(DTLB) ] = { | |
816 | [ C(OP_READ) ] = { | |
817 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
818 | [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ | |
819 | }, | |
820 | [ C(OP_WRITE) ] = { | |
821 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
822 | [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ | |
823 | }, | |
824 | [ C(OP_PREFETCH) ] = { | |
825 | [ C(RESULT_ACCESS) ] = 0x0, | |
826 | [ C(RESULT_MISS) ] = 0x0, | |
827 | }, | |
828 | }, | |
829 | [ C(ITLB) ] = { | |
830 | [ C(OP_READ) ] = { | |
831 | [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ | |
832 | [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ | |
833 | }, | |
834 | [ C(OP_WRITE) ] = { | |
835 | [ C(RESULT_ACCESS) ] = -1, | |
836 | [ C(RESULT_MISS) ] = -1, | |
837 | }, | |
838 | [ C(OP_PREFETCH) ] = { | |
839 | [ C(RESULT_ACCESS) ] = -1, | |
840 | [ C(RESULT_MISS) ] = -1, | |
841 | }, | |
842 | }, | |
843 | [ C(BPU ) ] = { | |
844 | [ C(OP_READ) ] = { | |
845 | [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
846 | [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
847 | }, | |
848 | [ C(OP_WRITE) ] = { | |
849 | [ C(RESULT_ACCESS) ] = -1, | |
850 | [ C(RESULT_MISS) ] = -1, | |
851 | }, | |
852 | [ C(OP_PREFETCH) ] = { | |
853 | [ C(RESULT_ACCESS) ] = -1, | |
854 | [ C(RESULT_MISS) ] = -1, | |
855 | }, | |
856 | }, | |
857 | [ C(NODE) ] = { | |
858 | [ C(OP_READ) ] = { | |
859 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
860 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
861 | }, | |
862 | [ C(OP_WRITE) ] = { | |
863 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
864 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
865 | }, | |
866 | [ C(OP_PREFETCH) ] = { | |
867 | [ C(RESULT_ACCESS) ] = 0x0, | |
868 | [ C(RESULT_MISS) ] = 0x0, | |
869 | }, | |
870 | }, | |
871 | }; | |
872 | ||
873 | static __initconst const u64 hsw_hw_cache_extra_regs | |
874 | [PERF_COUNT_HW_CACHE_MAX] | |
875 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
876 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
877 | { | |
878 | [ C(LL ) ] = { | |
879 | [ C(OP_READ) ] = { | |
880 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| | |
881 | HSW_LLC_ACCESS, | |
882 | [ C(RESULT_MISS) ] = HSW_DEMAND_READ| | |
883 | HSW_L3_MISS|HSW_ANY_SNOOP, | |
884 | }, | |
885 | [ C(OP_WRITE) ] = { | |
886 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| | |
887 | HSW_LLC_ACCESS, | |
888 | [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| | |
889 | HSW_L3_MISS|HSW_ANY_SNOOP, | |
890 | }, | |
891 | [ C(OP_PREFETCH) ] = { | |
892 | [ C(RESULT_ACCESS) ] = 0x0, | |
893 | [ C(RESULT_MISS) ] = 0x0, | |
894 | }, | |
895 | }, | |
896 | [ C(NODE) ] = { | |
897 | [ C(OP_READ) ] = { | |
898 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| | |
899 | HSW_L3_MISS_LOCAL_DRAM| | |
900 | HSW_SNOOP_DRAM, | |
901 | [ C(RESULT_MISS) ] = HSW_DEMAND_READ| | |
902 | HSW_L3_MISS_REMOTE| | |
903 | HSW_SNOOP_DRAM, | |
904 | }, | |
905 | [ C(OP_WRITE) ] = { | |
906 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| | |
907 | HSW_L3_MISS_LOCAL_DRAM| | |
908 | HSW_SNOOP_DRAM, | |
909 | [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| | |
910 | HSW_L3_MISS_REMOTE| | |
911 | HSW_SNOOP_DRAM, | |
912 | }, | |
913 | [ C(OP_PREFETCH) ] = { | |
914 | [ C(RESULT_ACCESS) ] = 0x0, | |
915 | [ C(RESULT_MISS) ] = 0x0, | |
916 | }, | |
917 | }, | |
918 | }; | |
919 | ||
caaa8be3 | 920 | static __initconst const u64 westmere_hw_cache_event_ids |
f22f54f4 PZ |
921 | [PERF_COUNT_HW_CACHE_MAX] |
922 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
923 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
924 | { | |
925 | [ C(L1D) ] = { | |
926 | [ C(OP_READ) ] = { | |
927 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
928 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
929 | }, | |
930 | [ C(OP_WRITE) ] = { | |
931 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
932 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
933 | }, | |
934 | [ C(OP_PREFETCH) ] = { | |
935 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
936 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
937 | }, | |
938 | }, | |
939 | [ C(L1I ) ] = { | |
940 | [ C(OP_READ) ] = { | |
941 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
942 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
943 | }, | |
944 | [ C(OP_WRITE) ] = { | |
945 | [ C(RESULT_ACCESS) ] = -1, | |
946 | [ C(RESULT_MISS) ] = -1, | |
947 | }, | |
948 | [ C(OP_PREFETCH) ] = { | |
949 | [ C(RESULT_ACCESS) ] = 0x0, | |
950 | [ C(RESULT_MISS) ] = 0x0, | |
951 | }, | |
952 | }, | |
953 | [ C(LL ) ] = { | |
954 | [ C(OP_READ) ] = { | |
63b6a675 | 955 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
e994d7d2 | 956 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
957 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
958 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 959 | }, |
e994d7d2 AK |
960 | /* |
961 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
962 | * on RFO. | |
963 | */ | |
f22f54f4 | 964 | [ C(OP_WRITE) ] = { |
63b6a675 PZ |
965 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
966 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
967 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
e994d7d2 | 968 | [ C(RESULT_MISS) ] = 0x01b7, |
f22f54f4 PZ |
969 | }, |
970 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 971 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
e994d7d2 | 972 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
973 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
974 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
975 | }, |
976 | }, | |
977 | [ C(DTLB) ] = { | |
978 | [ C(OP_READ) ] = { | |
979 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
980 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
981 | }, | |
982 | [ C(OP_WRITE) ] = { | |
983 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
984 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
985 | }, | |
986 | [ C(OP_PREFETCH) ] = { | |
987 | [ C(RESULT_ACCESS) ] = 0x0, | |
988 | [ C(RESULT_MISS) ] = 0x0, | |
989 | }, | |
990 | }, | |
991 | [ C(ITLB) ] = { | |
992 | [ C(OP_READ) ] = { | |
993 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
994 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ | |
995 | }, | |
996 | [ C(OP_WRITE) ] = { | |
997 | [ C(RESULT_ACCESS) ] = -1, | |
998 | [ C(RESULT_MISS) ] = -1, | |
999 | }, | |
1000 | [ C(OP_PREFETCH) ] = { | |
1001 | [ C(RESULT_ACCESS) ] = -1, | |
1002 | [ C(RESULT_MISS) ] = -1, | |
1003 | }, | |
1004 | }, | |
1005 | [ C(BPU ) ] = { | |
1006 | [ C(OP_READ) ] = { | |
1007 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1008 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
1009 | }, | |
1010 | [ C(OP_WRITE) ] = { | |
1011 | [ C(RESULT_ACCESS) ] = -1, | |
1012 | [ C(RESULT_MISS) ] = -1, | |
1013 | }, | |
1014 | [ C(OP_PREFETCH) ] = { | |
1015 | [ C(RESULT_ACCESS) ] = -1, | |
1016 | [ C(RESULT_MISS) ] = -1, | |
1017 | }, | |
1018 | }, | |
89d6c0b5 PZ |
1019 | [ C(NODE) ] = { |
1020 | [ C(OP_READ) ] = { | |
1021 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1022 | [ C(RESULT_MISS) ] = 0x01b7, | |
1023 | }, | |
1024 | [ C(OP_WRITE) ] = { | |
1025 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1026 | [ C(RESULT_MISS) ] = 0x01b7, | |
1027 | }, | |
1028 | [ C(OP_PREFETCH) ] = { | |
1029 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1030 | [ C(RESULT_MISS) ] = 0x01b7, | |
1031 | }, | |
1032 | }, | |
f22f54f4 PZ |
1033 | }; |
1034 | ||
e994d7d2 | 1035 | /* |
63b6a675 PZ |
1036 | * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; |
1037 | * See IA32 SDM Vol 3B 30.6.1.3 | |
e994d7d2 AK |
1038 | */ |
1039 | ||
63b6a675 PZ |
1040 | #define NHM_DMND_DATA_RD (1 << 0) |
1041 | #define NHM_DMND_RFO (1 << 1) | |
1042 | #define NHM_DMND_IFETCH (1 << 2) | |
1043 | #define NHM_DMND_WB (1 << 3) | |
1044 | #define NHM_PF_DATA_RD (1 << 4) | |
1045 | #define NHM_PF_DATA_RFO (1 << 5) | |
1046 | #define NHM_PF_IFETCH (1 << 6) | |
1047 | #define NHM_OFFCORE_OTHER (1 << 7) | |
1048 | #define NHM_UNCORE_HIT (1 << 8) | |
1049 | #define NHM_OTHER_CORE_HIT_SNP (1 << 9) | |
1050 | #define NHM_OTHER_CORE_HITM (1 << 10) | |
1051 | /* reserved */ | |
1052 | #define NHM_REMOTE_CACHE_FWD (1 << 12) | |
1053 | #define NHM_REMOTE_DRAM (1 << 13) | |
1054 | #define NHM_LOCAL_DRAM (1 << 14) | |
1055 | #define NHM_NON_DRAM (1 << 15) | |
1056 | ||
87e24f4b PZ |
1057 | #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) |
1058 | #define NHM_REMOTE (NHM_REMOTE_DRAM) | |
63b6a675 PZ |
1059 | |
1060 | #define NHM_DMND_READ (NHM_DMND_DATA_RD) | |
1061 | #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) | |
1062 | #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) | |
1063 | ||
1064 | #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) | |
87e24f4b | 1065 | #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) |
63b6a675 | 1066 | #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) |
e994d7d2 AK |
1067 | |
1068 | static __initconst const u64 nehalem_hw_cache_extra_regs | |
1069 | [PERF_COUNT_HW_CACHE_MAX] | |
1070 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1071 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1072 | { | |
1073 | [ C(LL ) ] = { | |
1074 | [ C(OP_READ) ] = { | |
63b6a675 PZ |
1075 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, |
1076 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, | |
e994d7d2 AK |
1077 | }, |
1078 | [ C(OP_WRITE) ] = { | |
63b6a675 PZ |
1079 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, |
1080 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, | |
e994d7d2 AK |
1081 | }, |
1082 | [ C(OP_PREFETCH) ] = { | |
63b6a675 PZ |
1083 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, |
1084 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, | |
e994d7d2 | 1085 | }, |
89d6c0b5 PZ |
1086 | }, |
1087 | [ C(NODE) ] = { | |
1088 | [ C(OP_READ) ] = { | |
87e24f4b PZ |
1089 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, |
1090 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, | |
89d6c0b5 PZ |
1091 | }, |
1092 | [ C(OP_WRITE) ] = { | |
87e24f4b PZ |
1093 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, |
1094 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, | |
89d6c0b5 PZ |
1095 | }, |
1096 | [ C(OP_PREFETCH) ] = { | |
87e24f4b PZ |
1097 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, |
1098 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, | |
89d6c0b5 PZ |
1099 | }, |
1100 | }, | |
e994d7d2 AK |
1101 | }; |
1102 | ||
caaa8be3 | 1103 | static __initconst const u64 nehalem_hw_cache_event_ids |
f22f54f4 PZ |
1104 | [PERF_COUNT_HW_CACHE_MAX] |
1105 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1106 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1107 | { | |
1108 | [ C(L1D) ] = { | |
1109 | [ C(OP_READ) ] = { | |
f4929bd3 PZ |
1110 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ |
1111 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
f22f54f4 PZ |
1112 | }, |
1113 | [ C(OP_WRITE) ] = { | |
f4929bd3 PZ |
1114 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ |
1115 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
f22f54f4 PZ |
1116 | }, |
1117 | [ C(OP_PREFETCH) ] = { | |
1118 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
1119 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
1120 | }, | |
1121 | }, | |
1122 | [ C(L1I ) ] = { | |
1123 | [ C(OP_READ) ] = { | |
1124 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
1125 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
1126 | }, | |
1127 | [ C(OP_WRITE) ] = { | |
1128 | [ C(RESULT_ACCESS) ] = -1, | |
1129 | [ C(RESULT_MISS) ] = -1, | |
1130 | }, | |
1131 | [ C(OP_PREFETCH) ] = { | |
1132 | [ C(RESULT_ACCESS) ] = 0x0, | |
1133 | [ C(RESULT_MISS) ] = 0x0, | |
1134 | }, | |
1135 | }, | |
1136 | [ C(LL ) ] = { | |
1137 | [ C(OP_READ) ] = { | |
e994d7d2 AK |
1138 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
1139 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1140 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ | |
1141 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 1142 | }, |
e994d7d2 AK |
1143 | /* |
1144 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
1145 | * on RFO. | |
1146 | */ | |
f22f54f4 | 1147 | [ C(OP_WRITE) ] = { |
e994d7d2 AK |
1148 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
1149 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1150 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
1151 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
1152 | }, |
1153 | [ C(OP_PREFETCH) ] = { | |
e994d7d2 AK |
1154 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
1155 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1156 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ | |
1157 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
1158 | }, |
1159 | }, | |
1160 | [ C(DTLB) ] = { | |
1161 | [ C(OP_READ) ] = { | |
1162 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
1163 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
1164 | }, | |
1165 | [ C(OP_WRITE) ] = { | |
1166 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
1167 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
1168 | }, | |
1169 | [ C(OP_PREFETCH) ] = { | |
1170 | [ C(RESULT_ACCESS) ] = 0x0, | |
1171 | [ C(RESULT_MISS) ] = 0x0, | |
1172 | }, | |
1173 | }, | |
1174 | [ C(ITLB) ] = { | |
1175 | [ C(OP_READ) ] = { | |
1176 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
1177 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ | |
1178 | }, | |
1179 | [ C(OP_WRITE) ] = { | |
1180 | [ C(RESULT_ACCESS) ] = -1, | |
1181 | [ C(RESULT_MISS) ] = -1, | |
1182 | }, | |
1183 | [ C(OP_PREFETCH) ] = { | |
1184 | [ C(RESULT_ACCESS) ] = -1, | |
1185 | [ C(RESULT_MISS) ] = -1, | |
1186 | }, | |
1187 | }, | |
1188 | [ C(BPU ) ] = { | |
1189 | [ C(OP_READ) ] = { | |
1190 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1191 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
1192 | }, | |
1193 | [ C(OP_WRITE) ] = { | |
1194 | [ C(RESULT_ACCESS) ] = -1, | |
1195 | [ C(RESULT_MISS) ] = -1, | |
1196 | }, | |
1197 | [ C(OP_PREFETCH) ] = { | |
1198 | [ C(RESULT_ACCESS) ] = -1, | |
1199 | [ C(RESULT_MISS) ] = -1, | |
1200 | }, | |
1201 | }, | |
89d6c0b5 PZ |
1202 | [ C(NODE) ] = { |
1203 | [ C(OP_READ) ] = { | |
1204 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1205 | [ C(RESULT_MISS) ] = 0x01b7, | |
1206 | }, | |
1207 | [ C(OP_WRITE) ] = { | |
1208 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1209 | [ C(RESULT_MISS) ] = 0x01b7, | |
1210 | }, | |
1211 | [ C(OP_PREFETCH) ] = { | |
1212 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1213 | [ C(RESULT_MISS) ] = 0x01b7, | |
1214 | }, | |
1215 | }, | |
f22f54f4 PZ |
1216 | }; |
1217 | ||
caaa8be3 | 1218 | static __initconst const u64 core2_hw_cache_event_ids |
f22f54f4 PZ |
1219 | [PERF_COUNT_HW_CACHE_MAX] |
1220 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1221 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1222 | { | |
1223 | [ C(L1D) ] = { | |
1224 | [ C(OP_READ) ] = { | |
1225 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
1226 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
1227 | }, | |
1228 | [ C(OP_WRITE) ] = { | |
1229 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
1230 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
1231 | }, | |
1232 | [ C(OP_PREFETCH) ] = { | |
1233 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
1234 | [ C(RESULT_MISS) ] = 0, | |
1235 | }, | |
1236 | }, | |
1237 | [ C(L1I ) ] = { | |
1238 | [ C(OP_READ) ] = { | |
1239 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
1240 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
1241 | }, | |
1242 | [ C(OP_WRITE) ] = { | |
1243 | [ C(RESULT_ACCESS) ] = -1, | |
1244 | [ C(RESULT_MISS) ] = -1, | |
1245 | }, | |
1246 | [ C(OP_PREFETCH) ] = { | |
1247 | [ C(RESULT_ACCESS) ] = 0, | |
1248 | [ C(RESULT_MISS) ] = 0, | |
1249 | }, | |
1250 | }, | |
1251 | [ C(LL ) ] = { | |
1252 | [ C(OP_READ) ] = { | |
1253 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
1254 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
1255 | }, | |
1256 | [ C(OP_WRITE) ] = { | |
1257 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
1258 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
1259 | }, | |
1260 | [ C(OP_PREFETCH) ] = { | |
1261 | [ C(RESULT_ACCESS) ] = 0, | |
1262 | [ C(RESULT_MISS) ] = 0, | |
1263 | }, | |
1264 | }, | |
1265 | [ C(DTLB) ] = { | |
1266 | [ C(OP_READ) ] = { | |
1267 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
1268 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
1269 | }, | |
1270 | [ C(OP_WRITE) ] = { | |
1271 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
1272 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
1273 | }, | |
1274 | [ C(OP_PREFETCH) ] = { | |
1275 | [ C(RESULT_ACCESS) ] = 0, | |
1276 | [ C(RESULT_MISS) ] = 0, | |
1277 | }, | |
1278 | }, | |
1279 | [ C(ITLB) ] = { | |
1280 | [ C(OP_READ) ] = { | |
1281 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1282 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
1283 | }, | |
1284 | [ C(OP_WRITE) ] = { | |
1285 | [ C(RESULT_ACCESS) ] = -1, | |
1286 | [ C(RESULT_MISS) ] = -1, | |
1287 | }, | |
1288 | [ C(OP_PREFETCH) ] = { | |
1289 | [ C(RESULT_ACCESS) ] = -1, | |
1290 | [ C(RESULT_MISS) ] = -1, | |
1291 | }, | |
1292 | }, | |
1293 | [ C(BPU ) ] = { | |
1294 | [ C(OP_READ) ] = { | |
1295 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
1296 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
1297 | }, | |
1298 | [ C(OP_WRITE) ] = { | |
1299 | [ C(RESULT_ACCESS) ] = -1, | |
1300 | [ C(RESULT_MISS) ] = -1, | |
1301 | }, | |
1302 | [ C(OP_PREFETCH) ] = { | |
1303 | [ C(RESULT_ACCESS) ] = -1, | |
1304 | [ C(RESULT_MISS) ] = -1, | |
1305 | }, | |
1306 | }, | |
1307 | }; | |
1308 | ||
caaa8be3 | 1309 | static __initconst const u64 atom_hw_cache_event_ids |
f22f54f4 PZ |
1310 | [PERF_COUNT_HW_CACHE_MAX] |
1311 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1312 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1313 | { | |
1314 | [ C(L1D) ] = { | |
1315 | [ C(OP_READ) ] = { | |
1316 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
1317 | [ C(RESULT_MISS) ] = 0, | |
1318 | }, | |
1319 | [ C(OP_WRITE) ] = { | |
1320 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ | |
1321 | [ C(RESULT_MISS) ] = 0, | |
1322 | }, | |
1323 | [ C(OP_PREFETCH) ] = { | |
1324 | [ C(RESULT_ACCESS) ] = 0x0, | |
1325 | [ C(RESULT_MISS) ] = 0, | |
1326 | }, | |
1327 | }, | |
1328 | [ C(L1I ) ] = { | |
1329 | [ C(OP_READ) ] = { | |
1330 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
1331 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
1332 | }, | |
1333 | [ C(OP_WRITE) ] = { | |
1334 | [ C(RESULT_ACCESS) ] = -1, | |
1335 | [ C(RESULT_MISS) ] = -1, | |
1336 | }, | |
1337 | [ C(OP_PREFETCH) ] = { | |
1338 | [ C(RESULT_ACCESS) ] = 0, | |
1339 | [ C(RESULT_MISS) ] = 0, | |
1340 | }, | |
1341 | }, | |
1342 | [ C(LL ) ] = { | |
1343 | [ C(OP_READ) ] = { | |
1344 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
1345 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
1346 | }, | |
1347 | [ C(OP_WRITE) ] = { | |
1348 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
1349 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
1350 | }, | |
1351 | [ C(OP_PREFETCH) ] = { | |
1352 | [ C(RESULT_ACCESS) ] = 0, | |
1353 | [ C(RESULT_MISS) ] = 0, | |
1354 | }, | |
1355 | }, | |
1356 | [ C(DTLB) ] = { | |
1357 | [ C(OP_READ) ] = { | |
1358 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ | |
1359 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ | |
1360 | }, | |
1361 | [ C(OP_WRITE) ] = { | |
1362 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ | |
1363 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ | |
1364 | }, | |
1365 | [ C(OP_PREFETCH) ] = { | |
1366 | [ C(RESULT_ACCESS) ] = 0, | |
1367 | [ C(RESULT_MISS) ] = 0, | |
1368 | }, | |
1369 | }, | |
1370 | [ C(ITLB) ] = { | |
1371 | [ C(OP_READ) ] = { | |
1372 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1373 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
1374 | }, | |
1375 | [ C(OP_WRITE) ] = { | |
1376 | [ C(RESULT_ACCESS) ] = -1, | |
1377 | [ C(RESULT_MISS) ] = -1, | |
1378 | }, | |
1379 | [ C(OP_PREFETCH) ] = { | |
1380 | [ C(RESULT_ACCESS) ] = -1, | |
1381 | [ C(RESULT_MISS) ] = -1, | |
1382 | }, | |
1383 | }, | |
1384 | [ C(BPU ) ] = { | |
1385 | [ C(OP_READ) ] = { | |
1386 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
1387 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
1388 | }, | |
1389 | [ C(OP_WRITE) ] = { | |
1390 | [ C(RESULT_ACCESS) ] = -1, | |
1391 | [ C(RESULT_MISS) ] = -1, | |
1392 | }, | |
1393 | [ C(OP_PREFETCH) ] = { | |
1394 | [ C(RESULT_ACCESS) ] = -1, | |
1395 | [ C(RESULT_MISS) ] = -1, | |
1396 | }, | |
1397 | }, | |
1398 | }; | |
1399 | ||
eb12b8ec AK |
1400 | EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); |
1401 | EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); | |
1402 | /* no_alloc_cycles.not_delivered */ | |
1403 | EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, | |
1404 | "event=0xca,umask=0x50"); | |
1405 | EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); | |
1406 | /* uops_retired.all */ | |
1407 | EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, | |
1408 | "event=0xc2,umask=0x10"); | |
1409 | /* uops_retired.all */ | |
1410 | EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, | |
1411 | "event=0xc2,umask=0x10"); | |
1412 | ||
1413 | static struct attribute *slm_events_attrs[] = { | |
1414 | EVENT_PTR(td_total_slots_slm), | |
1415 | EVENT_PTR(td_total_slots_scale_slm), | |
1416 | EVENT_PTR(td_fetch_bubbles_slm), | |
1417 | EVENT_PTR(td_fetch_bubbles_scale_slm), | |
1418 | EVENT_PTR(td_slots_issued_slm), | |
1419 | EVENT_PTR(td_slots_retired_slm), | |
1420 | NULL | |
1421 | }; | |
1422 | ||
1fa64180 YZ |
1423 | static struct extra_reg intel_slm_extra_regs[] __read_mostly = |
1424 | { | |
1425 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ | |
06c939c1 | 1426 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), |
ae3f011f | 1427 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), |
1fa64180 YZ |
1428 | EVENT_EXTRA_END |
1429 | }; | |
1430 | ||
1431 | #define SLM_DMND_READ SNB_DMND_DATA_RD | |
1432 | #define SLM_DMND_WRITE SNB_DMND_RFO | |
1433 | #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) | |
1434 | ||
1435 | #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) | |
1436 | #define SLM_LLC_ACCESS SNB_RESP_ANY | |
1437 | #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) | |
1438 | ||
1439 | static __initconst const u64 slm_hw_cache_extra_regs | |
1440 | [PERF_COUNT_HW_CACHE_MAX] | |
1441 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1442 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1443 | { | |
1444 | [ C(LL ) ] = { | |
1445 | [ C(OP_READ) ] = { | |
1446 | [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, | |
6d374056 | 1447 | [ C(RESULT_MISS) ] = 0, |
1fa64180 YZ |
1448 | }, |
1449 | [ C(OP_WRITE) ] = { | |
1450 | [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, | |
1451 | [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, | |
1452 | }, | |
1453 | [ C(OP_PREFETCH) ] = { | |
1454 | [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, | |
1455 | [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, | |
1456 | }, | |
1457 | }, | |
1458 | }; | |
1459 | ||
1460 | static __initconst const u64 slm_hw_cache_event_ids | |
1461 | [PERF_COUNT_HW_CACHE_MAX] | |
1462 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1463 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1464 | { | |
1465 | [ C(L1D) ] = { | |
1466 | [ C(OP_READ) ] = { | |
1467 | [ C(RESULT_ACCESS) ] = 0, | |
1468 | [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ | |
1469 | }, | |
1470 | [ C(OP_WRITE) ] = { | |
1471 | [ C(RESULT_ACCESS) ] = 0, | |
1472 | [ C(RESULT_MISS) ] = 0, | |
1473 | }, | |
1474 | [ C(OP_PREFETCH) ] = { | |
1475 | [ C(RESULT_ACCESS) ] = 0, | |
1476 | [ C(RESULT_MISS) ] = 0, | |
1477 | }, | |
1478 | }, | |
1479 | [ C(L1I ) ] = { | |
1480 | [ C(OP_READ) ] = { | |
1481 | [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ | |
1482 | [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ | |
1483 | }, | |
1484 | [ C(OP_WRITE) ] = { | |
1485 | [ C(RESULT_ACCESS) ] = -1, | |
1486 | [ C(RESULT_MISS) ] = -1, | |
1487 | }, | |
1488 | [ C(OP_PREFETCH) ] = { | |
1489 | [ C(RESULT_ACCESS) ] = 0, | |
1490 | [ C(RESULT_MISS) ] = 0, | |
1491 | }, | |
1492 | }, | |
1493 | [ C(LL ) ] = { | |
1494 | [ C(OP_READ) ] = { | |
1495 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ | |
1496 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
6d374056 | 1497 | [ C(RESULT_MISS) ] = 0, |
1fa64180 YZ |
1498 | }, |
1499 | [ C(OP_WRITE) ] = { | |
1500 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ | |
1501 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1502 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
1503 | [ C(RESULT_MISS) ] = 0x01b7, | |
1504 | }, | |
1505 | [ C(OP_PREFETCH) ] = { | |
1506 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ | |
1507 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1508 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ | |
1509 | [ C(RESULT_MISS) ] = 0x01b7, | |
1510 | }, | |
1511 | }, | |
1512 | [ C(DTLB) ] = { | |
1513 | [ C(OP_READ) ] = { | |
1514 | [ C(RESULT_ACCESS) ] = 0, | |
1515 | [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ | |
1516 | }, | |
1517 | [ C(OP_WRITE) ] = { | |
1518 | [ C(RESULT_ACCESS) ] = 0, | |
1519 | [ C(RESULT_MISS) ] = 0, | |
1520 | }, | |
1521 | [ C(OP_PREFETCH) ] = { | |
1522 | [ C(RESULT_ACCESS) ] = 0, | |
1523 | [ C(RESULT_MISS) ] = 0, | |
1524 | }, | |
1525 | }, | |
1526 | [ C(ITLB) ] = { | |
1527 | [ C(OP_READ) ] = { | |
1528 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
6d374056 | 1529 | [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ |
1fa64180 YZ |
1530 | }, |
1531 | [ C(OP_WRITE) ] = { | |
1532 | [ C(RESULT_ACCESS) ] = -1, | |
1533 | [ C(RESULT_MISS) ] = -1, | |
1534 | }, | |
1535 | [ C(OP_PREFETCH) ] = { | |
1536 | [ C(RESULT_ACCESS) ] = -1, | |
1537 | [ C(RESULT_MISS) ] = -1, | |
1538 | }, | |
1539 | }, | |
1540 | [ C(BPU ) ] = { | |
1541 | [ C(OP_READ) ] = { | |
1542 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
1543 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
1544 | }, | |
1545 | [ C(OP_WRITE) ] = { | |
1546 | [ C(RESULT_ACCESS) ] = -1, | |
1547 | [ C(RESULT_MISS) ] = -1, | |
1548 | }, | |
1549 | [ C(OP_PREFETCH) ] = { | |
1550 | [ C(RESULT_ACCESS) ] = -1, | |
1551 | [ C(RESULT_MISS) ] = -1, | |
1552 | }, | |
1553 | }, | |
1554 | }; | |
1555 | ||
ed827adb KL |
1556 | EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); |
1557 | EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); | |
1558 | /* UOPS_NOT_DELIVERED.ANY */ | |
1559 | EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); | |
1560 | /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ | |
1561 | EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); | |
1562 | /* UOPS_RETIRED.ANY */ | |
1563 | EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); | |
1564 | /* UOPS_ISSUED.ANY */ | |
1565 | EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); | |
1566 | ||
1567 | static struct attribute *glm_events_attrs[] = { | |
1568 | EVENT_PTR(td_total_slots_glm), | |
1569 | EVENT_PTR(td_total_slots_scale_glm), | |
1570 | EVENT_PTR(td_fetch_bubbles_glm), | |
1571 | EVENT_PTR(td_recovery_bubbles_glm), | |
1572 | EVENT_PTR(td_slots_issued_glm), | |
1573 | EVENT_PTR(td_slots_retired_glm), | |
1574 | NULL | |
1575 | }; | |
1576 | ||
8b92c3a7 KL |
1577 | static struct extra_reg intel_glm_extra_regs[] __read_mostly = { |
1578 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ | |
1579 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), | |
1580 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), | |
1581 | EVENT_EXTRA_END | |
1582 | }; | |
1583 | ||
1584 | #define GLM_DEMAND_DATA_RD BIT_ULL(0) | |
1585 | #define GLM_DEMAND_RFO BIT_ULL(1) | |
1586 | #define GLM_ANY_RESPONSE BIT_ULL(16) | |
1587 | #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) | |
1588 | #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD | |
1589 | #define GLM_DEMAND_WRITE GLM_DEMAND_RFO | |
1590 | #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) | |
1591 | #define GLM_LLC_ACCESS GLM_ANY_RESPONSE | |
1592 | #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) | |
1593 | #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) | |
1594 | ||
1595 | static __initconst const u64 glm_hw_cache_event_ids | |
1596 | [PERF_COUNT_HW_CACHE_MAX] | |
1597 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1598 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1599 | [C(L1D)] = { | |
1600 | [C(OP_READ)] = { | |
1601 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1602 | [C(RESULT_MISS)] = 0x0, | |
1603 | }, | |
1604 | [C(OP_WRITE)] = { | |
1605 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1606 | [C(RESULT_MISS)] = 0x0, | |
1607 | }, | |
1608 | [C(OP_PREFETCH)] = { | |
1609 | [C(RESULT_ACCESS)] = 0x0, | |
1610 | [C(RESULT_MISS)] = 0x0, | |
1611 | }, | |
1612 | }, | |
1613 | [C(L1I)] = { | |
1614 | [C(OP_READ)] = { | |
1615 | [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ | |
1616 | [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ | |
1617 | }, | |
1618 | [C(OP_WRITE)] = { | |
1619 | [C(RESULT_ACCESS)] = -1, | |
1620 | [C(RESULT_MISS)] = -1, | |
1621 | }, | |
1622 | [C(OP_PREFETCH)] = { | |
1623 | [C(RESULT_ACCESS)] = 0x0, | |
1624 | [C(RESULT_MISS)] = 0x0, | |
1625 | }, | |
1626 | }, | |
1627 | [C(LL)] = { | |
1628 | [C(OP_READ)] = { | |
1629 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1630 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1631 | }, | |
1632 | [C(OP_WRITE)] = { | |
1633 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1634 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1635 | }, | |
1636 | [C(OP_PREFETCH)] = { | |
1637 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1638 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1639 | }, | |
1640 | }, | |
1641 | [C(DTLB)] = { | |
1642 | [C(OP_READ)] = { | |
1643 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1644 | [C(RESULT_MISS)] = 0x0, | |
1645 | }, | |
1646 | [C(OP_WRITE)] = { | |
1647 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1648 | [C(RESULT_MISS)] = 0x0, | |
1649 | }, | |
1650 | [C(OP_PREFETCH)] = { | |
1651 | [C(RESULT_ACCESS)] = 0x0, | |
1652 | [C(RESULT_MISS)] = 0x0, | |
1653 | }, | |
1654 | }, | |
1655 | [C(ITLB)] = { | |
1656 | [C(OP_READ)] = { | |
1657 | [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1658 | [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ | |
1659 | }, | |
1660 | [C(OP_WRITE)] = { | |
1661 | [C(RESULT_ACCESS)] = -1, | |
1662 | [C(RESULT_MISS)] = -1, | |
1663 | }, | |
1664 | [C(OP_PREFETCH)] = { | |
1665 | [C(RESULT_ACCESS)] = -1, | |
1666 | [C(RESULT_MISS)] = -1, | |
1667 | }, | |
1668 | }, | |
1669 | [C(BPU)] = { | |
1670 | [C(OP_READ)] = { | |
1671 | [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1672 | [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
1673 | }, | |
1674 | [C(OP_WRITE)] = { | |
1675 | [C(RESULT_ACCESS)] = -1, | |
1676 | [C(RESULT_MISS)] = -1, | |
1677 | }, | |
1678 | [C(OP_PREFETCH)] = { | |
1679 | [C(RESULT_ACCESS)] = -1, | |
1680 | [C(RESULT_MISS)] = -1, | |
1681 | }, | |
1682 | }, | |
1683 | }; | |
1684 | ||
1685 | static __initconst const u64 glm_hw_cache_extra_regs | |
1686 | [PERF_COUNT_HW_CACHE_MAX] | |
1687 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1688 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1689 | [C(LL)] = { | |
1690 | [C(OP_READ)] = { | |
1691 | [C(RESULT_ACCESS)] = GLM_DEMAND_READ| | |
1692 | GLM_LLC_ACCESS, | |
1693 | [C(RESULT_MISS)] = GLM_DEMAND_READ| | |
1694 | GLM_LLC_MISS, | |
1695 | }, | |
1696 | [C(OP_WRITE)] = { | |
1697 | [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| | |
1698 | GLM_LLC_ACCESS, | |
1699 | [C(RESULT_MISS)] = GLM_DEMAND_WRITE| | |
1700 | GLM_LLC_MISS, | |
1701 | }, | |
1702 | [C(OP_PREFETCH)] = { | |
1703 | [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| | |
1704 | GLM_LLC_ACCESS, | |
1705 | [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| | |
1706 | GLM_LLC_MISS, | |
1707 | }, | |
1708 | }, | |
1709 | }; | |
1710 | ||
dd0b06b5 KL |
1711 | static __initconst const u64 glp_hw_cache_event_ids |
1712 | [PERF_COUNT_HW_CACHE_MAX] | |
1713 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1714 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1715 | [C(L1D)] = { | |
1716 | [C(OP_READ)] = { | |
1717 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1718 | [C(RESULT_MISS)] = 0x0, | |
1719 | }, | |
1720 | [C(OP_WRITE)] = { | |
1721 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1722 | [C(RESULT_MISS)] = 0x0, | |
1723 | }, | |
1724 | [C(OP_PREFETCH)] = { | |
1725 | [C(RESULT_ACCESS)] = 0x0, | |
1726 | [C(RESULT_MISS)] = 0x0, | |
1727 | }, | |
1728 | }, | |
1729 | [C(L1I)] = { | |
1730 | [C(OP_READ)] = { | |
1731 | [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ | |
1732 | [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ | |
1733 | }, | |
1734 | [C(OP_WRITE)] = { | |
1735 | [C(RESULT_ACCESS)] = -1, | |
1736 | [C(RESULT_MISS)] = -1, | |
1737 | }, | |
1738 | [C(OP_PREFETCH)] = { | |
1739 | [C(RESULT_ACCESS)] = 0x0, | |
1740 | [C(RESULT_MISS)] = 0x0, | |
1741 | }, | |
1742 | }, | |
1743 | [C(LL)] = { | |
1744 | [C(OP_READ)] = { | |
1745 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1746 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1747 | }, | |
1748 | [C(OP_WRITE)] = { | |
1749 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1750 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1751 | }, | |
1752 | [C(OP_PREFETCH)] = { | |
1753 | [C(RESULT_ACCESS)] = 0x0, | |
1754 | [C(RESULT_MISS)] = 0x0, | |
1755 | }, | |
1756 | }, | |
1757 | [C(DTLB)] = { | |
1758 | [C(OP_READ)] = { | |
1759 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1760 | [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ | |
1761 | }, | |
1762 | [C(OP_WRITE)] = { | |
1763 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1764 | [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ | |
1765 | }, | |
1766 | [C(OP_PREFETCH)] = { | |
1767 | [C(RESULT_ACCESS)] = 0x0, | |
1768 | [C(RESULT_MISS)] = 0x0, | |
1769 | }, | |
1770 | }, | |
1771 | [C(ITLB)] = { | |
1772 | [C(OP_READ)] = { | |
1773 | [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1774 | [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ | |
1775 | }, | |
1776 | [C(OP_WRITE)] = { | |
1777 | [C(RESULT_ACCESS)] = -1, | |
1778 | [C(RESULT_MISS)] = -1, | |
1779 | }, | |
1780 | [C(OP_PREFETCH)] = { | |
1781 | [C(RESULT_ACCESS)] = -1, | |
1782 | [C(RESULT_MISS)] = -1, | |
1783 | }, | |
1784 | }, | |
1785 | [C(BPU)] = { | |
1786 | [C(OP_READ)] = { | |
1787 | [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1788 | [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
1789 | }, | |
1790 | [C(OP_WRITE)] = { | |
1791 | [C(RESULT_ACCESS)] = -1, | |
1792 | [C(RESULT_MISS)] = -1, | |
1793 | }, | |
1794 | [C(OP_PREFETCH)] = { | |
1795 | [C(RESULT_ACCESS)] = -1, | |
1796 | [C(RESULT_MISS)] = -1, | |
1797 | }, | |
1798 | }, | |
1799 | }; | |
1800 | ||
1801 | static __initconst const u64 glp_hw_cache_extra_regs | |
1802 | [PERF_COUNT_HW_CACHE_MAX] | |
1803 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1804 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1805 | [C(LL)] = { | |
1806 | [C(OP_READ)] = { | |
1807 | [C(RESULT_ACCESS)] = GLM_DEMAND_READ| | |
1808 | GLM_LLC_ACCESS, | |
1809 | [C(RESULT_MISS)] = GLM_DEMAND_READ| | |
1810 | GLM_LLC_MISS, | |
1811 | }, | |
1812 | [C(OP_WRITE)] = { | |
1813 | [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| | |
1814 | GLM_LLC_ACCESS, | |
1815 | [C(RESULT_MISS)] = GLM_DEMAND_WRITE| | |
1816 | GLM_LLC_MISS, | |
1817 | }, | |
1818 | [C(OP_PREFETCH)] = { | |
1819 | [C(RESULT_ACCESS)] = 0x0, | |
1820 | [C(RESULT_MISS)] = 0x0, | |
1821 | }, | |
1822 | }, | |
1823 | }; | |
1824 | ||
1e7b9390 HC |
1825 | #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ |
1826 | #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ | |
1827 | #define KNL_MCDRAM_LOCAL BIT_ULL(21) | |
1828 | #define KNL_MCDRAM_FAR BIT_ULL(22) | |
1829 | #define KNL_DDR_LOCAL BIT_ULL(23) | |
1830 | #define KNL_DDR_FAR BIT_ULL(24) | |
1831 | #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ | |
1832 | KNL_DDR_LOCAL | KNL_DDR_FAR) | |
1833 | #define KNL_L2_READ SLM_DMND_READ | |
1834 | #define KNL_L2_WRITE SLM_DMND_WRITE | |
1835 | #define KNL_L2_PREFETCH SLM_DMND_PREFETCH | |
1836 | #define KNL_L2_ACCESS SLM_LLC_ACCESS | |
1837 | #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ | |
1838 | KNL_DRAM_ANY | SNB_SNP_ANY | \ | |
1839 | SNB_NON_DRAM) | |
1840 | ||
1841 | static __initconst const u64 knl_hw_cache_extra_regs | |
1842 | [PERF_COUNT_HW_CACHE_MAX] | |
1843 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1844 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1845 | [C(LL)] = { | |
1846 | [C(OP_READ)] = { | |
1847 | [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, | |
1848 | [C(RESULT_MISS)] = 0, | |
1849 | }, | |
1850 | [C(OP_WRITE)] = { | |
1851 | [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, | |
1852 | [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, | |
1853 | }, | |
1854 | [C(OP_PREFETCH)] = { | |
1855 | [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, | |
1856 | [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, | |
1857 | }, | |
1858 | }, | |
1859 | }; | |
1860 | ||
1a78d937 | 1861 | /* |
c3d266c8 KL |
1862 | * Used from PMIs where the LBRs are already disabled. |
1863 | * | |
1864 | * This function could be called consecutively. It is required to remain in | |
1865 | * disabled state if called consecutively. | |
1866 | * | |
1867 | * During consecutive calls, the same disable value will be written to related | |
cecf6235 AS |
1868 | * registers, so the PMU state remains unchanged. |
1869 | * | |
1870 | * intel_bts events don't coexist with intel PMU's BTS events because of | |
1871 | * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them | |
1872 | * disabled around intel PMU's event batching etc, only inside the PMI handler. | |
1a78d937 AK |
1873 | */ |
1874 | static void __intel_pmu_disable_all(void) | |
f22f54f4 | 1875 | { |
89cbc767 | 1876 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f22f54f4 PZ |
1877 | |
1878 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
1879 | ||
15c7ad51 | 1880 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) |
f22f54f4 | 1881 | intel_pmu_disable_bts(); |
ca037701 PZ |
1882 | |
1883 | intel_pmu_pebs_disable_all(); | |
1a78d937 AK |
1884 | } |
1885 | ||
1886 | static void intel_pmu_disable_all(void) | |
1887 | { | |
1888 | __intel_pmu_disable_all(); | |
caff2bef | 1889 | intel_pmu_lbr_disable_all(); |
f22f54f4 PZ |
1890 | } |
1891 | ||
1a78d937 | 1892 | static void __intel_pmu_enable_all(int added, bool pmi) |
f22f54f4 | 1893 | { |
89cbc767 | 1894 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f22f54f4 | 1895 | |
d329527e | 1896 | intel_pmu_pebs_enable_all(); |
1a78d937 | 1897 | intel_pmu_lbr_enable_all(pmi); |
144d31e6 GN |
1898 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, |
1899 | x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); | |
f22f54f4 | 1900 | |
15c7ad51 | 1901 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { |
f22f54f4 | 1902 | struct perf_event *event = |
15c7ad51 | 1903 | cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
f22f54f4 PZ |
1904 | |
1905 | if (WARN_ON_ONCE(!event)) | |
1906 | return; | |
1907 | ||
1908 | intel_pmu_enable_bts(event->hw.config); | |
cecf6235 | 1909 | } |
f22f54f4 PZ |
1910 | } |
1911 | ||
1a78d937 AK |
1912 | static void intel_pmu_enable_all(int added) |
1913 | { | |
1914 | __intel_pmu_enable_all(added, false); | |
1915 | } | |
1916 | ||
11164cd4 PZ |
1917 | /* |
1918 | * Workaround for: | |
1919 | * Intel Errata AAK100 (model 26) | |
1920 | * Intel Errata AAP53 (model 30) | |
40b91cd1 | 1921 | * Intel Errata BD53 (model 44) |
11164cd4 | 1922 | * |
351af072 ZY |
1923 | * The official story: |
1924 | * These chips need to be 'reset' when adding counters by programming the | |
1925 | * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either | |
1926 | * in sequence on the same PMC or on different PMCs. | |
1927 | * | |
1928 | * In practise it appears some of these events do in fact count, and | |
1929 | * we need to programm all 4 events. | |
11164cd4 | 1930 | */ |
351af072 | 1931 | static void intel_pmu_nhm_workaround(void) |
11164cd4 | 1932 | { |
89cbc767 | 1933 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
351af072 ZY |
1934 | static const unsigned long nhm_magic[4] = { |
1935 | 0x4300B5, | |
1936 | 0x4300D2, | |
1937 | 0x4300B1, | |
1938 | 0x4300B1 | |
1939 | }; | |
1940 | struct perf_event *event; | |
1941 | int i; | |
11164cd4 | 1942 | |
351af072 ZY |
1943 | /* |
1944 | * The Errata requires below steps: | |
1945 | * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; | |
1946 | * 2) Configure 4 PERFEVTSELx with the magic events and clear | |
1947 | * the corresponding PMCx; | |
1948 | * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; | |
1949 | * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; | |
1950 | * 5) Clear 4 pairs of ERFEVTSELx and PMCx; | |
1951 | */ | |
11164cd4 | 1952 | |
351af072 ZY |
1953 | /* |
1954 | * The real steps we choose are a little different from above. | |
1955 | * A) To reduce MSR operations, we don't run step 1) as they | |
1956 | * are already cleared before this function is called; | |
1957 | * B) Call x86_perf_event_update to save PMCx before configuring | |
1958 | * PERFEVTSELx with magic number; | |
1959 | * C) With step 5), we do clear only when the PERFEVTSELx is | |
1960 | * not used currently. | |
1961 | * D) Call x86_perf_event_set_period to restore PMCx; | |
1962 | */ | |
11164cd4 | 1963 | |
351af072 ZY |
1964 | /* We always operate 4 pairs of PERF Counters */ |
1965 | for (i = 0; i < 4; i++) { | |
1966 | event = cpuc->events[i]; | |
1967 | if (event) | |
1968 | x86_perf_event_update(event); | |
1969 | } | |
11164cd4 | 1970 | |
351af072 ZY |
1971 | for (i = 0; i < 4; i++) { |
1972 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); | |
1973 | wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); | |
1974 | } | |
1975 | ||
1976 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); | |
1977 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); | |
11164cd4 | 1978 | |
351af072 ZY |
1979 | for (i = 0; i < 4; i++) { |
1980 | event = cpuc->events[i]; | |
1981 | ||
1982 | if (event) { | |
1983 | x86_perf_event_set_period(event); | |
31fa58af | 1984 | __x86_pmu_enable_event(&event->hw, |
351af072 ZY |
1985 | ARCH_PERFMON_EVENTSEL_ENABLE); |
1986 | } else | |
1987 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); | |
11164cd4 | 1988 | } |
351af072 ZY |
1989 | } |
1990 | ||
1991 | static void intel_pmu_nhm_enable_all(int added) | |
1992 | { | |
1993 | if (added) | |
1994 | intel_pmu_nhm_workaround(); | |
11164cd4 PZ |
1995 | intel_pmu_enable_all(added); |
1996 | } | |
1997 | ||
f22f54f4 PZ |
1998 | static inline u64 intel_pmu_get_status(void) |
1999 | { | |
2000 | u64 status; | |
2001 | ||
2002 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
2003 | ||
2004 | return status; | |
2005 | } | |
2006 | ||
2007 | static inline void intel_pmu_ack_status(u64 ack) | |
2008 | { | |
2009 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
2010 | } | |
2011 | ||
ca037701 | 2012 | static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 2013 | { |
15c7ad51 | 2014 | int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
f22f54f4 PZ |
2015 | u64 ctrl_val, mask; |
2016 | ||
2017 | mask = 0xfULL << (idx * 4); | |
2018 | ||
2019 | rdmsrl(hwc->config_base, ctrl_val); | |
2020 | ctrl_val &= ~mask; | |
7645a24c | 2021 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
2022 | } |
2023 | ||
2b9e344d PZ |
2024 | static inline bool event_is_checkpointed(struct perf_event *event) |
2025 | { | |
2026 | return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; | |
2027 | } | |
2028 | ||
ca037701 | 2029 | static void intel_pmu_disable_event(struct perf_event *event) |
f22f54f4 | 2030 | { |
aff3d91a | 2031 | struct hw_perf_event *hwc = &event->hw; |
89cbc767 | 2032 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
aff3d91a | 2033 | |
15c7ad51 | 2034 | if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { |
f22f54f4 PZ |
2035 | intel_pmu_disable_bts(); |
2036 | intel_pmu_drain_bts_buffer(); | |
2037 | return; | |
2038 | } | |
2039 | ||
144d31e6 GN |
2040 | cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); |
2041 | cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); | |
2b9e344d | 2042 | cpuc->intel_cp_status &= ~(1ull << hwc->idx); |
144d31e6 | 2043 | |
f22f54f4 | 2044 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
aff3d91a | 2045 | intel_pmu_disable_fixed(hwc); |
f22f54f4 PZ |
2046 | return; |
2047 | } | |
2048 | ||
aff3d91a | 2049 | x86_pmu_disable_event(event); |
ca037701 | 2050 | |
ab608344 | 2051 | if (unlikely(event->attr.precise_ip)) |
ef21f683 | 2052 | intel_pmu_pebs_disable(event); |
f22f54f4 PZ |
2053 | } |
2054 | ||
68f7082f PZ |
2055 | static void intel_pmu_del_event(struct perf_event *event) |
2056 | { | |
2057 | if (needs_branch_stack(event)) | |
2058 | intel_pmu_lbr_del(event); | |
2059 | if (event->attr.precise_ip) | |
2060 | intel_pmu_pebs_del(event); | |
2061 | } | |
2062 | ||
ca037701 | 2063 | static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 2064 | { |
15c7ad51 | 2065 | int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
f22f54f4 | 2066 | u64 ctrl_val, bits, mask; |
f22f54f4 PZ |
2067 | |
2068 | /* | |
2069 | * Enable IRQ generation (0x8), | |
2070 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
2071 | * if requested: | |
2072 | */ | |
2073 | bits = 0x8ULL; | |
2074 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
2075 | bits |= 0x2; | |
2076 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
2077 | bits |= 0x1; | |
2078 | ||
2079 | /* | |
2080 | * ANY bit is supported in v3 and up | |
2081 | */ | |
2082 | if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) | |
2083 | bits |= 0x4; | |
2084 | ||
2085 | bits <<= (idx * 4); | |
2086 | mask = 0xfULL << (idx * 4); | |
2087 | ||
2088 | rdmsrl(hwc->config_base, ctrl_val); | |
2089 | ctrl_val &= ~mask; | |
2090 | ctrl_val |= bits; | |
7645a24c | 2091 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
2092 | } |
2093 | ||
aff3d91a | 2094 | static void intel_pmu_enable_event(struct perf_event *event) |
f22f54f4 | 2095 | { |
aff3d91a | 2096 | struct hw_perf_event *hwc = &event->hw; |
89cbc767 | 2097 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
aff3d91a | 2098 | |
15c7ad51 | 2099 | if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { |
0a3aee0d | 2100 | if (!__this_cpu_read(cpu_hw_events.enabled)) |
f22f54f4 PZ |
2101 | return; |
2102 | ||
2103 | intel_pmu_enable_bts(hwc->config); | |
2104 | return; | |
2105 | } | |
2106 | ||
144d31e6 GN |
2107 | if (event->attr.exclude_host) |
2108 | cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); | |
2109 | if (event->attr.exclude_guest) | |
2110 | cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); | |
2111 | ||
2b9e344d PZ |
2112 | if (unlikely(event_is_checkpointed(event))) |
2113 | cpuc->intel_cp_status |= (1ull << hwc->idx); | |
2114 | ||
f22f54f4 | 2115 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
aff3d91a | 2116 | intel_pmu_enable_fixed(hwc); |
f22f54f4 PZ |
2117 | return; |
2118 | } | |
2119 | ||
ab608344 | 2120 | if (unlikely(event->attr.precise_ip)) |
ef21f683 | 2121 | intel_pmu_pebs_enable(event); |
ca037701 | 2122 | |
31fa58af | 2123 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f22f54f4 PZ |
2124 | } |
2125 | ||
68f7082f PZ |
2126 | static void intel_pmu_add_event(struct perf_event *event) |
2127 | { | |
2128 | if (event->attr.precise_ip) | |
2129 | intel_pmu_pebs_add(event); | |
2130 | if (needs_branch_stack(event)) | |
2131 | intel_pmu_lbr_add(event); | |
2132 | } | |
2133 | ||
f22f54f4 PZ |
2134 | /* |
2135 | * Save and restart an expired event. Called by NMI contexts, | |
2136 | * so it has to be careful about preempting normal event ops: | |
2137 | */ | |
de0428a7 | 2138 | int intel_pmu_save_and_restart(struct perf_event *event) |
f22f54f4 | 2139 | { |
cc2ad4ba | 2140 | x86_perf_event_update(event); |
2dbf0116 AK |
2141 | /* |
2142 | * For a checkpointed counter always reset back to 0. This | |
2143 | * avoids a situation where the counter overflows, aborts the | |
2144 | * transaction and is then set back to shortly before the | |
2145 | * overflow, and overflows and aborts again. | |
2146 | */ | |
2147 | if (unlikely(event_is_checkpointed(event))) { | |
2148 | /* No race with NMIs because the counter should not be armed */ | |
2149 | wrmsrl(event->hw.event_base, 0); | |
2150 | local64_set(&event->hw.prev_count, 0); | |
2151 | } | |
cc2ad4ba | 2152 | return x86_perf_event_set_period(event); |
f22f54f4 PZ |
2153 | } |
2154 | ||
2155 | static void intel_pmu_reset(void) | |
2156 | { | |
0a3aee0d | 2157 | struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); |
f22f54f4 PZ |
2158 | unsigned long flags; |
2159 | int idx; | |
2160 | ||
948b1bb8 | 2161 | if (!x86_pmu.num_counters) |
f22f54f4 PZ |
2162 | return; |
2163 | ||
2164 | local_irq_save(flags); | |
2165 | ||
c767a54b | 2166 | pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); |
f22f54f4 | 2167 | |
948b1bb8 | 2168 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
715c85b1 PA |
2169 | wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); |
2170 | wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); | |
f22f54f4 | 2171 | } |
948b1bb8 | 2172 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) |
715c85b1 | 2173 | wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); |
948b1bb8 | 2174 | |
f22f54f4 PZ |
2175 | if (ds) |
2176 | ds->bts_index = ds->bts_buffer_base; | |
2177 | ||
8882edf7 AK |
2178 | /* Ack all overflows and disable fixed counters */ |
2179 | if (x86_pmu.version >= 2) { | |
2180 | intel_pmu_ack_status(intel_pmu_get_status()); | |
2181 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
2182 | } | |
2183 | ||
2184 | /* Reset LBRs and LBR freezing */ | |
2185 | if (x86_pmu.lbr_nr) { | |
2186 | update_debugctlmsr(get_debugctlmsr() & | |
2187 | ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); | |
2188 | } | |
2189 | ||
f22f54f4 PZ |
2190 | local_irq_restore(flags); |
2191 | } | |
2192 | ||
2193 | /* | |
2194 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
2195 | * rules apply: | |
2196 | */ | |
2197 | static int intel_pmu_handle_irq(struct pt_regs *regs) | |
2198 | { | |
2199 | struct perf_sample_data data; | |
2200 | struct cpu_hw_events *cpuc; | |
2201 | int bit, loops; | |
2e556b5b | 2202 | u64 status; |
b0b2072d | 2203 | int handled; |
f22f54f4 | 2204 | |
89cbc767 | 2205 | cpuc = this_cpu_ptr(&cpu_hw_events); |
f22f54f4 | 2206 | |
2bce5dac | 2207 | /* |
72db5596 AK |
2208 | * No known reason to not always do late ACK, |
2209 | * but just in case do it opt-in. | |
2bce5dac | 2210 | */ |
72db5596 AK |
2211 | if (!x86_pmu.late_ack) |
2212 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
cecf6235 | 2213 | intel_bts_disable_local(); |
1a78d937 | 2214 | __intel_pmu_disable_all(); |
b0b2072d | 2215 | handled = intel_pmu_drain_bts_buffer(); |
8062382c | 2216 | handled += intel_bts_interrupt(); |
f22f54f4 | 2217 | status = intel_pmu_get_status(); |
a3ef2229 MM |
2218 | if (!status) |
2219 | goto done; | |
f22f54f4 PZ |
2220 | |
2221 | loops = 0; | |
2222 | again: | |
0f29e573 | 2223 | intel_pmu_lbr_read(); |
2e556b5b | 2224 | intel_pmu_ack_status(status); |
f22f54f4 | 2225 | if (++loops > 100) { |
ae0def05 DH |
2226 | static bool warned = false; |
2227 | if (!warned) { | |
2228 | WARN(1, "perfevents: irq loop stuck!\n"); | |
2229 | perf_event_print_debug(); | |
2230 | warned = true; | |
2231 | } | |
f22f54f4 | 2232 | intel_pmu_reset(); |
3fb2b8dd | 2233 | goto done; |
f22f54f4 PZ |
2234 | } |
2235 | ||
2236 | inc_irq_stat(apic_perf_irqs); | |
ca037701 | 2237 | |
caff2bef | 2238 | |
b292d7a1 | 2239 | /* |
d8020bee AK |
2240 | * Ignore a range of extra bits in status that do not indicate |
2241 | * overflow by themselves. | |
b292d7a1 | 2242 | */ |
d8020bee AK |
2243 | status &= ~(GLOBAL_STATUS_COND_CHG | |
2244 | GLOBAL_STATUS_ASIF | | |
2245 | GLOBAL_STATUS_LBRS_FROZEN); | |
2246 | if (!status) | |
2247 | goto done; | |
daa864b8 SE |
2248 | /* |
2249 | * In case multiple PEBS events are sampled at the same time, | |
2250 | * it is possible to have GLOBAL_STATUS bit 62 set indicating | |
2251 | * PEBS buffer overflow and also seeing at most 3 PEBS counters | |
2252 | * having their bits set in the status register. This is a sign | |
2253 | * that there was at least one PEBS record pending at the time | |
2254 | * of the PMU interrupt. PEBS counters must only be processed | |
2255 | * via the drain_pebs() calls and not via the regular sample | |
2256 | * processing loop coming after that the function, otherwise | |
2257 | * phony regular samples may be generated in the sampling buffer | |
2258 | * not marked with the EXACT tag. Another possibility is to have | |
2259 | * one PEBS event and at least one non-PEBS event whic hoverflows | |
2260 | * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will | |
2261 | * not be set, yet the overflow status bit for the PEBS counter will | |
2262 | * be on Skylake. | |
2263 | * | |
2264 | * To avoid this problem, we systematically ignore the PEBS-enabled | |
2265 | * counters from the GLOBAL_STATUS mask and we always process PEBS | |
2266 | * events via drain_pebs(). | |
2267 | */ | |
fd583ad1 | 2268 | status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); |
b292d7a1 | 2269 | |
ca037701 PZ |
2270 | /* |
2271 | * PEBS overflow sets bit 62 in the global status register | |
2272 | */ | |
de725dec PZ |
2273 | if (__test_and_clear_bit(62, (unsigned long *)&status)) { |
2274 | handled++; | |
ca037701 | 2275 | x86_pmu.drain_pebs(regs); |
8077eca0 | 2276 | status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; |
de725dec | 2277 | } |
ca037701 | 2278 | |
52ca9ced AS |
2279 | /* |
2280 | * Intel PT | |
2281 | */ | |
2282 | if (__test_and_clear_bit(55, (unsigned long *)&status)) { | |
2283 | handled++; | |
2284 | intel_pt_interrupt(); | |
2285 | } | |
2286 | ||
2dbf0116 | 2287 | /* |
2b9e344d PZ |
2288 | * Checkpointed counters can lead to 'spurious' PMIs because the |
2289 | * rollback caused by the PMI will have cleared the overflow status | |
2290 | * bit. Therefore always force probe these counters. | |
2dbf0116 | 2291 | */ |
2b9e344d | 2292 | status |= cpuc->intel_cp_status; |
2dbf0116 | 2293 | |
984b3f57 | 2294 | for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
f22f54f4 PZ |
2295 | struct perf_event *event = cpuc->events[bit]; |
2296 | ||
de725dec PZ |
2297 | handled++; |
2298 | ||
f22f54f4 PZ |
2299 | if (!test_bit(bit, cpuc->active_mask)) |
2300 | continue; | |
2301 | ||
2302 | if (!intel_pmu_save_and_restart(event)) | |
2303 | continue; | |
2304 | ||
fd0d000b | 2305 | perf_sample_data_init(&data, 0, event->hw.last_period); |
f22f54f4 | 2306 | |
60ce0fbd SE |
2307 | if (has_branch_stack(event)) |
2308 | data.br_stack = &cpuc->lbr_stack; | |
2309 | ||
a8b0ca17 | 2310 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 2311 | x86_pmu_stop(event, 0); |
f22f54f4 PZ |
2312 | } |
2313 | ||
f22f54f4 PZ |
2314 | /* |
2315 | * Repeat if there is more work to be done: | |
2316 | */ | |
2317 | status = intel_pmu_get_status(); | |
2318 | if (status) | |
2319 | goto again; | |
2320 | ||
3fb2b8dd | 2321 | done: |
c3d266c8 KL |
2322 | /* Only restore PMU state when it's active. See x86_pmu_disable(). */ |
2323 | if (cpuc->enabled) | |
2324 | __intel_pmu_enable_all(0, true); | |
cecf6235 | 2325 | intel_bts_enable_local(); |
c3d266c8 | 2326 | |
72db5596 AK |
2327 | /* |
2328 | * Only unmask the NMI after the overflow counters | |
2329 | * have been reset. This avoids spurious NMIs on | |
2330 | * Haswell CPUs. | |
2331 | */ | |
2332 | if (x86_pmu.late_ack) | |
2333 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
de725dec | 2334 | return handled; |
f22f54f4 PZ |
2335 | } |
2336 | ||
f22f54f4 | 2337 | static struct event_constraint * |
ca037701 | 2338 | intel_bts_constraints(struct perf_event *event) |
f22f54f4 | 2339 | { |
ca037701 PZ |
2340 | struct hw_perf_event *hwc = &event->hw; |
2341 | unsigned int hw_event, bts_event; | |
f22f54f4 | 2342 | |
18a073a3 PZ |
2343 | if (event->attr.freq) |
2344 | return NULL; | |
2345 | ||
ca037701 PZ |
2346 | hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; |
2347 | bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); | |
f22f54f4 | 2348 | |
ca037701 | 2349 | if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) |
f22f54f4 | 2350 | return &bts_constraint; |
ca037701 | 2351 | |
f22f54f4 PZ |
2352 | return NULL; |
2353 | } | |
2354 | ||
ae3f011f | 2355 | static int intel_alt_er(int idx, u64 config) |
b79e8941 | 2356 | { |
e01d8718 PZ |
2357 | int alt_idx = idx; |
2358 | ||
9a5e3fb5 | 2359 | if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) |
5a425294 | 2360 | return idx; |
b79e8941 | 2361 | |
5a425294 | 2362 | if (idx == EXTRA_REG_RSP_0) |
ae3f011f | 2363 | alt_idx = EXTRA_REG_RSP_1; |
5a425294 PZ |
2364 | |
2365 | if (idx == EXTRA_REG_RSP_1) | |
ae3f011f | 2366 | alt_idx = EXTRA_REG_RSP_0; |
5a425294 | 2367 | |
ae3f011f KL |
2368 | if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) |
2369 | return idx; | |
2370 | ||
2371 | return alt_idx; | |
5a425294 PZ |
2372 | } |
2373 | ||
2374 | static void intel_fixup_er(struct perf_event *event, int idx) | |
2375 | { | |
2376 | event->hw.extra_reg.idx = idx; | |
2377 | ||
2378 | if (idx == EXTRA_REG_RSP_0) { | |
b79e8941 | 2379 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; |
53ad0447 | 2380 | event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; |
b79e8941 | 2381 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; |
5a425294 PZ |
2382 | } else if (idx == EXTRA_REG_RSP_1) { |
2383 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; | |
53ad0447 | 2384 | event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; |
5a425294 | 2385 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; |
b79e8941 | 2386 | } |
b79e8941 PZ |
2387 | } |
2388 | ||
efc9f05d SE |
2389 | /* |
2390 | * manage allocation of shared extra msr for certain events | |
2391 | * | |
2392 | * sharing can be: | |
2393 | * per-cpu: to be shared between the various events on a single PMU | |
2394 | * per-core: per-cpu + shared by HT threads | |
2395 | */ | |
a7e3ed1e | 2396 | static struct event_constraint * |
efc9f05d | 2397 | __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, |
b36817e8 SE |
2398 | struct perf_event *event, |
2399 | struct hw_perf_event_extra *reg) | |
a7e3ed1e | 2400 | { |
efc9f05d | 2401 | struct event_constraint *c = &emptyconstraint; |
a7e3ed1e | 2402 | struct er_account *era; |
cd8a38d3 | 2403 | unsigned long flags; |
5a425294 | 2404 | int idx = reg->idx; |
a7e3ed1e | 2405 | |
5a425294 PZ |
2406 | /* |
2407 | * reg->alloc can be set due to existing state, so for fake cpuc we | |
2408 | * need to ignore this, otherwise we might fail to allocate proper fake | |
2409 | * state for this extra reg constraint. Also see the comment below. | |
2410 | */ | |
2411 | if (reg->alloc && !cpuc->is_fake) | |
b36817e8 | 2412 | return NULL; /* call x86_get_event_constraint() */ |
a7e3ed1e | 2413 | |
b79e8941 | 2414 | again: |
5a425294 | 2415 | era = &cpuc->shared_regs->regs[idx]; |
cd8a38d3 SE |
2416 | /* |
2417 | * we use spin_lock_irqsave() to avoid lockdep issues when | |
2418 | * passing a fake cpuc | |
2419 | */ | |
2420 | raw_spin_lock_irqsave(&era->lock, flags); | |
efc9f05d SE |
2421 | |
2422 | if (!atomic_read(&era->ref) || era->config == reg->config) { | |
2423 | ||
5a425294 PZ |
2424 | /* |
2425 | * If its a fake cpuc -- as per validate_{group,event}() we | |
2426 | * shouldn't touch event state and we can avoid doing so | |
2427 | * since both will only call get_event_constraints() once | |
2428 | * on each event, this avoids the need for reg->alloc. | |
2429 | * | |
2430 | * Not doing the ER fixup will only result in era->reg being | |
2431 | * wrong, but since we won't actually try and program hardware | |
2432 | * this isn't a problem either. | |
2433 | */ | |
2434 | if (!cpuc->is_fake) { | |
2435 | if (idx != reg->idx) | |
2436 | intel_fixup_er(event, idx); | |
2437 | ||
2438 | /* | |
2439 | * x86_schedule_events() can call get_event_constraints() | |
2440 | * multiple times on events in the case of incremental | |
2441 | * scheduling(). reg->alloc ensures we only do the ER | |
2442 | * allocation once. | |
2443 | */ | |
2444 | reg->alloc = 1; | |
2445 | } | |
2446 | ||
efc9f05d SE |
2447 | /* lock in msr value */ |
2448 | era->config = reg->config; | |
2449 | era->reg = reg->reg; | |
2450 | ||
2451 | /* one more user */ | |
2452 | atomic_inc(&era->ref); | |
2453 | ||
a7e3ed1e | 2454 | /* |
b36817e8 SE |
2455 | * need to call x86_get_event_constraint() |
2456 | * to check if associated event has constraints | |
a7e3ed1e | 2457 | */ |
b36817e8 | 2458 | c = NULL; |
5a425294 | 2459 | } else { |
ae3f011f | 2460 | idx = intel_alt_er(idx, reg->config); |
5a425294 PZ |
2461 | if (idx != reg->idx) { |
2462 | raw_spin_unlock_irqrestore(&era->lock, flags); | |
2463 | goto again; | |
2464 | } | |
a7e3ed1e | 2465 | } |
cd8a38d3 | 2466 | raw_spin_unlock_irqrestore(&era->lock, flags); |
a7e3ed1e | 2467 | |
efc9f05d SE |
2468 | return c; |
2469 | } | |
2470 | ||
2471 | static void | |
2472 | __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, | |
2473 | struct hw_perf_event_extra *reg) | |
2474 | { | |
2475 | struct er_account *era; | |
2476 | ||
2477 | /* | |
5a425294 PZ |
2478 | * Only put constraint if extra reg was actually allocated. Also takes |
2479 | * care of event which do not use an extra shared reg. | |
2480 | * | |
2481 | * Also, if this is a fake cpuc we shouldn't touch any event state | |
2482 | * (reg->alloc) and we don't care about leaving inconsistent cpuc state | |
2483 | * either since it'll be thrown out. | |
efc9f05d | 2484 | */ |
5a425294 | 2485 | if (!reg->alloc || cpuc->is_fake) |
efc9f05d SE |
2486 | return; |
2487 | ||
2488 | era = &cpuc->shared_regs->regs[reg->idx]; | |
2489 | ||
2490 | /* one fewer user */ | |
2491 | atomic_dec(&era->ref); | |
2492 | ||
2493 | /* allocate again next time */ | |
2494 | reg->alloc = 0; | |
2495 | } | |
2496 | ||
2497 | static struct event_constraint * | |
2498 | intel_shared_regs_constraints(struct cpu_hw_events *cpuc, | |
2499 | struct perf_event *event) | |
2500 | { | |
b36817e8 SE |
2501 | struct event_constraint *c = NULL, *d; |
2502 | struct hw_perf_event_extra *xreg, *breg; | |
2503 | ||
2504 | xreg = &event->hw.extra_reg; | |
2505 | if (xreg->idx != EXTRA_REG_NONE) { | |
2506 | c = __intel_shared_reg_get_constraints(cpuc, event, xreg); | |
2507 | if (c == &emptyconstraint) | |
2508 | return c; | |
2509 | } | |
2510 | breg = &event->hw.branch_reg; | |
2511 | if (breg->idx != EXTRA_REG_NONE) { | |
2512 | d = __intel_shared_reg_get_constraints(cpuc, event, breg); | |
2513 | if (d == &emptyconstraint) { | |
2514 | __intel_shared_reg_put_constraints(cpuc, xreg); | |
2515 | c = d; | |
2516 | } | |
2517 | } | |
efc9f05d | 2518 | return c; |
a7e3ed1e AK |
2519 | } |
2520 | ||
de0428a7 | 2521 | struct event_constraint * |
79cba822 SE |
2522 | x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
2523 | struct perf_event *event) | |
de0428a7 KW |
2524 | { |
2525 | struct event_constraint *c; | |
2526 | ||
2527 | if (x86_pmu.event_constraints) { | |
2528 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
9fac2cf3 | 2529 | if ((event->hw.config & c->cmask) == c->code) { |
9fac2cf3 | 2530 | event->hw.flags |= c->flags; |
de0428a7 | 2531 | return c; |
9fac2cf3 | 2532 | } |
de0428a7 KW |
2533 | } |
2534 | } | |
2535 | ||
2536 | return &unconstrained; | |
2537 | } | |
2538 | ||
f22f54f4 | 2539 | static struct event_constraint * |
e979121b | 2540 | __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
79cba822 | 2541 | struct perf_event *event) |
f22f54f4 PZ |
2542 | { |
2543 | struct event_constraint *c; | |
2544 | ||
ca037701 PZ |
2545 | c = intel_bts_constraints(event); |
2546 | if (c) | |
2547 | return c; | |
2548 | ||
687805e4 | 2549 | c = intel_shared_regs_constraints(cpuc, event); |
f22f54f4 PZ |
2550 | if (c) |
2551 | return c; | |
2552 | ||
687805e4 | 2553 | c = intel_pebs_constraints(event); |
a7e3ed1e AK |
2554 | if (c) |
2555 | return c; | |
2556 | ||
79cba822 | 2557 | return x86_get_event_constraints(cpuc, idx, event); |
f22f54f4 PZ |
2558 | } |
2559 | ||
e979121b MD |
2560 | static void |
2561 | intel_start_scheduling(struct cpu_hw_events *cpuc) | |
2562 | { | |
2563 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
1c565833 | 2564 | struct intel_excl_states *xl; |
e979121b | 2565 | int tid = cpuc->excl_thread_id; |
e979121b MD |
2566 | |
2567 | /* | |
2568 | * nothing needed if in group validation mode | |
2569 | */ | |
b37609c3 | 2570 | if (cpuc->is_fake || !is_ht_workaround_enabled()) |
e979121b | 2571 | return; |
b37609c3 | 2572 | |
e979121b MD |
2573 | /* |
2574 | * no exclusion needed | |
2575 | */ | |
17186ccd | 2576 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b MD |
2577 | return; |
2578 | ||
e979121b MD |
2579 | xl = &excl_cntrs->states[tid]; |
2580 | ||
2581 | xl->sched_started = true; | |
e979121b MD |
2582 | /* |
2583 | * lock shared state until we are done scheduling | |
2584 | * in stop_event_scheduling() | |
2585 | * makes scheduling appear as a transaction | |
2586 | */ | |
e979121b | 2587 | raw_spin_lock(&excl_cntrs->lock); |
e979121b MD |
2588 | } |
2589 | ||
0c41e756 PZ |
2590 | static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) |
2591 | { | |
2592 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
2593 | struct event_constraint *c = cpuc->event_constraint[idx]; | |
2594 | struct intel_excl_states *xl; | |
2595 | int tid = cpuc->excl_thread_id; | |
2596 | ||
2597 | if (cpuc->is_fake || !is_ht_workaround_enabled()) | |
2598 | return; | |
2599 | ||
2600 | if (WARN_ON_ONCE(!excl_cntrs)) | |
2601 | return; | |
2602 | ||
2603 | if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) | |
2604 | return; | |
2605 | ||
2606 | xl = &excl_cntrs->states[tid]; | |
2607 | ||
2608 | lockdep_assert_held(&excl_cntrs->lock); | |
2609 | ||
1fe684e3 | 2610 | if (c->flags & PERF_X86_EVENT_EXCL) |
43ef205b | 2611 | xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; |
1fe684e3 | 2612 | else |
43ef205b | 2613 | xl->state[cntr] = INTEL_EXCL_SHARED; |
0c41e756 PZ |
2614 | } |
2615 | ||
e979121b MD |
2616 | static void |
2617 | intel_stop_scheduling(struct cpu_hw_events *cpuc) | |
2618 | { | |
2619 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
1c565833 | 2620 | struct intel_excl_states *xl; |
e979121b | 2621 | int tid = cpuc->excl_thread_id; |
e979121b MD |
2622 | |
2623 | /* | |
2624 | * nothing needed if in group validation mode | |
2625 | */ | |
b37609c3 | 2626 | if (cpuc->is_fake || !is_ht_workaround_enabled()) |
e979121b MD |
2627 | return; |
2628 | /* | |
2629 | * no exclusion needed | |
2630 | */ | |
17186ccd | 2631 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b MD |
2632 | return; |
2633 | ||
e979121b MD |
2634 | xl = &excl_cntrs->states[tid]; |
2635 | ||
e979121b MD |
2636 | xl->sched_started = false; |
2637 | /* | |
2638 | * release shared state lock (acquired in intel_start_scheduling()) | |
2639 | */ | |
2640 | raw_spin_unlock(&excl_cntrs->lock); | |
2641 | } | |
2642 | ||
2643 | static struct event_constraint * | |
2644 | intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, | |
2645 | int idx, struct event_constraint *c) | |
2646 | { | |
e979121b | 2647 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; |
1c565833 | 2648 | struct intel_excl_states *xlo; |
e979121b | 2649 | int tid = cpuc->excl_thread_id; |
1c565833 | 2650 | int is_excl, i; |
e979121b MD |
2651 | |
2652 | /* | |
2653 | * validating a group does not require | |
2654 | * enforcing cross-thread exclusion | |
2655 | */ | |
b37609c3 SE |
2656 | if (cpuc->is_fake || !is_ht_workaround_enabled()) |
2657 | return c; | |
2658 | ||
2659 | /* | |
2660 | * no exclusion needed | |
2661 | */ | |
17186ccd | 2662 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b | 2663 | return c; |
e979121b | 2664 | |
e979121b MD |
2665 | /* |
2666 | * because we modify the constraint, we need | |
2667 | * to make a copy. Static constraints come | |
2668 | * from static const tables. | |
2669 | * | |
2670 | * only needed when constraint has not yet | |
2671 | * been cloned (marked dynamic) | |
2672 | */ | |
2673 | if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { | |
aaf932e8 | 2674 | struct event_constraint *cx; |
e979121b | 2675 | |
e979121b MD |
2676 | /* |
2677 | * grab pre-allocated constraint entry | |
2678 | */ | |
2679 | cx = &cpuc->constraint_list[idx]; | |
2680 | ||
2681 | /* | |
2682 | * initialize dynamic constraint | |
2683 | * with static constraint | |
2684 | */ | |
aaf932e8 | 2685 | *cx = *c; |
e979121b MD |
2686 | |
2687 | /* | |
2688 | * mark constraint as dynamic, so we | |
2689 | * can free it later on | |
2690 | */ | |
2691 | cx->flags |= PERF_X86_EVENT_DYNAMIC; | |
aaf932e8 | 2692 | c = cx; |
e979121b MD |
2693 | } |
2694 | ||
2695 | /* | |
2696 | * From here on, the constraint is dynamic. | |
2697 | * Either it was just allocated above, or it | |
2698 | * was allocated during a earlier invocation | |
2699 | * of this function | |
2700 | */ | |
2701 | ||
1c565833 PZ |
2702 | /* |
2703 | * state of sibling HT | |
2704 | */ | |
2705 | xlo = &excl_cntrs->states[tid ^ 1]; | |
2706 | ||
2707 | /* | |
2708 | * event requires exclusive counter access | |
2709 | * across HT threads | |
2710 | */ | |
2711 | is_excl = c->flags & PERF_X86_EVENT_EXCL; | |
2712 | if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { | |
2713 | event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; | |
2714 | if (!cpuc->n_excl++) | |
2715 | WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); | |
2716 | } | |
2717 | ||
e979121b MD |
2718 | /* |
2719 | * Modify static constraint with current dynamic | |
2720 | * state of thread | |
2721 | * | |
2722 | * EXCLUSIVE: sibling counter measuring exclusive event | |
2723 | * SHARED : sibling counter measuring non-exclusive event | |
2724 | * UNUSED : sibling counter unused | |
2725 | */ | |
aaf932e8 | 2726 | for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { |
e979121b MD |
2727 | /* |
2728 | * exclusive event in sibling counter | |
2729 | * our corresponding counter cannot be used | |
2730 | * regardless of our event | |
2731 | */ | |
1c565833 | 2732 | if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) |
aaf932e8 | 2733 | __clear_bit(i, c->idxmsk); |
e979121b MD |
2734 | /* |
2735 | * if measuring an exclusive event, sibling | |
2736 | * measuring non-exclusive, then counter cannot | |
2737 | * be used | |
2738 | */ | |
1c565833 | 2739 | if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) |
aaf932e8 | 2740 | __clear_bit(i, c->idxmsk); |
e979121b MD |
2741 | } |
2742 | ||
2743 | /* | |
2744 | * recompute actual bit weight for scheduling algorithm | |
2745 | */ | |
aaf932e8 | 2746 | c->weight = hweight64(c->idxmsk64); |
e979121b MD |
2747 | |
2748 | /* | |
2749 | * if we return an empty mask, then switch | |
2750 | * back to static empty constraint to avoid | |
2751 | * the cost of freeing later on | |
2752 | */ | |
aaf932e8 PZ |
2753 | if (c->weight == 0) |
2754 | c = &emptyconstraint; | |
e979121b | 2755 | |
aaf932e8 | 2756 | return c; |
e979121b MD |
2757 | } |
2758 | ||
2759 | static struct event_constraint * | |
2760 | intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
2761 | struct perf_event *event) | |
2762 | { | |
ebfb4988 | 2763 | struct event_constraint *c1 = NULL; |
a90738c2 | 2764 | struct event_constraint *c2; |
e979121b | 2765 | |
ebfb4988 PZ |
2766 | if (idx >= 0) /* fake does < 0 */ |
2767 | c1 = cpuc->event_constraint[idx]; | |
2768 | ||
e979121b MD |
2769 | /* |
2770 | * first time only | |
2771 | * - static constraint: no change across incremental scheduling calls | |
2772 | * - dynamic constraint: handled by intel_get_excl_constraints() | |
2773 | */ | |
a90738c2 SE |
2774 | c2 = __intel_get_event_constraints(cpuc, idx, event); |
2775 | if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) { | |
2776 | bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); | |
2777 | c1->weight = c2->weight; | |
2778 | c2 = c1; | |
2779 | } | |
e979121b MD |
2780 | |
2781 | if (cpuc->excl_cntrs) | |
a90738c2 | 2782 | return intel_get_excl_constraints(cpuc, event, idx, c2); |
e979121b | 2783 | |
a90738c2 | 2784 | return c2; |
e979121b MD |
2785 | } |
2786 | ||
2787 | static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, | |
2788 | struct perf_event *event) | |
2789 | { | |
2790 | struct hw_perf_event *hwc = &event->hw; | |
2791 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
e979121b | 2792 | int tid = cpuc->excl_thread_id; |
1c565833 | 2793 | struct intel_excl_states *xl; |
e979121b MD |
2794 | |
2795 | /* | |
2796 | * nothing needed if in group validation mode | |
2797 | */ | |
2798 | if (cpuc->is_fake) | |
2799 | return; | |
2800 | ||
17186ccd | 2801 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b MD |
2802 | return; |
2803 | ||
cc1790cf PZ |
2804 | if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { |
2805 | hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; | |
2806 | if (!--cpuc->n_excl) | |
2807 | WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); | |
2808 | } | |
e979121b MD |
2809 | |
2810 | /* | |
ba040653 PZ |
2811 | * If event was actually assigned, then mark the counter state as |
2812 | * unused now. | |
e979121b | 2813 | */ |
ba040653 PZ |
2814 | if (hwc->idx >= 0) { |
2815 | xl = &excl_cntrs->states[tid]; | |
2816 | ||
2817 | /* | |
2818 | * put_constraint may be called from x86_schedule_events() | |
2819 | * which already has the lock held so here make locking | |
2820 | * conditional. | |
2821 | */ | |
2822 | if (!xl->sched_started) | |
2823 | raw_spin_lock(&excl_cntrs->lock); | |
e979121b | 2824 | |
1c565833 | 2825 | xl->state[hwc->idx] = INTEL_EXCL_UNUSED; |
e979121b | 2826 | |
ba040653 PZ |
2827 | if (!xl->sched_started) |
2828 | raw_spin_unlock(&excl_cntrs->lock); | |
2829 | } | |
e979121b MD |
2830 | } |
2831 | ||
efc9f05d SE |
2832 | static void |
2833 | intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, | |
a7e3ed1e AK |
2834 | struct perf_event *event) |
2835 | { | |
efc9f05d | 2836 | struct hw_perf_event_extra *reg; |
a7e3ed1e | 2837 | |
efc9f05d SE |
2838 | reg = &event->hw.extra_reg; |
2839 | if (reg->idx != EXTRA_REG_NONE) | |
2840 | __intel_shared_reg_put_constraints(cpuc, reg); | |
b36817e8 SE |
2841 | |
2842 | reg = &event->hw.branch_reg; | |
2843 | if (reg->idx != EXTRA_REG_NONE) | |
2844 | __intel_shared_reg_put_constraints(cpuc, reg); | |
efc9f05d | 2845 | } |
a7e3ed1e | 2846 | |
efc9f05d SE |
2847 | static void intel_put_event_constraints(struct cpu_hw_events *cpuc, |
2848 | struct perf_event *event) | |
2849 | { | |
2850 | intel_put_shared_regs_event_constraints(cpuc, event); | |
e979121b MD |
2851 | |
2852 | /* | |
2853 | * is PMU has exclusive counter restrictions, then | |
2854 | * all events are subject to and must call the | |
2855 | * put_excl_constraints() routine | |
2856 | */ | |
b371b594 | 2857 | if (cpuc->excl_cntrs) |
e979121b | 2858 | intel_put_excl_constraints(cpuc, event); |
e979121b MD |
2859 | } |
2860 | ||
0780c927 | 2861 | static void intel_pebs_aliases_core2(struct perf_event *event) |
b4cdc5c2 | 2862 | { |
0780c927 | 2863 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { |
7639dae0 PZ |
2864 | /* |
2865 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
2866 | * (0x003c) so that we can use it with PEBS. | |
2867 | * | |
2868 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
2869 | * PEBS capable. However we can use INST_RETIRED.ANY_P | |
2870 | * (0x00c0), which is a PEBS capable event, to get the same | |
2871 | * count. | |
2872 | * | |
2873 | * INST_RETIRED.ANY_P counts the number of cycles that retires | |
2874 | * CNTMASK instructions. By setting CNTMASK to a value (16) | |
2875 | * larger than the maximum number of instructions that can be | |
2876 | * retired per cycle (4) and then inverting the condition, we | |
2877 | * count all cycles that retire 16 or less instructions, which | |
2878 | * is every cycle. | |
2879 | * | |
2880 | * Thereby we gain a PEBS capable cycle counter. | |
2881 | */ | |
f9b4eeb8 PZ |
2882 | u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); |
2883 | ||
0780c927 PZ |
2884 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); |
2885 | event->hw.config = alt_config; | |
2886 | } | |
2887 | } | |
2888 | ||
2889 | static void intel_pebs_aliases_snb(struct perf_event *event) | |
2890 | { | |
2891 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { | |
2892 | /* | |
2893 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
2894 | * (0x003c) so that we can use it with PEBS. | |
2895 | * | |
2896 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
2897 | * PEBS capable. However we can use UOPS_RETIRED.ALL | |
2898 | * (0x01c2), which is a PEBS capable event, to get the same | |
2899 | * count. | |
2900 | * | |
2901 | * UOPS_RETIRED.ALL counts the number of cycles that retires | |
2902 | * CNTMASK micro-ops. By setting CNTMASK to a value (16) | |
2903 | * larger than the maximum number of micro-ops that can be | |
2904 | * retired per cycle (4) and then inverting the condition, we | |
2905 | * count all cycles that retire 16 or less micro-ops, which | |
2906 | * is every cycle. | |
2907 | * | |
2908 | * Thereby we gain a PEBS capable cycle counter. | |
2909 | */ | |
2910 | u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); | |
7639dae0 PZ |
2911 | |
2912 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); | |
2913 | event->hw.config = alt_config; | |
2914 | } | |
0780c927 PZ |
2915 | } |
2916 | ||
72469764 AK |
2917 | static void intel_pebs_aliases_precdist(struct perf_event *event) |
2918 | { | |
2919 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { | |
2920 | /* | |
2921 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
2922 | * (0x003c) so that we can use it with PEBS. | |
2923 | * | |
2924 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
2925 | * PEBS capable. However we can use INST_RETIRED.PREC_DIST | |
2926 | * (0x01c0), which is a PEBS capable event, to get the same | |
2927 | * count. | |
2928 | * | |
2929 | * The PREC_DIST event has special support to minimize sample | |
2930 | * shadowing effects. One drawback is that it can be | |
2931 | * only programmed on counter 1, but that seems like an | |
2932 | * acceptable trade off. | |
2933 | */ | |
2934 | u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); | |
2935 | ||
2936 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); | |
2937 | event->hw.config = alt_config; | |
2938 | } | |
2939 | } | |
2940 | ||
2941 | static void intel_pebs_aliases_ivb(struct perf_event *event) | |
2942 | { | |
2943 | if (event->attr.precise_ip < 3) | |
2944 | return intel_pebs_aliases_snb(event); | |
2945 | return intel_pebs_aliases_precdist(event); | |
2946 | } | |
2947 | ||
2948 | static void intel_pebs_aliases_skl(struct perf_event *event) | |
2949 | { | |
2950 | if (event->attr.precise_ip < 3) | |
2951 | return intel_pebs_aliases_core2(event); | |
2952 | return intel_pebs_aliases_precdist(event); | |
2953 | } | |
2954 | ||
a7b58d21 AK |
2955 | static unsigned long intel_pmu_free_running_flags(struct perf_event *event) |
2956 | { | |
2957 | unsigned long flags = x86_pmu.free_running_flags; | |
2958 | ||
2959 | if (event->attr.use_clockid) | |
2960 | flags &= ~PERF_SAMPLE_TIME; | |
06c6715f AK |
2961 | if (!event->attr.exclude_kernel) |
2962 | flags &= ~PERF_SAMPLE_REGS_USER; | |
2963 | if (event->attr.sample_regs_user & ~PEBS_REGS) | |
2964 | flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); | |
a7b58d21 AK |
2965 | return flags; |
2966 | } | |
2967 | ||
0780c927 PZ |
2968 | static int intel_pmu_hw_config(struct perf_event *event) |
2969 | { | |
2970 | int ret = x86_pmu_hw_config(event); | |
2971 | ||
2972 | if (ret) | |
2973 | return ret; | |
2974 | ||
851559e3 | 2975 | if (event->attr.precise_ip) { |
3569c0d7 | 2976 | if (!event->attr.freq) { |
851559e3 | 2977 | event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; |
a7b58d21 AK |
2978 | if (!(event->attr.sample_type & |
2979 | ~intel_pmu_free_running_flags(event))) | |
3569c0d7 YZ |
2980 | event->hw.flags |= PERF_X86_EVENT_FREERUNNING; |
2981 | } | |
851559e3 YZ |
2982 | if (x86_pmu.pebs_aliases) |
2983 | x86_pmu.pebs_aliases(event); | |
2984 | } | |
7639dae0 | 2985 | |
a46a2300 | 2986 | if (needs_branch_stack(event)) { |
60ce0fbd SE |
2987 | ret = intel_pmu_setup_lbr_filter(event); |
2988 | if (ret) | |
2989 | return ret; | |
48070342 AS |
2990 | |
2991 | /* | |
2992 | * BTS is set up earlier in this path, so don't account twice | |
2993 | */ | |
2994 | if (!intel_pmu_has_bts(event)) { | |
2995 | /* disallow lbr if conflicting events are present */ | |
2996 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
2997 | return -EBUSY; | |
2998 | ||
2999 | event->destroy = hw_perf_lbr_event_destroy; | |
3000 | } | |
60ce0fbd SE |
3001 | } |
3002 | ||
b4cdc5c2 PZ |
3003 | if (event->attr.type != PERF_TYPE_RAW) |
3004 | return 0; | |
3005 | ||
3006 | if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) | |
3007 | return 0; | |
3008 | ||
3009 | if (x86_pmu.version < 3) | |
3010 | return -EINVAL; | |
3011 | ||
3012 | if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) | |
3013 | return -EACCES; | |
3014 | ||
3015 | event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; | |
3016 | ||
3017 | return 0; | |
3018 | } | |
3019 | ||
144d31e6 GN |
3020 | struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) |
3021 | { | |
3022 | if (x86_pmu.guest_get_msrs) | |
3023 | return x86_pmu.guest_get_msrs(nr); | |
3024 | *nr = 0; | |
3025 | return NULL; | |
3026 | } | |
3027 | EXPORT_SYMBOL_GPL(perf_guest_get_msrs); | |
3028 | ||
3029 | static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) | |
3030 | { | |
89cbc767 | 3031 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
144d31e6 GN |
3032 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; |
3033 | ||
3034 | arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; | |
3035 | arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; | |
3036 | arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; | |
26a4f3c0 GN |
3037 | /* |
3038 | * If PMU counter has PEBS enabled it is not enough to disable counter | |
3039 | * on a guest entry since PEBS memory write can overshoot guest entry | |
3040 | * and corrupt guest memory. Disabling PEBS solves the problem. | |
3041 | */ | |
3042 | arr[1].msr = MSR_IA32_PEBS_ENABLE; | |
3043 | arr[1].host = cpuc->pebs_enabled; | |
3044 | arr[1].guest = 0; | |
144d31e6 | 3045 | |
26a4f3c0 | 3046 | *nr = 2; |
144d31e6 GN |
3047 | return arr; |
3048 | } | |
3049 | ||
3050 | static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) | |
3051 | { | |
89cbc767 | 3052 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
144d31e6 GN |
3053 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; |
3054 | int idx; | |
3055 | ||
3056 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
3057 | struct perf_event *event = cpuc->events[idx]; | |
3058 | ||
3059 | arr[idx].msr = x86_pmu_config_addr(idx); | |
3060 | arr[idx].host = arr[idx].guest = 0; | |
3061 | ||
3062 | if (!test_bit(idx, cpuc->active_mask)) | |
3063 | continue; | |
3064 | ||
3065 | arr[idx].host = arr[idx].guest = | |
3066 | event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; | |
3067 | ||
3068 | if (event->attr.exclude_host) | |
3069 | arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
3070 | else if (event->attr.exclude_guest) | |
3071 | arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
3072 | } | |
3073 | ||
3074 | *nr = x86_pmu.num_counters; | |
3075 | return arr; | |
3076 | } | |
3077 | ||
3078 | static void core_pmu_enable_event(struct perf_event *event) | |
3079 | { | |
3080 | if (!event->attr.exclude_host) | |
3081 | x86_pmu_enable_event(event); | |
3082 | } | |
3083 | ||
3084 | static void core_pmu_enable_all(int added) | |
3085 | { | |
89cbc767 | 3086 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
144d31e6 GN |
3087 | int idx; |
3088 | ||
3089 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
3090 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; | |
3091 | ||
3092 | if (!test_bit(idx, cpuc->active_mask) || | |
3093 | cpuc->events[idx]->attr.exclude_host) | |
3094 | continue; | |
3095 | ||
3096 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); | |
3097 | } | |
3098 | } | |
3099 | ||
3a632cb2 AK |
3100 | static int hsw_hw_config(struct perf_event *event) |
3101 | { | |
3102 | int ret = intel_pmu_hw_config(event); | |
3103 | ||
3104 | if (ret) | |
3105 | return ret; | |
3106 | if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) | |
3107 | return 0; | |
3108 | event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); | |
3109 | ||
3110 | /* | |
3111 | * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with | |
3112 | * PEBS or in ANY thread mode. Since the results are non-sensical forbid | |
3113 | * this combination. | |
3114 | */ | |
3115 | if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && | |
3116 | ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || | |
3117 | event->attr.precise_ip > 0)) | |
3118 | return -EOPNOTSUPP; | |
3119 | ||
2dbf0116 AK |
3120 | if (event_is_checkpointed(event)) { |
3121 | /* | |
3122 | * Sampling of checkpointed events can cause situations where | |
3123 | * the CPU constantly aborts because of a overflow, which is | |
3124 | * then checkpointed back and ignored. Forbid checkpointing | |
3125 | * for sampling. | |
3126 | * | |
3127 | * But still allow a long sampling period, so that perf stat | |
3128 | * from KVM works. | |
3129 | */ | |
3130 | if (event->attr.sample_period > 0 && | |
3131 | event->attr.sample_period < 0x7fffffff) | |
3132 | return -EOPNOTSUPP; | |
3133 | } | |
3a632cb2 AK |
3134 | return 0; |
3135 | } | |
3136 | ||
dd0b06b5 KL |
3137 | static struct event_constraint counter0_constraint = |
3138 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); | |
3139 | ||
3a632cb2 AK |
3140 | static struct event_constraint counter2_constraint = |
3141 | EVENT_CONSTRAINT(0, 0x4, 0); | |
3142 | ||
3143 | static struct event_constraint * | |
79cba822 SE |
3144 | hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
3145 | struct perf_event *event) | |
3a632cb2 | 3146 | { |
79cba822 SE |
3147 | struct event_constraint *c; |
3148 | ||
3149 | c = intel_get_event_constraints(cpuc, idx, event); | |
3a632cb2 AK |
3150 | |
3151 | /* Handle special quirk on in_tx_checkpointed only in counter 2 */ | |
3152 | if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { | |
3153 | if (c->idxmsk64 & (1U << 2)) | |
3154 | return &counter2_constraint; | |
3155 | return &emptyconstraint; | |
3156 | } | |
3157 | ||
3158 | return c; | |
3159 | } | |
3160 | ||
dd0b06b5 KL |
3161 | static struct event_constraint * |
3162 | glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
3163 | struct perf_event *event) | |
3164 | { | |
3165 | struct event_constraint *c; | |
3166 | ||
3167 | /* :ppp means to do reduced skid PEBS which is PMC0 only. */ | |
3168 | if (event->attr.precise_ip == 3) | |
3169 | return &counter0_constraint; | |
3170 | ||
3171 | c = intel_get_event_constraints(cpuc, idx, event); | |
3172 | ||
3173 | return c; | |
3174 | } | |
3175 | ||
294fe0f5 AK |
3176 | /* |
3177 | * Broadwell: | |
3178 | * | |
3179 | * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared | |
3180 | * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine | |
3181 | * the two to enforce a minimum period of 128 (the smallest value that has bits | |
3182 | * 0-5 cleared and >= 100). | |
3183 | * | |
3184 | * Because of how the code in x86_perf_event_set_period() works, the truncation | |
3185 | * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period | |
3186 | * to make up for the 'lost' events due to carrying the 'error' in period_left. | |
3187 | * | |
3188 | * Therefore the effective (average) period matches the requested period, | |
3189 | * despite coarser hardware granularity. | |
3190 | */ | |
3191 | static unsigned bdw_limit_period(struct perf_event *event, unsigned left) | |
3192 | { | |
3193 | if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == | |
3194 | X86_CONFIG(.event=0xc0, .umask=0x01)) { | |
3195 | if (left < 128) | |
3196 | left = 128; | |
3197 | left &= ~0x3fu; | |
3198 | } | |
3199 | return left; | |
3200 | } | |
3201 | ||
641cc938 JO |
3202 | PMU_FORMAT_ATTR(event, "config:0-7" ); |
3203 | PMU_FORMAT_ATTR(umask, "config:8-15" ); | |
3204 | PMU_FORMAT_ATTR(edge, "config:18" ); | |
3205 | PMU_FORMAT_ATTR(pc, "config:19" ); | |
3206 | PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ | |
3207 | PMU_FORMAT_ATTR(inv, "config:23" ); | |
3208 | PMU_FORMAT_ATTR(cmask, "config:24-31" ); | |
3a632cb2 AK |
3209 | PMU_FORMAT_ATTR(in_tx, "config:32"); |
3210 | PMU_FORMAT_ATTR(in_tx_cp, "config:33"); | |
641cc938 JO |
3211 | |
3212 | static struct attribute *intel_arch_formats_attr[] = { | |
3213 | &format_attr_event.attr, | |
3214 | &format_attr_umask.attr, | |
3215 | &format_attr_edge.attr, | |
3216 | &format_attr_pc.attr, | |
3217 | &format_attr_inv.attr, | |
3218 | &format_attr_cmask.attr, | |
3219 | NULL, | |
3220 | }; | |
3221 | ||
0bf79d44 JO |
3222 | ssize_t intel_event_sysfs_show(char *page, u64 config) |
3223 | { | |
3224 | u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); | |
3225 | ||
3226 | return x86_event_sysfs_show(page, config, event); | |
3227 | } | |
3228 | ||
de0428a7 | 3229 | struct intel_shared_regs *allocate_shared_regs(int cpu) |
efc9f05d SE |
3230 | { |
3231 | struct intel_shared_regs *regs; | |
3232 | int i; | |
3233 | ||
3234 | regs = kzalloc_node(sizeof(struct intel_shared_regs), | |
3235 | GFP_KERNEL, cpu_to_node(cpu)); | |
3236 | if (regs) { | |
3237 | /* | |
3238 | * initialize the locks to keep lockdep happy | |
3239 | */ | |
3240 | for (i = 0; i < EXTRA_REG_MAX; i++) | |
3241 | raw_spin_lock_init(®s->regs[i].lock); | |
3242 | ||
3243 | regs->core_id = -1; | |
3244 | } | |
3245 | return regs; | |
3246 | } | |
3247 | ||
6f6539ca MD |
3248 | static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) |
3249 | { | |
3250 | struct intel_excl_cntrs *c; | |
6f6539ca MD |
3251 | |
3252 | c = kzalloc_node(sizeof(struct intel_excl_cntrs), | |
3253 | GFP_KERNEL, cpu_to_node(cpu)); | |
3254 | if (c) { | |
3255 | raw_spin_lock_init(&c->lock); | |
6f6539ca MD |
3256 | c->core_id = -1; |
3257 | } | |
3258 | return c; | |
3259 | } | |
3260 | ||
a7e3ed1e AK |
3261 | static int intel_pmu_cpu_prepare(int cpu) |
3262 | { | |
3263 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
3264 | ||
6f6539ca MD |
3265 | if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { |
3266 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
3267 | if (!cpuc->shared_regs) | |
dbc72b7a | 3268 | goto err; |
6f6539ca | 3269 | } |
69092624 | 3270 | |
6f6539ca MD |
3271 | if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { |
3272 | size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); | |
3273 | ||
3274 | cpuc->constraint_list = kzalloc(sz, GFP_KERNEL); | |
3275 | if (!cpuc->constraint_list) | |
dbc72b7a | 3276 | goto err_shared_regs; |
6f6539ca MD |
3277 | |
3278 | cpuc->excl_cntrs = allocate_excl_cntrs(cpu); | |
dbc72b7a PZ |
3279 | if (!cpuc->excl_cntrs) |
3280 | goto err_constraint_list; | |
3281 | ||
6f6539ca MD |
3282 | cpuc->excl_thread_id = 0; |
3283 | } | |
a7e3ed1e | 3284 | |
95ca792c | 3285 | return 0; |
dbc72b7a PZ |
3286 | |
3287 | err_constraint_list: | |
3288 | kfree(cpuc->constraint_list); | |
3289 | cpuc->constraint_list = NULL; | |
3290 | ||
3291 | err_shared_regs: | |
3292 | kfree(cpuc->shared_regs); | |
3293 | cpuc->shared_regs = NULL; | |
3294 | ||
3295 | err: | |
95ca792c | 3296 | return -ENOMEM; |
a7e3ed1e AK |
3297 | } |
3298 | ||
6089327f KL |
3299 | static void flip_smm_bit(void *data) |
3300 | { | |
3301 | unsigned long set = *(unsigned long *)data; | |
3302 | ||
3303 | if (set > 0) { | |
3304 | msr_set_bit(MSR_IA32_DEBUGCTLMSR, | |
3305 | DEBUGCTLMSR_FREEZE_IN_SMM_BIT); | |
3306 | } else { | |
3307 | msr_clear_bit(MSR_IA32_DEBUGCTLMSR, | |
3308 | DEBUGCTLMSR_FREEZE_IN_SMM_BIT); | |
3309 | } | |
3310 | } | |
3311 | ||
74846d35 PZ |
3312 | static void intel_pmu_cpu_starting(int cpu) |
3313 | { | |
a7e3ed1e AK |
3314 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
3315 | int core_id = topology_core_id(cpu); | |
3316 | int i; | |
3317 | ||
69092624 LM |
3318 | init_debug_store_on_cpu(cpu); |
3319 | /* | |
3320 | * Deal with CPUs that don't clear their LBRs on power-up. | |
3321 | */ | |
3322 | intel_pmu_lbr_reset(); | |
3323 | ||
b36817e8 SE |
3324 | cpuc->lbr_sel = NULL; |
3325 | ||
6089327f KL |
3326 | flip_smm_bit(&x86_pmu.attr_freeze_on_smi); |
3327 | ||
b36817e8 | 3328 | if (!cpuc->shared_regs) |
69092624 LM |
3329 | return; |
3330 | ||
9a5e3fb5 | 3331 | if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { |
06931e62 | 3332 | for_each_cpu(i, topology_sibling_cpumask(cpu)) { |
b36817e8 | 3333 | struct intel_shared_regs *pc; |
a7e3ed1e | 3334 | |
b36817e8 SE |
3335 | pc = per_cpu(cpu_hw_events, i).shared_regs; |
3336 | if (pc && pc->core_id == core_id) { | |
8f04b853 | 3337 | cpuc->kfree_on_online[0] = cpuc->shared_regs; |
b36817e8 SE |
3338 | cpuc->shared_regs = pc; |
3339 | break; | |
3340 | } | |
a7e3ed1e | 3341 | } |
b36817e8 SE |
3342 | cpuc->shared_regs->core_id = core_id; |
3343 | cpuc->shared_regs->refcnt++; | |
a7e3ed1e AK |
3344 | } |
3345 | ||
b36817e8 SE |
3346 | if (x86_pmu.lbr_sel_map) |
3347 | cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; | |
6f6539ca MD |
3348 | |
3349 | if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { | |
06931e62 | 3350 | for_each_cpu(i, topology_sibling_cpumask(cpu)) { |
4e71de79 | 3351 | struct cpu_hw_events *sibling; |
6f6539ca MD |
3352 | struct intel_excl_cntrs *c; |
3353 | ||
4e71de79 ZC |
3354 | sibling = &per_cpu(cpu_hw_events, i); |
3355 | c = sibling->excl_cntrs; | |
6f6539ca MD |
3356 | if (c && c->core_id == core_id) { |
3357 | cpuc->kfree_on_online[1] = cpuc->excl_cntrs; | |
3358 | cpuc->excl_cntrs = c; | |
4e71de79 ZC |
3359 | if (!sibling->excl_thread_id) |
3360 | cpuc->excl_thread_id = 1; | |
6f6539ca MD |
3361 | break; |
3362 | } | |
3363 | } | |
3364 | cpuc->excl_cntrs->core_id = core_id; | |
3365 | cpuc->excl_cntrs->refcnt++; | |
3366 | } | |
74846d35 PZ |
3367 | } |
3368 | ||
b37609c3 | 3369 | static void free_excl_cntrs(int cpu) |
74846d35 | 3370 | { |
a7e3ed1e | 3371 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
6f6539ca | 3372 | struct intel_excl_cntrs *c; |
a7e3ed1e | 3373 | |
6f6539ca MD |
3374 | c = cpuc->excl_cntrs; |
3375 | if (c) { | |
3376 | if (c->core_id == -1 || --c->refcnt == 0) | |
3377 | kfree(c); | |
3378 | cpuc->excl_cntrs = NULL; | |
3379 | kfree(cpuc->constraint_list); | |
3380 | cpuc->constraint_list = NULL; | |
3381 | } | |
b37609c3 | 3382 | } |
a7e3ed1e | 3383 | |
b37609c3 SE |
3384 | static void intel_pmu_cpu_dying(int cpu) |
3385 | { | |
3386 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
3387 | struct intel_shared_regs *pc; | |
3388 | ||
3389 | pc = cpuc->shared_regs; | |
3390 | if (pc) { | |
3391 | if (pc->core_id == -1 || --pc->refcnt == 0) | |
3392 | kfree(pc); | |
3393 | cpuc->shared_regs = NULL; | |
e979121b MD |
3394 | } |
3395 | ||
b37609c3 SE |
3396 | free_excl_cntrs(cpu); |
3397 | ||
74846d35 PZ |
3398 | fini_debug_store_on_cpu(cpu); |
3399 | } | |
3400 | ||
9c964efa YZ |
3401 | static void intel_pmu_sched_task(struct perf_event_context *ctx, |
3402 | bool sched_in) | |
3403 | { | |
df6c3db8 JO |
3404 | intel_pmu_pebs_sched_task(ctx, sched_in); |
3405 | intel_pmu_lbr_sched_task(ctx, sched_in); | |
9c964efa YZ |
3406 | } |
3407 | ||
641cc938 JO |
3408 | PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); |
3409 | ||
a63fcab4 SE |
3410 | PMU_FORMAT_ATTR(ldlat, "config1:0-15"); |
3411 | ||
d0dc8494 AK |
3412 | PMU_FORMAT_ATTR(frontend, "config1:0-23"); |
3413 | ||
641cc938 JO |
3414 | static struct attribute *intel_arch3_formats_attr[] = { |
3415 | &format_attr_event.attr, | |
3416 | &format_attr_umask.attr, | |
3417 | &format_attr_edge.attr, | |
3418 | &format_attr_pc.attr, | |
3419 | &format_attr_any.attr, | |
3420 | &format_attr_inv.attr, | |
3421 | &format_attr_cmask.attr, | |
3a632cb2 AK |
3422 | &format_attr_in_tx.attr, |
3423 | &format_attr_in_tx_cp.attr, | |
641cc938 JO |
3424 | |
3425 | &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */ | |
a63fcab4 | 3426 | &format_attr_ldlat.attr, /* PEBS load latency */ |
641cc938 JO |
3427 | NULL, |
3428 | }; | |
3429 | ||
d0dc8494 AK |
3430 | static struct attribute *skl_format_attr[] = { |
3431 | &format_attr_frontend.attr, | |
3432 | NULL, | |
3433 | }; | |
3434 | ||
3b6e0421 JO |
3435 | static __initconst const struct x86_pmu core_pmu = { |
3436 | .name = "core", | |
3437 | .handle_irq = x86_pmu_handle_irq, | |
3438 | .disable_all = x86_pmu_disable_all, | |
3439 | .enable_all = core_pmu_enable_all, | |
3440 | .enable = core_pmu_enable_event, | |
3441 | .disable = x86_pmu_disable_event, | |
3442 | .hw_config = x86_pmu_hw_config, | |
3443 | .schedule_events = x86_schedule_events, | |
3444 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, | |
3445 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
3446 | .event_map = intel_pmu_event_map, | |
3447 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), | |
3448 | .apic = 1, | |
a7b58d21 AK |
3449 | .free_running_flags = PEBS_FREERUNNING_FLAGS, |
3450 | ||
3b6e0421 JO |
3451 | /* |
3452 | * Intel PMCs cannot be accessed sanely above 32-bit width, | |
3453 | * so we install an artificial 1<<31 period regardless of | |
3454 | * the generic event period: | |
3455 | */ | |
3456 | .max_period = (1ULL<<31) - 1, | |
3457 | .get_event_constraints = intel_get_event_constraints, | |
3458 | .put_event_constraints = intel_put_event_constraints, | |
3459 | .event_constraints = intel_core_event_constraints, | |
3460 | .guest_get_msrs = core_guest_get_msrs, | |
3461 | .format_attrs = intel_arch_formats_attr, | |
3462 | .events_sysfs_show = intel_event_sysfs_show, | |
3463 | ||
3464 | /* | |
3465 | * Virtual (or funny metal) CPU can define x86_pmu.extra_regs | |
3466 | * together with PMU version 1 and thus be using core_pmu with | |
3467 | * shared_regs. We need following callbacks here to allocate | |
3468 | * it properly. | |
3469 | */ | |
3470 | .cpu_prepare = intel_pmu_cpu_prepare, | |
3471 | .cpu_starting = intel_pmu_cpu_starting, | |
3472 | .cpu_dying = intel_pmu_cpu_dying, | |
3473 | }; | |
3474 | ||
caaa8be3 | 3475 | static __initconst const struct x86_pmu intel_pmu = { |
f22f54f4 PZ |
3476 | .name = "Intel", |
3477 | .handle_irq = intel_pmu_handle_irq, | |
3478 | .disable_all = intel_pmu_disable_all, | |
3479 | .enable_all = intel_pmu_enable_all, | |
3480 | .enable = intel_pmu_enable_event, | |
3481 | .disable = intel_pmu_disable_event, | |
68f7082f PZ |
3482 | .add = intel_pmu_add_event, |
3483 | .del = intel_pmu_del_event, | |
b4cdc5c2 | 3484 | .hw_config = intel_pmu_hw_config, |
a072738e | 3485 | .schedule_events = x86_schedule_events, |
f22f54f4 PZ |
3486 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
3487 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
3488 | .event_map = intel_pmu_event_map, | |
f22f54f4 PZ |
3489 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
3490 | .apic = 1, | |
a7b58d21 | 3491 | .free_running_flags = PEBS_FREERUNNING_FLAGS, |
f22f54f4 PZ |
3492 | /* |
3493 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
3494 | * so we install an artificial 1<<31 period regardless of | |
3495 | * the generic event period: | |
3496 | */ | |
3497 | .max_period = (1ULL << 31) - 1, | |
3f6da390 | 3498 | .get_event_constraints = intel_get_event_constraints, |
a7e3ed1e | 3499 | .put_event_constraints = intel_put_event_constraints, |
0780c927 | 3500 | .pebs_aliases = intel_pebs_aliases_core2, |
3f6da390 | 3501 | |
641cc938 | 3502 | .format_attrs = intel_arch3_formats_attr, |
0bf79d44 | 3503 | .events_sysfs_show = intel_event_sysfs_show, |
641cc938 | 3504 | |
a7e3ed1e | 3505 | .cpu_prepare = intel_pmu_cpu_prepare, |
74846d35 PZ |
3506 | .cpu_starting = intel_pmu_cpu_starting, |
3507 | .cpu_dying = intel_pmu_cpu_dying, | |
144d31e6 | 3508 | .guest_get_msrs = intel_guest_get_msrs, |
9c964efa | 3509 | .sched_task = intel_pmu_sched_task, |
f22f54f4 PZ |
3510 | }; |
3511 | ||
c1d6f42f | 3512 | static __init void intel_clovertown_quirk(void) |
3c44780b PZ |
3513 | { |
3514 | /* | |
3515 | * PEBS is unreliable due to: | |
3516 | * | |
3517 | * AJ67 - PEBS may experience CPL leaks | |
3518 | * AJ68 - PEBS PMI may be delayed by one event | |
3519 | * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] | |
3520 | * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS | |
3521 | * | |
3522 | * AJ67 could be worked around by restricting the OS/USR flags. | |
3523 | * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. | |
3524 | * | |
3525 | * AJ106 could possibly be worked around by not allowing LBR | |
3526 | * usage from PEBS, including the fixup. | |
3527 | * AJ68 could possibly be worked around by always programming | |
ec75a716 | 3528 | * a pebs_event_reset[0] value and coping with the lost events. |
3c44780b PZ |
3529 | * |
3530 | * But taken together it might just make sense to not enable PEBS on | |
3531 | * these chips. | |
3532 | */ | |
c767a54b | 3533 | pr_warn("PEBS disabled due to CPU errata\n"); |
3c44780b PZ |
3534 | x86_pmu.pebs = 0; |
3535 | x86_pmu.pebs_constraints = NULL; | |
3536 | } | |
3537 | ||
c93dc84c PZ |
3538 | static int intel_snb_pebs_broken(int cpu) |
3539 | { | |
3540 | u32 rev = UINT_MAX; /* default to broken for unknown models */ | |
3541 | ||
3542 | switch (cpu_data(cpu).x86_model) { | |
ef5f9f47 | 3543 | case INTEL_FAM6_SANDYBRIDGE: |
c93dc84c PZ |
3544 | rev = 0x28; |
3545 | break; | |
3546 | ||
ef5f9f47 | 3547 | case INTEL_FAM6_SANDYBRIDGE_X: |
c93dc84c PZ |
3548 | switch (cpu_data(cpu).x86_mask) { |
3549 | case 6: rev = 0x618; break; | |
3550 | case 7: rev = 0x70c; break; | |
3551 | } | |
3552 | } | |
3553 | ||
3554 | return (cpu_data(cpu).microcode < rev); | |
3555 | } | |
3556 | ||
3557 | static void intel_snb_check_microcode(void) | |
3558 | { | |
3559 | int pebs_broken = 0; | |
3560 | int cpu; | |
3561 | ||
c93dc84c PZ |
3562 | for_each_online_cpu(cpu) { |
3563 | if ((pebs_broken = intel_snb_pebs_broken(cpu))) | |
3564 | break; | |
3565 | } | |
c93dc84c PZ |
3566 | |
3567 | if (pebs_broken == x86_pmu.pebs_broken) | |
3568 | return; | |
3569 | ||
3570 | /* | |
3571 | * Serialized by the microcode lock.. | |
3572 | */ | |
3573 | if (x86_pmu.pebs_broken) { | |
3574 | pr_info("PEBS enabled due to microcode update\n"); | |
3575 | x86_pmu.pebs_broken = 0; | |
3576 | } else { | |
3577 | pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); | |
3578 | x86_pmu.pebs_broken = 1; | |
3579 | } | |
3580 | } | |
3581 | ||
19fc9ddd DCC |
3582 | static bool is_lbr_from(unsigned long msr) |
3583 | { | |
3584 | unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; | |
3585 | ||
3586 | return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; | |
3587 | } | |
3588 | ||
338b522c KL |
3589 | /* |
3590 | * Under certain circumstances, access certain MSR may cause #GP. | |
3591 | * The function tests if the input MSR can be safely accessed. | |
3592 | */ | |
3593 | static bool check_msr(unsigned long msr, u64 mask) | |
3594 | { | |
3595 | u64 val_old, val_new, val_tmp; | |
3596 | ||
3597 | /* | |
3598 | * Read the current value, change it and read it back to see if it | |
3599 | * matches, this is needed to detect certain hardware emulators | |
3600 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
3601 | */ | |
3602 | if (rdmsrl_safe(msr, &val_old)) | |
3603 | return false; | |
3604 | ||
3605 | /* | |
3606 | * Only change the bits which can be updated by wrmsrl. | |
3607 | */ | |
3608 | val_tmp = val_old ^ mask; | |
19fc9ddd DCC |
3609 | |
3610 | if (is_lbr_from(msr)) | |
3611 | val_tmp = lbr_from_signext_quirk_wr(val_tmp); | |
3612 | ||
338b522c KL |
3613 | if (wrmsrl_safe(msr, val_tmp) || |
3614 | rdmsrl_safe(msr, &val_new)) | |
3615 | return false; | |
3616 | ||
19fc9ddd DCC |
3617 | /* |
3618 | * Quirk only affects validation in wrmsr(), so wrmsrl()'s value | |
3619 | * should equal rdmsrl()'s even with the quirk. | |
3620 | */ | |
338b522c KL |
3621 | if (val_new != val_tmp) |
3622 | return false; | |
3623 | ||
19fc9ddd DCC |
3624 | if (is_lbr_from(msr)) |
3625 | val_old = lbr_from_signext_quirk_wr(val_old); | |
3626 | ||
338b522c KL |
3627 | /* Here it's sure that the MSR can be safely accessed. |
3628 | * Restore the old value and return. | |
3629 | */ | |
3630 | wrmsrl(msr, val_old); | |
3631 | ||
3632 | return true; | |
3633 | } | |
3634 | ||
c1d6f42f | 3635 | static __init void intel_sandybridge_quirk(void) |
6a600a8b | 3636 | { |
c93dc84c | 3637 | x86_pmu.check_microcode = intel_snb_check_microcode; |
1ba143a5 | 3638 | cpus_read_lock(); |
c93dc84c | 3639 | intel_snb_check_microcode(); |
1ba143a5 | 3640 | cpus_read_unlock(); |
6a600a8b PZ |
3641 | } |
3642 | ||
c1d6f42f PZ |
3643 | static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { |
3644 | { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, | |
3645 | { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, | |
3646 | { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, | |
3647 | { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, | |
3648 | { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, | |
3649 | { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, | |
3650 | { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, | |
ffb871bc GN |
3651 | }; |
3652 | ||
c1d6f42f PZ |
3653 | static __init void intel_arch_events_quirk(void) |
3654 | { | |
3655 | int bit; | |
3656 | ||
3657 | /* disable event that reported as not presend by cpuid */ | |
3658 | for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { | |
3659 | intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; | |
c767a54b JP |
3660 | pr_warn("CPUID marked event: \'%s\' unavailable\n", |
3661 | intel_arch_events_map[bit].name); | |
c1d6f42f PZ |
3662 | } |
3663 | } | |
3664 | ||
3665 | static __init void intel_nehalem_quirk(void) | |
3666 | { | |
3667 | union cpuid10_ebx ebx; | |
3668 | ||
3669 | ebx.full = x86_pmu.events_maskl; | |
3670 | if (ebx.split.no_branch_misses_retired) { | |
3671 | /* | |
3672 | * Erratum AAJ80 detected, we work it around by using | |
3673 | * the BR_MISP_EXEC.ANY event. This will over-count | |
3674 | * branch-misses, but it's still much better than the | |
3675 | * architectural event which is often completely bogus: | |
3676 | */ | |
3677 | intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; | |
3678 | ebx.split.no_branch_misses_retired = 0; | |
3679 | x86_pmu.events_maskl = ebx.full; | |
c767a54b | 3680 | pr_info("CPU erratum AAJ80 worked around\n"); |
c1d6f42f PZ |
3681 | } |
3682 | } | |
3683 | ||
93fcf72c MD |
3684 | /* |
3685 | * enable software workaround for errata: | |
3686 | * SNB: BJ122 | |
3687 | * IVB: BV98 | |
3688 | * HSW: HSD29 | |
3689 | * | |
3690 | * Only needed when HT is enabled. However detecting | |
b37609c3 SE |
3691 | * if HT is enabled is difficult (model specific). So instead, |
3692 | * we enable the workaround in the early boot, and verify if | |
3693 | * it is needed in a later initcall phase once we have valid | |
3694 | * topology information to check if HT is actually enabled | |
93fcf72c MD |
3695 | */ |
3696 | static __init void intel_ht_bug(void) | |
3697 | { | |
b37609c3 | 3698 | x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; |
93fcf72c | 3699 | |
93fcf72c | 3700 | x86_pmu.start_scheduling = intel_start_scheduling; |
0c41e756 | 3701 | x86_pmu.commit_scheduling = intel_commit_scheduling; |
93fcf72c | 3702 | x86_pmu.stop_scheduling = intel_stop_scheduling; |
93fcf72c MD |
3703 | } |
3704 | ||
7f2ee91f IM |
3705 | EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); |
3706 | EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") | |
f9134f36 | 3707 | |
4b2c4f1f | 3708 | /* Haswell special events */ |
7f2ee91f IM |
3709 | EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); |
3710 | EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); | |
3711 | EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); | |
3712 | EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); | |
3713 | EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); | |
3714 | EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); | |
3715 | EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); | |
3716 | EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); | |
3717 | EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); | |
3718 | EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); | |
3719 | EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); | |
3720 | EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); | |
4b2c4f1f | 3721 | |
f9134f36 | 3722 | static struct attribute *hsw_events_attrs[] = { |
4b2c4f1f AK |
3723 | EVENT_PTR(tx_start), |
3724 | EVENT_PTR(tx_commit), | |
3725 | EVENT_PTR(tx_abort), | |
3726 | EVENT_PTR(tx_capacity), | |
3727 | EVENT_PTR(tx_conflict), | |
3728 | EVENT_PTR(el_start), | |
3729 | EVENT_PTR(el_commit), | |
3730 | EVENT_PTR(el_abort), | |
3731 | EVENT_PTR(el_capacity), | |
3732 | EVENT_PTR(el_conflict), | |
3733 | EVENT_PTR(cycles_t), | |
3734 | EVENT_PTR(cycles_ct), | |
f9134f36 AK |
3735 | EVENT_PTR(mem_ld_hsw), |
3736 | EVENT_PTR(mem_st_hsw), | |
a39fcae7 AK |
3737 | EVENT_PTR(td_slots_issued), |
3738 | EVENT_PTR(td_slots_retired), | |
3739 | EVENT_PTR(td_fetch_bubbles), | |
3740 | EVENT_PTR(td_total_slots), | |
3741 | EVENT_PTR(td_total_slots_scale), | |
3742 | EVENT_PTR(td_recovery_bubbles), | |
3743 | EVENT_PTR(td_recovery_bubbles_scale), | |
f9134f36 AK |
3744 | NULL |
3745 | }; | |
3746 | ||
6089327f KL |
3747 | static ssize_t freeze_on_smi_show(struct device *cdev, |
3748 | struct device_attribute *attr, | |
3749 | char *buf) | |
3750 | { | |
3751 | return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); | |
3752 | } | |
3753 | ||
3754 | static DEFINE_MUTEX(freeze_on_smi_mutex); | |
3755 | ||
3756 | static ssize_t freeze_on_smi_store(struct device *cdev, | |
3757 | struct device_attribute *attr, | |
3758 | const char *buf, size_t count) | |
3759 | { | |
3760 | unsigned long val; | |
3761 | ssize_t ret; | |
3762 | ||
3763 | ret = kstrtoul(buf, 0, &val); | |
3764 | if (ret) | |
3765 | return ret; | |
3766 | ||
3767 | if (val > 1) | |
3768 | return -EINVAL; | |
3769 | ||
3770 | mutex_lock(&freeze_on_smi_mutex); | |
3771 | ||
3772 | if (x86_pmu.attr_freeze_on_smi == val) | |
3773 | goto done; | |
3774 | ||
3775 | x86_pmu.attr_freeze_on_smi = val; | |
3776 | ||
3777 | get_online_cpus(); | |
3778 | on_each_cpu(flip_smm_bit, &val, 1); | |
3779 | put_online_cpus(); | |
3780 | done: | |
3781 | mutex_unlock(&freeze_on_smi_mutex); | |
3782 | ||
3783 | return count; | |
3784 | } | |
3785 | ||
3786 | static DEVICE_ATTR_RW(freeze_on_smi); | |
3787 | ||
3788 | static struct attribute *intel_pmu_attrs[] = { | |
3789 | &dev_attr_freeze_on_smi.attr, | |
3790 | NULL, | |
3791 | }; | |
3792 | ||
de0428a7 | 3793 | __init int intel_pmu_init(void) |
f22f54f4 PZ |
3794 | { |
3795 | union cpuid10_edx edx; | |
3796 | union cpuid10_eax eax; | |
ffb871bc | 3797 | union cpuid10_ebx ebx; |
a1eac7ac | 3798 | struct event_constraint *c; |
f22f54f4 | 3799 | unsigned int unused; |
338b522c KL |
3800 | struct extra_reg *er; |
3801 | int version, i; | |
f22f54f4 PZ |
3802 | |
3803 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { | |
a072738e CG |
3804 | switch (boot_cpu_data.x86) { |
3805 | case 0x6: | |
3806 | return p6_pmu_init(); | |
e717bf4e VW |
3807 | case 0xb: |
3808 | return knc_pmu_init(); | |
a072738e CG |
3809 | case 0xf: |
3810 | return p4_pmu_init(); | |
3811 | } | |
f22f54f4 | 3812 | return -ENODEV; |
f22f54f4 PZ |
3813 | } |
3814 | ||
3815 | /* | |
3816 | * Check whether the Architectural PerfMon supports | |
3817 | * Branch Misses Retired hw_event or not. | |
3818 | */ | |
ffb871bc GN |
3819 | cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); |
3820 | if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) | |
f22f54f4 PZ |
3821 | return -ENODEV; |
3822 | ||
3823 | version = eax.split.version_id; | |
3824 | if (version < 2) | |
3825 | x86_pmu = core_pmu; | |
3826 | else | |
3827 | x86_pmu = intel_pmu; | |
3828 | ||
3829 | x86_pmu.version = version; | |
948b1bb8 RR |
3830 | x86_pmu.num_counters = eax.split.num_counters; |
3831 | x86_pmu.cntval_bits = eax.split.bit_width; | |
3832 | x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; | |
f22f54f4 | 3833 | |
c1d6f42f PZ |
3834 | x86_pmu.events_maskl = ebx.full; |
3835 | x86_pmu.events_mask_len = eax.split.mask_length; | |
3836 | ||
70ab7003 AK |
3837 | x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); |
3838 | ||
6089327f KL |
3839 | |
3840 | x86_pmu.attrs = intel_pmu_attrs; | |
f22f54f4 PZ |
3841 | /* |
3842 | * Quirk: v2 perfmon does not report fixed-purpose events, so | |
f92b7604 | 3843 | * assume at least 3 events, when not running in a hypervisor: |
f22f54f4 | 3844 | */ |
f92b7604 IP |
3845 | if (version > 1) { |
3846 | int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); | |
3847 | ||
3848 | x86_pmu.num_counters_fixed = | |
3849 | max((int)edx.split.num_counters_fixed, assume); | |
3850 | } | |
f22f54f4 | 3851 | |
c9b08884 | 3852 | if (boot_cpu_has(X86_FEATURE_PDCM)) { |
8db909a7 PZ |
3853 | u64 capabilities; |
3854 | ||
3855 | rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); | |
3856 | x86_pmu.intel_cap.capabilities = capabilities; | |
3857 | } | |
3858 | ||
ca037701 PZ |
3859 | intel_ds_init(); |
3860 | ||
c1d6f42f PZ |
3861 | x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ |
3862 | ||
f22f54f4 PZ |
3863 | /* |
3864 | * Install the hw-cache-events table: | |
3865 | */ | |
3866 | switch (boot_cpu_data.x86_model) { | |
ef5f9f47 | 3867 | case INTEL_FAM6_CORE_YONAH: |
f22f54f4 PZ |
3868 | pr_cont("Core events, "); |
3869 | break; | |
3870 | ||
ef5f9f47 | 3871 | case INTEL_FAM6_CORE2_MEROM: |
c1d6f42f | 3872 | x86_add_quirk(intel_clovertown_quirk); |
ef5f9f47 DH |
3873 | case INTEL_FAM6_CORE2_MEROM_L: |
3874 | case INTEL_FAM6_CORE2_PENRYN: | |
3875 | case INTEL_FAM6_CORE2_DUNNINGTON: | |
f22f54f4 PZ |
3876 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
3877 | sizeof(hw_cache_event_ids)); | |
3878 | ||
caff2bef PZ |
3879 | intel_pmu_lbr_init_core(); |
3880 | ||
f22f54f4 | 3881 | x86_pmu.event_constraints = intel_core2_event_constraints; |
17e31629 | 3882 | x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; |
f22f54f4 PZ |
3883 | pr_cont("Core2 events, "); |
3884 | break; | |
3885 | ||
ef5f9f47 DH |
3886 | case INTEL_FAM6_NEHALEM: |
3887 | case INTEL_FAM6_NEHALEM_EP: | |
3888 | case INTEL_FAM6_NEHALEM_EX: | |
f22f54f4 PZ |
3889 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, |
3890 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
3891 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
3892 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 3893 | |
caff2bef PZ |
3894 | intel_pmu_lbr_init_nhm(); |
3895 | ||
f22f54f4 | 3896 | x86_pmu.event_constraints = intel_nehalem_event_constraints; |
17e31629 | 3897 | x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; |
11164cd4 | 3898 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
a7e3ed1e | 3899 | x86_pmu.extra_regs = intel_nehalem_extra_regs; |
ec75a716 | 3900 | |
f20093ee SE |
3901 | x86_pmu.cpu_events = nhm_events_attrs; |
3902 | ||
91fc4cc0 | 3903 | /* UOPS_ISSUED.STALLED_CYCLES */ |
f9b4eeb8 PZ |
3904 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
3905 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
91fc4cc0 | 3906 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
3907 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
3908 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
94403f88 | 3909 | |
e17dc653 | 3910 | intel_pmu_pebs_data_source_nhm(); |
c1d6f42f | 3911 | x86_add_quirk(intel_nehalem_quirk); |
f473bf9c | 3912 | x86_pmu.pebs_no_tlb = 1; |
ec75a716 | 3913 | |
11164cd4 | 3914 | pr_cont("Nehalem events, "); |
f22f54f4 | 3915 | break; |
caff2bef | 3916 | |
ef5f9f47 DH |
3917 | case INTEL_FAM6_ATOM_PINEVIEW: |
3918 | case INTEL_FAM6_ATOM_LINCROFT: | |
3919 | case INTEL_FAM6_ATOM_PENWELL: | |
3920 | case INTEL_FAM6_ATOM_CLOVERVIEW: | |
3921 | case INTEL_FAM6_ATOM_CEDARVIEW: | |
f22f54f4 PZ |
3922 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, |
3923 | sizeof(hw_cache_event_ids)); | |
3924 | ||
caff2bef PZ |
3925 | intel_pmu_lbr_init_atom(); |
3926 | ||
f22f54f4 | 3927 | x86_pmu.event_constraints = intel_gen_event_constraints; |
17e31629 | 3928 | x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; |
673d188b | 3929 | x86_pmu.pebs_aliases = intel_pebs_aliases_core2; |
f22f54f4 PZ |
3930 | pr_cont("Atom events, "); |
3931 | break; | |
3932 | ||
ef5f9f47 DH |
3933 | case INTEL_FAM6_ATOM_SILVERMONT1: |
3934 | case INTEL_FAM6_ATOM_SILVERMONT2: | |
3935 | case INTEL_FAM6_ATOM_AIRMONT: | |
1fa64180 YZ |
3936 | memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, |
3937 | sizeof(hw_cache_event_ids)); | |
3938 | memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, | |
3939 | sizeof(hw_cache_extra_regs)); | |
3940 | ||
f21d5adc | 3941 | intel_pmu_lbr_init_slm(); |
1fa64180 YZ |
3942 | |
3943 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
3944 | x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; | |
3945 | x86_pmu.extra_regs = intel_slm_extra_regs; | |
9a5e3fb5 | 3946 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
eb12b8ec | 3947 | x86_pmu.cpu_events = slm_events_attrs; |
1fa64180 YZ |
3948 | pr_cont("Silvermont events, "); |
3949 | break; | |
3950 | ||
ef5f9f47 DH |
3951 | case INTEL_FAM6_ATOM_GOLDMONT: |
3952 | case INTEL_FAM6_ATOM_DENVERTON: | |
8b92c3a7 KL |
3953 | memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, |
3954 | sizeof(hw_cache_event_ids)); | |
3955 | memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, | |
3956 | sizeof(hw_cache_extra_regs)); | |
3957 | ||
3958 | intel_pmu_lbr_init_skl(); | |
3959 | ||
3960 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
3961 | x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; | |
3962 | x86_pmu.extra_regs = intel_glm_extra_regs; | |
3963 | /* | |
3964 | * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS | |
3965 | * for precise cycles. | |
3966 | * :pp is identical to :ppp | |
3967 | */ | |
3968 | x86_pmu.pebs_aliases = NULL; | |
3969 | x86_pmu.pebs_prec_dist = true; | |
ccbebba4 | 3970 | x86_pmu.lbr_pt_coexist = true; |
8b92c3a7 | 3971 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
ed827adb | 3972 | x86_pmu.cpu_events = glm_events_attrs; |
8b92c3a7 KL |
3973 | pr_cont("Goldmont events, "); |
3974 | break; | |
3975 | ||
dd0b06b5 KL |
3976 | case INTEL_FAM6_ATOM_GEMINI_LAKE: |
3977 | memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, | |
3978 | sizeof(hw_cache_event_ids)); | |
3979 | memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, | |
3980 | sizeof(hw_cache_extra_regs)); | |
3981 | ||
3982 | intel_pmu_lbr_init_skl(); | |
3983 | ||
3984 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
3985 | x86_pmu.pebs_constraints = intel_glp_pebs_event_constraints; | |
3986 | x86_pmu.extra_regs = intel_glm_extra_regs; | |
3987 | /* | |
3988 | * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS | |
3989 | * for precise cycles. | |
3990 | */ | |
3991 | x86_pmu.pebs_aliases = NULL; | |
3992 | x86_pmu.pebs_prec_dist = true; | |
3993 | x86_pmu.lbr_pt_coexist = true; | |
3994 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
3995 | x86_pmu.get_event_constraints = glp_get_event_constraints; | |
3996 | x86_pmu.cpu_events = glm_events_attrs; | |
3997 | /* Goldmont Plus has 4-wide pipeline */ | |
3998 | event_attr_td_total_slots_scale_glm.event_str = "4"; | |
3999 | pr_cont("Goldmont plus events, "); | |
4000 | break; | |
4001 | ||
ef5f9f47 DH |
4002 | case INTEL_FAM6_WESTMERE: |
4003 | case INTEL_FAM6_WESTMERE_EP: | |
4004 | case INTEL_FAM6_WESTMERE_EX: | |
f22f54f4 PZ |
4005 | memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, |
4006 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
4007 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
4008 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 4009 | |
caff2bef PZ |
4010 | intel_pmu_lbr_init_nhm(); |
4011 | ||
f22f54f4 | 4012 | x86_pmu.event_constraints = intel_westmere_event_constraints; |
40b91cd1 | 4013 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
17e31629 | 4014 | x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; |
a7e3ed1e | 4015 | x86_pmu.extra_regs = intel_westmere_extra_regs; |
9a5e3fb5 | 4016 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
30112039 | 4017 | |
f20093ee SE |
4018 | x86_pmu.cpu_events = nhm_events_attrs; |
4019 | ||
30112039 | 4020 | /* UOPS_ISSUED.STALLED_CYCLES */ |
f9b4eeb8 PZ |
4021 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
4022 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
30112039 | 4023 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
4024 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
4025 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
30112039 | 4026 | |
e17dc653 | 4027 | intel_pmu_pebs_data_source_nhm(); |
f22f54f4 PZ |
4028 | pr_cont("Westmere events, "); |
4029 | break; | |
b622d644 | 4030 | |
ef5f9f47 DH |
4031 | case INTEL_FAM6_SANDYBRIDGE: |
4032 | case INTEL_FAM6_SANDYBRIDGE_X: | |
47a8863d | 4033 | x86_add_quirk(intel_sandybridge_quirk); |
93fcf72c | 4034 | x86_add_quirk(intel_ht_bug); |
b06b3d49 LM |
4035 | memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, |
4036 | sizeof(hw_cache_event_ids)); | |
74e6543f YZ |
4037 | memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, |
4038 | sizeof(hw_cache_extra_regs)); | |
b06b3d49 | 4039 | |
c5cc2cd9 | 4040 | intel_pmu_lbr_init_snb(); |
b06b3d49 LM |
4041 | |
4042 | x86_pmu.event_constraints = intel_snb_event_constraints; | |
de0428a7 | 4043 | x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; |
0780c927 | 4044 | x86_pmu.pebs_aliases = intel_pebs_aliases_snb; |
ef5f9f47 | 4045 | if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) |
f1923820 SE |
4046 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
4047 | else | |
4048 | x86_pmu.extra_regs = intel_snb_extra_regs; | |
93fcf72c MD |
4049 | |
4050 | ||
ee89cbc2 | 4051 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
4052 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
4053 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
e04d1b23 | 4054 | |
f20093ee SE |
4055 | x86_pmu.cpu_events = snb_events_attrs; |
4056 | ||
e04d1b23 | 4057 | /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ |
f9b4eeb8 PZ |
4058 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
4059 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 4060 | /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ |
f9b4eeb8 PZ |
4061 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
4062 | X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 4063 | |
b06b3d49 LM |
4064 | pr_cont("SandyBridge events, "); |
4065 | break; | |
0f7c29ce | 4066 | |
ef5f9f47 DH |
4067 | case INTEL_FAM6_IVYBRIDGE: |
4068 | case INTEL_FAM6_IVYBRIDGE_X: | |
93fcf72c | 4069 | x86_add_quirk(intel_ht_bug); |
20a36e39 SE |
4070 | memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, |
4071 | sizeof(hw_cache_event_ids)); | |
1996388e VW |
4072 | /* dTLB-load-misses on IVB is different than SNB */ |
4073 | hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ | |
4074 | ||
20a36e39 SE |
4075 | memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, |
4076 | sizeof(hw_cache_extra_regs)); | |
4077 | ||
4078 | intel_pmu_lbr_init_snb(); | |
4079 | ||
69943182 | 4080 | x86_pmu.event_constraints = intel_ivb_event_constraints; |
20a36e39 | 4081 | x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; |
72469764 AK |
4082 | x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; |
4083 | x86_pmu.pebs_prec_dist = true; | |
ef5f9f47 | 4084 | if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) |
f1923820 SE |
4085 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
4086 | else | |
4087 | x86_pmu.extra_regs = intel_snb_extra_regs; | |
20a36e39 | 4088 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
4089 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
4090 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
20a36e39 | 4091 | |
f20093ee SE |
4092 | x86_pmu.cpu_events = snb_events_attrs; |
4093 | ||
20a36e39 SE |
4094 | /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ |
4095 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = | |
4096 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
4097 | ||
4098 | pr_cont("IvyBridge events, "); | |
4099 | break; | |
4100 | ||
b06b3d49 | 4101 | |
ef5f9f47 DH |
4102 | case INTEL_FAM6_HASWELL_CORE: |
4103 | case INTEL_FAM6_HASWELL_X: | |
4104 | case INTEL_FAM6_HASWELL_ULT: | |
4105 | case INTEL_FAM6_HASWELL_GT3E: | |
93fcf72c | 4106 | x86_add_quirk(intel_ht_bug); |
72db5596 | 4107 | x86_pmu.late_ack = true; |
0f1b5ca2 AK |
4108 | memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); |
4109 | memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
3a632cb2 | 4110 | |
e9d7f7cd | 4111 | intel_pmu_lbr_init_hsw(); |
3a632cb2 AK |
4112 | |
4113 | x86_pmu.event_constraints = intel_hsw_event_constraints; | |
3044318f | 4114 | x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; |
36bbb2f2 | 4115 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
72469764 AK |
4116 | x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; |
4117 | x86_pmu.pebs_prec_dist = true; | |
3a632cb2 | 4118 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
4119 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
4120 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
3a632cb2 AK |
4121 | |
4122 | x86_pmu.hw_config = hsw_hw_config; | |
4123 | x86_pmu.get_event_constraints = hsw_get_event_constraints; | |
f9134f36 | 4124 | x86_pmu.cpu_events = hsw_events_attrs; |
b7af41a1 | 4125 | x86_pmu.lbr_double_abort = true; |
3a632cb2 AK |
4126 | pr_cont("Haswell events, "); |
4127 | break; | |
4128 | ||
ef5f9f47 DH |
4129 | case INTEL_FAM6_BROADWELL_CORE: |
4130 | case INTEL_FAM6_BROADWELL_XEON_D: | |
4131 | case INTEL_FAM6_BROADWELL_GT3E: | |
4132 | case INTEL_FAM6_BROADWELL_X: | |
91f1b705 AK |
4133 | x86_pmu.late_ack = true; |
4134 | memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
4135 | memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
4136 | ||
4137 | /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ | |
4138 | hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | | |
4139 | BDW_L3_MISS|HSW_SNOOP_DRAM; | |
4140 | hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| | |
4141 | HSW_SNOOP_DRAM; | |
4142 | hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| | |
4143 | BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; | |
4144 | hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| | |
4145 | BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; | |
4146 | ||
78d504bc | 4147 | intel_pmu_lbr_init_hsw(); |
91f1b705 AK |
4148 | |
4149 | x86_pmu.event_constraints = intel_bdw_event_constraints; | |
b3e62463 | 4150 | x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; |
91f1b705 | 4151 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
72469764 AK |
4152 | x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; |
4153 | x86_pmu.pebs_prec_dist = true; | |
91f1b705 | 4154 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
4155 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
4156 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
91f1b705 AK |
4157 | |
4158 | x86_pmu.hw_config = hsw_hw_config; | |
4159 | x86_pmu.get_event_constraints = hsw_get_event_constraints; | |
4160 | x86_pmu.cpu_events = hsw_events_attrs; | |
294fe0f5 | 4161 | x86_pmu.limit_period = bdw_limit_period; |
91f1b705 AK |
4162 | pr_cont("Broadwell events, "); |
4163 | break; | |
4164 | ||
ef5f9f47 | 4165 | case INTEL_FAM6_XEON_PHI_KNL: |
608284bf | 4166 | case INTEL_FAM6_XEON_PHI_KNM: |
1e7b9390 HC |
4167 | memcpy(hw_cache_event_ids, |
4168 | slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
4169 | memcpy(hw_cache_extra_regs, | |
4170 | knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
4171 | intel_pmu_lbr_init_knl(); | |
4172 | ||
4173 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
4174 | x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; | |
4175 | x86_pmu.extra_regs = intel_knl_extra_regs; | |
4176 | ||
4177 | /* all extra regs are per-cpu when HT is on */ | |
4178 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
4179 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
4180 | ||
608284bf | 4181 | pr_cont("Knights Landing/Mill events, "); |
1e7b9390 HC |
4182 | break; |
4183 | ||
ef5f9f47 DH |
4184 | case INTEL_FAM6_SKYLAKE_MOBILE: |
4185 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
4186 | case INTEL_FAM6_SKYLAKE_X: | |
4187 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
4188 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
9a92e16f AK |
4189 | x86_pmu.late_ack = true; |
4190 | memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
4191 | memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
4192 | intel_pmu_lbr_init_skl(); | |
4193 | ||
a39fcae7 AK |
4194 | /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ |
4195 | event_attr_td_recovery_bubbles.event_str_noht = | |
4196 | "event=0xd,umask=0x1,cmask=1"; | |
4197 | event_attr_td_recovery_bubbles.event_str_ht = | |
4198 | "event=0xd,umask=0x1,cmask=1,any=1"; | |
4199 | ||
9a92e16f AK |
4200 | x86_pmu.event_constraints = intel_skl_event_constraints; |
4201 | x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; | |
4202 | x86_pmu.extra_regs = intel_skl_extra_regs; | |
72469764 AK |
4203 | x86_pmu.pebs_aliases = intel_pebs_aliases_skl; |
4204 | x86_pmu.pebs_prec_dist = true; | |
9a92e16f AK |
4205 | /* all extra regs are per-cpu when HT is on */ |
4206 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
4207 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
4208 | ||
4209 | x86_pmu.hw_config = hsw_hw_config; | |
4210 | x86_pmu.get_event_constraints = hsw_get_event_constraints; | |
d0dc8494 AK |
4211 | x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, |
4212 | skl_format_attr); | |
9a92e16f AK |
4213 | WARN_ON(!x86_pmu.format_attrs); |
4214 | x86_pmu.cpu_events = hsw_events_attrs; | |
39ae1ca8 AK |
4215 | intel_pmu_pebs_data_source_skl( |
4216 | boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X); | |
9a92e16f AK |
4217 | pr_cont("Skylake events, "); |
4218 | break; | |
4219 | ||
f22f54f4 | 4220 | default: |
0af3ac1f AK |
4221 | switch (x86_pmu.version) { |
4222 | case 1: | |
4223 | x86_pmu.event_constraints = intel_v1_event_constraints; | |
4224 | pr_cont("generic architected perfmon v1, "); | |
4225 | break; | |
4226 | default: | |
4227 | /* | |
4228 | * default constraints for v2 and up | |
4229 | */ | |
4230 | x86_pmu.event_constraints = intel_gen_event_constraints; | |
4231 | pr_cont("generic architected perfmon, "); | |
4232 | break; | |
4233 | } | |
f22f54f4 | 4234 | } |
ffb871bc | 4235 | |
a1eac7ac RR |
4236 | if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { |
4237 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", | |
4238 | x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); | |
4239 | x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; | |
4240 | } | |
ad5013d5 | 4241 | x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; |
a1eac7ac RR |
4242 | |
4243 | if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { | |
4244 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", | |
4245 | x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); | |
4246 | x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; | |
4247 | } | |
4248 | ||
4249 | x86_pmu.intel_ctrl |= | |
4250 | ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; | |
4251 | ||
4252 | if (x86_pmu.event_constraints) { | |
4253 | /* | |
4254 | * event on fixed counter2 (REF_CYCLES) only works on this | |
4255 | * counter, so do not extend mask to generic counters | |
4256 | */ | |
4257 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
2c33645d PI |
4258 | if (c->cmask == FIXED_EVENT_FLAGS |
4259 | && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { | |
4260 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; | |
a1eac7ac | 4261 | } |
2c33645d | 4262 | c->idxmsk64 &= |
6d6f2833 | 4263 | ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); |
2c33645d | 4264 | c->weight = hweight64(c->idxmsk64); |
a1eac7ac RR |
4265 | } |
4266 | } | |
4267 | ||
338b522c KL |
4268 | /* |
4269 | * Access LBR MSR may cause #GP under certain circumstances. | |
4270 | * E.g. KVM doesn't support LBR MSR | |
4271 | * Check all LBT MSR here. | |
4272 | * Disable LBR access if any LBR MSRs can not be accessed. | |
4273 | */ | |
4274 | if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) | |
4275 | x86_pmu.lbr_nr = 0; | |
4276 | for (i = 0; i < x86_pmu.lbr_nr; i++) { | |
4277 | if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && | |
4278 | check_msr(x86_pmu.lbr_to + i, 0xffffUL))) | |
4279 | x86_pmu.lbr_nr = 0; | |
4280 | } | |
4281 | ||
f09509b9 DCC |
4282 | if (x86_pmu.lbr_nr) |
4283 | pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); | |
338b522c KL |
4284 | /* |
4285 | * Access extra MSR may cause #GP under certain circumstances. | |
4286 | * E.g. KVM doesn't support offcore event | |
4287 | * Check all extra_regs here. | |
4288 | */ | |
4289 | if (x86_pmu.extra_regs) { | |
4290 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
8c4fe709 | 4291 | er->extra_msr_access = check_msr(er->msr, 0x11UL); |
338b522c KL |
4292 | /* Disable LBR select mapping */ |
4293 | if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) | |
4294 | x86_pmu.lbr_sel_map = NULL; | |
4295 | } | |
4296 | } | |
4297 | ||
069e0c3c AK |
4298 | /* Support full width counters using alternative MSR range */ |
4299 | if (x86_pmu.intel_cap.full_width_write) { | |
7f612a7f | 4300 | x86_pmu.max_period = x86_pmu.cntval_mask >> 1; |
069e0c3c AK |
4301 | x86_pmu.perfctr = MSR_IA32_PMC0; |
4302 | pr_cont("full-width counters, "); | |
4303 | } | |
4304 | ||
f22f54f4 PZ |
4305 | return 0; |
4306 | } | |
b37609c3 SE |
4307 | |
4308 | /* | |
4309 | * HT bug: phase 2 init | |
4310 | * Called once we have valid topology information to check | |
4311 | * whether or not HT is enabled | |
4312 | * If HT is off, then we disable the workaround | |
4313 | */ | |
4314 | static __init int fixup_ht_bug(void) | |
4315 | { | |
030ba6cd | 4316 | int c; |
b37609c3 SE |
4317 | /* |
4318 | * problem not present on this CPU model, nothing to do | |
4319 | */ | |
4320 | if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) | |
4321 | return 0; | |
4322 | ||
030ba6cd | 4323 | if (topology_max_smt_threads() > 1) { |
b37609c3 SE |
4324 | pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); |
4325 | return 0; | |
4326 | } | |
4327 | ||
ec6a9066 | 4328 | if (lockup_detector_suspend() != 0) { |
999bbe49 UO |
4329 | pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n"); |
4330 | return 0; | |
4331 | } | |
b37609c3 SE |
4332 | |
4333 | x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); | |
4334 | ||
b37609c3 | 4335 | x86_pmu.start_scheduling = NULL; |
0c41e756 | 4336 | x86_pmu.commit_scheduling = NULL; |
b37609c3 SE |
4337 | x86_pmu.stop_scheduling = NULL; |
4338 | ||
ec6a9066 | 4339 | lockup_detector_resume(); |
b37609c3 | 4340 | |
1ba143a5 | 4341 | cpus_read_lock(); |
b37609c3 | 4342 | |
1ba143a5 | 4343 | for_each_online_cpu(c) |
b37609c3 | 4344 | free_excl_cntrs(c); |
b37609c3 | 4345 | |
1ba143a5 | 4346 | cpus_read_unlock(); |
b37609c3 SE |
4347 | pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); |
4348 | return 0; | |
4349 | } | |
4350 | subsys_initcall(fixup_ht_bug) |