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Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a7e3ed1e | 2 | /* |
efc9f05d SE |
3 | * Per core/cpu state |
4 | * | |
5 | * Used to coordinate shared registers between HT threads or | |
6 | * among events on a single PMU. | |
a7e3ed1e | 7 | */ |
de0428a7 | 8 | |
c767a54b JP |
9 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
10 | ||
de0428a7 KW |
11 | #include <linux/stddef.h> |
12 | #include <linux/types.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
69c60c88 | 15 | #include <linux/export.h> |
aacfbe6a | 16 | #include <linux/nmi.h> |
de0428a7 | 17 | |
3a632cb2 | 18 | #include <asm/cpufeature.h> |
de0428a7 | 19 | #include <asm/hardirq.h> |
ef5f9f47 | 20 | #include <asm/intel-family.h> |
42880f72 | 21 | #include <asm/intel_pt.h> |
de0428a7 | 22 | #include <asm/apic.h> |
9b545c04 | 23 | #include <asm/cpu_device_id.h> |
de0428a7 | 24 | |
27f6d22b | 25 | #include "../perf_event.h" |
a7e3ed1e | 26 | |
f22f54f4 | 27 | /* |
b622d644 | 28 | * Intel PerfMon, used on Core and later. |
f22f54f4 | 29 | */ |
ec75a716 | 30 | static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = |
f22f54f4 | 31 | { |
c3b7cdf1 PE |
32 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
33 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
34 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
35 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
36 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
37 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
38 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
39 | [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ | |
f22f54f4 PZ |
40 | }; |
41 | ||
5c543e3c | 42 | static struct event_constraint intel_core_event_constraints[] __read_mostly = |
f22f54f4 PZ |
43 | { |
44 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
45 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
46 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
47 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
48 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
49 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ | |
50 | EVENT_CONSTRAINT_END | |
51 | }; | |
52 | ||
5c543e3c | 53 | static struct event_constraint intel_core2_event_constraints[] __read_mostly = |
f22f54f4 | 54 | { |
b622d644 PZ |
55 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
56 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 57 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
58 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
59 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
60 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
61 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
62 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
63 | INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ | |
64 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
65 | INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ | |
b622d644 | 66 | INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ |
f22f54f4 PZ |
67 | INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ |
68 | EVENT_CONSTRAINT_END | |
69 | }; | |
70 | ||
5c543e3c | 71 | static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = |
f22f54f4 | 72 | { |
b622d644 PZ |
73 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
74 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 75 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
76 | INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ |
77 | INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ | |
78 | INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ | |
79 | INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ | |
80 | INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ | |
81 | INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ | |
82 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ | |
83 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
84 | EVENT_CONSTRAINT_END | |
85 | }; | |
86 | ||
5c543e3c | 87 | static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = |
a7e3ed1e | 88 | { |
53ad0447 YZ |
89 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
90 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), | |
f20093ee | 91 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), |
a7e3ed1e AK |
92 | EVENT_EXTRA_END |
93 | }; | |
94 | ||
5c543e3c | 95 | static struct event_constraint intel_westmere_event_constraints[] __read_mostly = |
f22f54f4 | 96 | { |
b622d644 PZ |
97 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
98 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 99 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
100 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ |
101 | INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ | |
102 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
d1100770 | 103 | INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ |
f22f54f4 PZ |
104 | EVENT_CONSTRAINT_END |
105 | }; | |
106 | ||
5c543e3c | 107 | static struct event_constraint intel_snb_event_constraints[] __read_mostly = |
b06b3d49 LM |
108 | { |
109 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
110 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 111 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
fd4a5aef SE |
112 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ |
113 | INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ | |
114 | INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
115 | INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ | |
b06b3d49 | 116 | INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ |
b06b3d49 LM |
117 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ |
118 | INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ | |
f8378f52 AK |
119 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ |
120 | INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
93fcf72c | 121 | |
9010ae4a SE |
122 | /* |
123 | * When HT is off these events can only run on the bottom 4 counters | |
124 | * When HT is on, they are impacted by the HT bug and require EXCL access | |
125 | */ | |
93fcf72c MD |
126 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ |
127 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
128 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
129 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
130 | ||
b06b3d49 LM |
131 | EVENT_CONSTRAINT_END |
132 | }; | |
133 | ||
69943182 SE |
134 | static struct event_constraint intel_ivb_event_constraints[] __read_mostly = |
135 | { | |
136 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
137 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
138 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
139 | INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ | |
d9f6e12f | 140 | INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ |
69943182 | 141 | INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ |
6113af14 | 142 | INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ |
69943182 SE |
143 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ |
144 | INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ | |
145 | INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ | |
146 | INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
147 | INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ | |
148 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ | |
93fcf72c | 149 | |
9010ae4a SE |
150 | /* |
151 | * When HT is off these events can only run on the bottom 4 counters | |
152 | * When HT is on, they are impacted by the HT bug and require EXCL access | |
153 | */ | |
93fcf72c MD |
154 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ |
155 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
156 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
157 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
158 | ||
69943182 SE |
159 | EVENT_CONSTRAINT_END |
160 | }; | |
161 | ||
5c543e3c | 162 | static struct extra_reg intel_westmere_extra_regs[] __read_mostly = |
a7e3ed1e | 163 | { |
53ad0447 YZ |
164 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
165 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), | |
166 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), | |
f20093ee | 167 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), |
a7e3ed1e AK |
168 | EVENT_EXTRA_END |
169 | }; | |
170 | ||
0af3ac1f AK |
171 | static struct event_constraint intel_v1_event_constraints[] __read_mostly = |
172 | { | |
173 | EVENT_CONSTRAINT_END | |
174 | }; | |
175 | ||
5c543e3c | 176 | static struct event_constraint intel_gen_event_constraints[] __read_mostly = |
f22f54f4 | 177 | { |
b622d644 PZ |
178 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
179 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 180 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
181 | EVENT_CONSTRAINT_END |
182 | }; | |
183 | ||
1fa64180 YZ |
184 | static struct event_constraint intel_slm_event_constraints[] __read_mostly = |
185 | { | |
186 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
187 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
1fa64180 YZ |
188 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ |
189 | EVENT_CONSTRAINT_END | |
190 | }; | |
191 | ||
20f36278 | 192 | static struct event_constraint intel_skl_event_constraints[] = { |
9a92e16f AK |
193 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
194 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
195 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
196 | INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ | |
9010ae4a SE |
197 | |
198 | /* | |
199 | * when HT is off, these can only run on the bottom 4 counters | |
200 | */ | |
201 | INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ | |
202 | INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ | |
203 | INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ | |
204 | INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ | |
205 | INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ | |
206 | ||
9a92e16f AK |
207 | EVENT_CONSTRAINT_END |
208 | }; | |
209 | ||
1e7b9390 | 210 | static struct extra_reg intel_knl_extra_regs[] __read_mostly = { |
9c489fce LO |
211 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), |
212 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), | |
1e7b9390 HC |
213 | EVENT_EXTRA_END |
214 | }; | |
215 | ||
ee89cbc2 | 216 | static struct extra_reg intel_snb_extra_regs[] __read_mostly = { |
53ad0447 YZ |
217 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
218 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), | |
219 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), | |
f20093ee | 220 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), |
f1923820 SE |
221 | EVENT_EXTRA_END |
222 | }; | |
223 | ||
224 | static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { | |
53ad0447 YZ |
225 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ |
226 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), | |
227 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), | |
f1a52789 | 228 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), |
ee89cbc2 SE |
229 | EVENT_EXTRA_END |
230 | }; | |
231 | ||
9a92e16f AK |
232 | static struct extra_reg intel_skl_extra_regs[] __read_mostly = { |
233 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), | |
234 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), | |
235 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), | |
dfe1f3cb AK |
236 | /* |
237 | * Note the low 8 bits eventsel code is not a continuous field, containing | |
238 | * some #GPing bits. These are masked out. | |
239 | */ | |
240 | INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), | |
9a92e16f AK |
241 | EVENT_EXTRA_END |
242 | }; | |
243 | ||
60176089 KL |
244 | static struct event_constraint intel_icl_event_constraints[] = { |
245 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
31f6c02c SE |
246 | FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ |
247 | FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ | |
60176089 KL |
248 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ |
249 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
250 | FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ | |
59a854e2 KL |
251 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), |
252 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), | |
253 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), | |
254 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), | |
60176089 KL |
255 | INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), |
256 | INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), | |
257 | INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ | |
258 | INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), | |
259 | INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), | |
260 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ | |
306e3e91 KL |
261 | INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ |
262 | INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ | |
60176089 KL |
263 | INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ |
264 | INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), | |
265 | INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), | |
266 | INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), | |
ecc2123e | 267 | INTEL_EVENT_CONSTRAINT(0xef, 0xf), |
60176089 KL |
268 | INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), |
269 | EVENT_CONSTRAINT_END | |
270 | }; | |
271 | ||
272 | static struct extra_reg intel_icl_extra_regs[] __read_mostly = { | |
3b238a64 YS |
273 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), |
274 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), | |
60176089 KL |
275 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), |
276 | INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), | |
277 | EVENT_EXTRA_END | |
278 | }; | |
279 | ||
61b985e3 KL |
280 | static struct extra_reg intel_spr_extra_regs[] __read_mostly = { |
281 | INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), | |
282 | INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), | |
283 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), | |
1eb5faf1 | 284 | INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), |
d18216fa KL |
285 | INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), |
286 | INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), | |
61b985e3 KL |
287 | EVENT_EXTRA_END |
288 | }; | |
289 | ||
290 | static struct event_constraint intel_spr_event_constraints[] = { | |
291 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
31f6c02c | 292 | FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ |
61b985e3 KL |
293 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ |
294 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
295 | FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ | |
296 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), | |
297 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), | |
298 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), | |
299 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), | |
300 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), | |
301 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), | |
302 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), | |
303 | METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), | |
304 | ||
305 | INTEL_EVENT_CONSTRAINT(0x2e, 0xff), | |
306 | INTEL_EVENT_CONSTRAINT(0x3c, 0xff), | |
307 | /* | |
308 | * Generally event codes < 0x90 are restricted to counters 0-3. | |
309 | * The 0x2E and 0x3C are exception, which has no restriction. | |
310 | */ | |
311 | INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), | |
312 | ||
313 | INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), | |
314 | INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), | |
315 | INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), | |
316 | INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), | |
317 | INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), | |
318 | INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), | |
319 | INTEL_EVENT_CONSTRAINT(0xce, 0x1), | |
320 | INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), | |
321 | /* | |
322 | * Generally event codes >= 0x90 are likely to have no restrictions. | |
323 | * The exception are defined as above. | |
324 | */ | |
325 | INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), | |
326 | ||
327 | EVENT_CONSTRAINT_END | |
328 | }; | |
329 | ||
330 | ||
7f2ee91f IM |
331 | EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); |
332 | EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); | |
333 | EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); | |
f20093ee | 334 | |
d4ae5529 | 335 | static struct attribute *nhm_mem_events_attrs[] = { |
f20093ee SE |
336 | EVENT_PTR(mem_ld_nhm), |
337 | NULL, | |
338 | }; | |
339 | ||
a39fcae7 AK |
340 | /* |
341 | * topdown events for Intel Core CPUs. | |
342 | * | |
343 | * The events are all in slots, which is a free slot in a 4 wide | |
344 | * pipeline. Some events are already reported in slots, for cycle | |
345 | * events we multiply by the pipeline width (4). | |
346 | * | |
347 | * With Hyper Threading on, topdown metrics are either summed or averaged | |
348 | * between the threads of a core: (count_t0 + count_t1). | |
349 | * | |
350 | * For the average case the metric is always scaled to pipeline width, | |
351 | * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) | |
352 | */ | |
353 | ||
354 | EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, | |
355 | "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ | |
356 | "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ | |
357 | EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); | |
358 | EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, | |
359 | "event=0xe,umask=0x1"); /* uops_issued.any */ | |
360 | EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, | |
361 | "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ | |
362 | EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, | |
363 | "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ | |
364 | EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, | |
365 | "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ | |
366 | "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ | |
367 | EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, | |
368 | "4", "2"); | |
369 | ||
61b985e3 KL |
370 | EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); |
371 | EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); | |
372 | EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); | |
373 | EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); | |
374 | EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); | |
375 | EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); | |
376 | EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); | |
377 | EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); | |
378 | EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); | |
59a854e2 | 379 | |
20f36278 | 380 | static struct attribute *snb_events_attrs[] = { |
a39fcae7 AK |
381 | EVENT_PTR(td_slots_issued), |
382 | EVENT_PTR(td_slots_retired), | |
383 | EVENT_PTR(td_fetch_bubbles), | |
384 | EVENT_PTR(td_total_slots), | |
385 | EVENT_PTR(td_total_slots_scale), | |
386 | EVENT_PTR(td_recovery_bubbles), | |
387 | EVENT_PTR(td_recovery_bubbles_scale), | |
f20093ee SE |
388 | NULL, |
389 | }; | |
390 | ||
d4ae5529 JO |
391 | static struct attribute *snb_mem_events_attrs[] = { |
392 | EVENT_PTR(mem_ld_snb), | |
393 | EVENT_PTR(mem_st_snb), | |
394 | NULL, | |
395 | }; | |
396 | ||
3a632cb2 AK |
397 | static struct event_constraint intel_hsw_event_constraints[] = { |
398 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
399 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
400 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
e0fbac1c | 401 | INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ |
3a632cb2 AK |
402 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ |
403 | INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ | |
404 | /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ | |
c420f19b | 405 | INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), |
3a632cb2 | 406 | /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ |
c420f19b | 407 | INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), |
3a632cb2 | 408 | /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ |
c420f19b | 409 | INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), |
93fcf72c | 410 | |
9010ae4a SE |
411 | /* |
412 | * When HT is off these events can only run on the bottom 4 counters | |
413 | * When HT is on, they are impacted by the HT bug and require EXCL access | |
414 | */ | |
93fcf72c MD |
415 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ |
416 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
417 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
418 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
419 | ||
3a632cb2 AK |
420 | EVENT_CONSTRAINT_END |
421 | }; | |
422 | ||
20f36278 | 423 | static struct event_constraint intel_bdw_event_constraints[] = { |
91f1b705 AK |
424 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
425 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
426 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ | |
427 | INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ | |
b7883a1c | 428 | INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ |
9010ae4a SE |
429 | /* |
430 | * when HT is off, these can only run on the bottom 4 counters | |
431 | */ | |
432 | INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ | |
433 | INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ | |
434 | INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ | |
435 | INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ | |
91f1b705 AK |
436 | EVENT_CONSTRAINT_END |
437 | }; | |
438 | ||
f22f54f4 PZ |
439 | static u64 intel_pmu_event_map(int hw_event) |
440 | { | |
441 | return intel_perfmon_event_map[hw_event]; | |
442 | } | |
443 | ||
61b985e3 KL |
444 | static __initconst const u64 spr_hw_cache_event_ids |
445 | [PERF_COUNT_HW_CACHE_MAX] | |
446 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
447 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
448 | { | |
449 | [ C(L1D ) ] = { | |
450 | [ C(OP_READ) ] = { | |
451 | [ C(RESULT_ACCESS) ] = 0x81d0, | |
452 | [ C(RESULT_MISS) ] = 0xe124, | |
453 | }, | |
454 | [ C(OP_WRITE) ] = { | |
455 | [ C(RESULT_ACCESS) ] = 0x82d0, | |
456 | }, | |
457 | }, | |
458 | [ C(L1I ) ] = { | |
459 | [ C(OP_READ) ] = { | |
460 | [ C(RESULT_MISS) ] = 0xe424, | |
461 | }, | |
462 | [ C(OP_WRITE) ] = { | |
463 | [ C(RESULT_ACCESS) ] = -1, | |
464 | [ C(RESULT_MISS) ] = -1, | |
465 | }, | |
466 | }, | |
467 | [ C(LL ) ] = { | |
468 | [ C(OP_READ) ] = { | |
469 | [ C(RESULT_ACCESS) ] = 0x12a, | |
470 | [ C(RESULT_MISS) ] = 0x12a, | |
471 | }, | |
472 | [ C(OP_WRITE) ] = { | |
473 | [ C(RESULT_ACCESS) ] = 0x12a, | |
474 | [ C(RESULT_MISS) ] = 0x12a, | |
475 | }, | |
476 | }, | |
477 | [ C(DTLB) ] = { | |
478 | [ C(OP_READ) ] = { | |
479 | [ C(RESULT_ACCESS) ] = 0x81d0, | |
480 | [ C(RESULT_MISS) ] = 0xe12, | |
481 | }, | |
482 | [ C(OP_WRITE) ] = { | |
483 | [ C(RESULT_ACCESS) ] = 0x82d0, | |
484 | [ C(RESULT_MISS) ] = 0xe13, | |
485 | }, | |
486 | }, | |
487 | [ C(ITLB) ] = { | |
488 | [ C(OP_READ) ] = { | |
489 | [ C(RESULT_ACCESS) ] = -1, | |
490 | [ C(RESULT_MISS) ] = 0xe11, | |
491 | }, | |
492 | [ C(OP_WRITE) ] = { | |
493 | [ C(RESULT_ACCESS) ] = -1, | |
494 | [ C(RESULT_MISS) ] = -1, | |
495 | }, | |
496 | [ C(OP_PREFETCH) ] = { | |
497 | [ C(RESULT_ACCESS) ] = -1, | |
498 | [ C(RESULT_MISS) ] = -1, | |
499 | }, | |
500 | }, | |
501 | [ C(BPU ) ] = { | |
502 | [ C(OP_READ) ] = { | |
503 | [ C(RESULT_ACCESS) ] = 0x4c4, | |
504 | [ C(RESULT_MISS) ] = 0x4c5, | |
505 | }, | |
506 | [ C(OP_WRITE) ] = { | |
507 | [ C(RESULT_ACCESS) ] = -1, | |
508 | [ C(RESULT_MISS) ] = -1, | |
509 | }, | |
510 | [ C(OP_PREFETCH) ] = { | |
511 | [ C(RESULT_ACCESS) ] = -1, | |
512 | [ C(RESULT_MISS) ] = -1, | |
513 | }, | |
514 | }, | |
515 | [ C(NODE) ] = { | |
516 | [ C(OP_READ) ] = { | |
517 | [ C(RESULT_ACCESS) ] = 0x12a, | |
518 | [ C(RESULT_MISS) ] = 0x12a, | |
519 | }, | |
520 | }, | |
521 | }; | |
522 | ||
523 | static __initconst const u64 spr_hw_cache_extra_regs | |
524 | [PERF_COUNT_HW_CACHE_MAX] | |
525 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
526 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
527 | { | |
528 | [ C(LL ) ] = { | |
529 | [ C(OP_READ) ] = { | |
530 | [ C(RESULT_ACCESS) ] = 0x10001, | |
531 | [ C(RESULT_MISS) ] = 0x3fbfc00001, | |
532 | }, | |
533 | [ C(OP_WRITE) ] = { | |
534 | [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, | |
535 | [ C(RESULT_MISS) ] = 0x3f3fc00002, | |
536 | }, | |
537 | }, | |
538 | [ C(NODE) ] = { | |
539 | [ C(OP_READ) ] = { | |
540 | [ C(RESULT_ACCESS) ] = 0x10c000001, | |
541 | [ C(RESULT_MISS) ] = 0x3fb3000001, | |
542 | }, | |
543 | }, | |
544 | }; | |
545 | ||
9a92e16f AK |
546 | /* |
547 | * Notes on the events: | |
548 | * - data reads do not include code reads (comparable to earlier tables) | |
549 | * - data counts include speculative execution (except L1 write, dtlb, bpu) | |
550 | * - remote node access includes remote memory, remote cache, remote mmio. | |
551 | * - prefetches are not included in the counts. | |
552 | * - icache miss does not include decoded icache | |
553 | */ | |
554 | ||
555 | #define SKL_DEMAND_DATA_RD BIT_ULL(0) | |
556 | #define SKL_DEMAND_RFO BIT_ULL(1) | |
557 | #define SKL_ANY_RESPONSE BIT_ULL(16) | |
558 | #define SKL_SUPPLIER_NONE BIT_ULL(17) | |
559 | #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) | |
560 | #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) | |
561 | #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) | |
562 | #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) | |
563 | #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ | |
564 | SKL_L3_MISS_REMOTE_HOP0_DRAM| \ | |
565 | SKL_L3_MISS_REMOTE_HOP1_DRAM| \ | |
566 | SKL_L3_MISS_REMOTE_HOP2P_DRAM) | |
567 | #define SKL_SPL_HIT BIT_ULL(30) | |
568 | #define SKL_SNOOP_NONE BIT_ULL(31) | |
569 | #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) | |
570 | #define SKL_SNOOP_MISS BIT_ULL(33) | |
571 | #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) | |
572 | #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) | |
573 | #define SKL_SNOOP_HITM BIT_ULL(36) | |
574 | #define SKL_SNOOP_NON_DRAM BIT_ULL(37) | |
575 | #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ | |
576 | SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ | |
577 | SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ | |
578 | SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) | |
579 | #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD | |
580 | #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ | |
581 | SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ | |
582 | SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ | |
583 | SKL_SNOOP_HITM|SKL_SPL_HIT) | |
584 | #define SKL_DEMAND_WRITE SKL_DEMAND_RFO | |
585 | #define SKL_LLC_ACCESS SKL_ANY_RESPONSE | |
586 | #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ | |
587 | SKL_L3_MISS_REMOTE_HOP1_DRAM| \ | |
588 | SKL_L3_MISS_REMOTE_HOP2P_DRAM) | |
589 | ||
590 | static __initconst const u64 skl_hw_cache_event_ids | |
591 | [PERF_COUNT_HW_CACHE_MAX] | |
592 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
593 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
594 | { | |
595 | [ C(L1D ) ] = { | |
596 | [ C(OP_READ) ] = { | |
597 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ | |
598 | [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ | |
599 | }, | |
600 | [ C(OP_WRITE) ] = { | |
601 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ | |
602 | [ C(RESULT_MISS) ] = 0x0, | |
603 | }, | |
604 | [ C(OP_PREFETCH) ] = { | |
605 | [ C(RESULT_ACCESS) ] = 0x0, | |
606 | [ C(RESULT_MISS) ] = 0x0, | |
607 | }, | |
608 | }, | |
609 | [ C(L1I ) ] = { | |
610 | [ C(OP_READ) ] = { | |
611 | [ C(RESULT_ACCESS) ] = 0x0, | |
612 | [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ | |
613 | }, | |
614 | [ C(OP_WRITE) ] = { | |
615 | [ C(RESULT_ACCESS) ] = -1, | |
616 | [ C(RESULT_MISS) ] = -1, | |
617 | }, | |
618 | [ C(OP_PREFETCH) ] = { | |
619 | [ C(RESULT_ACCESS) ] = 0x0, | |
620 | [ C(RESULT_MISS) ] = 0x0, | |
621 | }, | |
622 | }, | |
623 | [ C(LL ) ] = { | |
624 | [ C(OP_READ) ] = { | |
625 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
626 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
627 | }, | |
628 | [ C(OP_WRITE) ] = { | |
629 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
630 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
631 | }, | |
632 | [ C(OP_PREFETCH) ] = { | |
633 | [ C(RESULT_ACCESS) ] = 0x0, | |
634 | [ C(RESULT_MISS) ] = 0x0, | |
635 | }, | |
636 | }, | |
637 | [ C(DTLB) ] = { | |
638 | [ C(OP_READ) ] = { | |
639 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ | |
fb3a5055 | 640 | [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ |
9a92e16f AK |
641 | }, |
642 | [ C(OP_WRITE) ] = { | |
643 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ | |
fb3a5055 | 644 | [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ |
9a92e16f AK |
645 | }, |
646 | [ C(OP_PREFETCH) ] = { | |
647 | [ C(RESULT_ACCESS) ] = 0x0, | |
648 | [ C(RESULT_MISS) ] = 0x0, | |
649 | }, | |
650 | }, | |
651 | [ C(ITLB) ] = { | |
652 | [ C(OP_READ) ] = { | |
653 | [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ | |
654 | [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ | |
655 | }, | |
656 | [ C(OP_WRITE) ] = { | |
657 | [ C(RESULT_ACCESS) ] = -1, | |
658 | [ C(RESULT_MISS) ] = -1, | |
659 | }, | |
660 | [ C(OP_PREFETCH) ] = { | |
661 | [ C(RESULT_ACCESS) ] = -1, | |
662 | [ C(RESULT_MISS) ] = -1, | |
663 | }, | |
664 | }, | |
665 | [ C(BPU ) ] = { | |
666 | [ C(OP_READ) ] = { | |
667 | [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
668 | [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
669 | }, | |
670 | [ C(OP_WRITE) ] = { | |
671 | [ C(RESULT_ACCESS) ] = -1, | |
672 | [ C(RESULT_MISS) ] = -1, | |
673 | }, | |
674 | [ C(OP_PREFETCH) ] = { | |
675 | [ C(RESULT_ACCESS) ] = -1, | |
676 | [ C(RESULT_MISS) ] = -1, | |
677 | }, | |
678 | }, | |
679 | [ C(NODE) ] = { | |
680 | [ C(OP_READ) ] = { | |
681 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
682 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
683 | }, | |
684 | [ C(OP_WRITE) ] = { | |
685 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
686 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
687 | }, | |
688 | [ C(OP_PREFETCH) ] = { | |
689 | [ C(RESULT_ACCESS) ] = 0x0, | |
690 | [ C(RESULT_MISS) ] = 0x0, | |
691 | }, | |
692 | }, | |
693 | }; | |
694 | ||
695 | static __initconst const u64 skl_hw_cache_extra_regs | |
696 | [PERF_COUNT_HW_CACHE_MAX] | |
697 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
698 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
699 | { | |
700 | [ C(LL ) ] = { | |
701 | [ C(OP_READ) ] = { | |
702 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| | |
703 | SKL_LLC_ACCESS|SKL_ANY_SNOOP, | |
704 | [ C(RESULT_MISS) ] = SKL_DEMAND_READ| | |
705 | SKL_L3_MISS|SKL_ANY_SNOOP| | |
706 | SKL_SUPPLIER_NONE, | |
707 | }, | |
708 | [ C(OP_WRITE) ] = { | |
709 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| | |
710 | SKL_LLC_ACCESS|SKL_ANY_SNOOP, | |
711 | [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| | |
712 | SKL_L3_MISS|SKL_ANY_SNOOP| | |
713 | SKL_SUPPLIER_NONE, | |
714 | }, | |
715 | [ C(OP_PREFETCH) ] = { | |
716 | [ C(RESULT_ACCESS) ] = 0x0, | |
717 | [ C(RESULT_MISS) ] = 0x0, | |
718 | }, | |
719 | }, | |
720 | [ C(NODE) ] = { | |
721 | [ C(OP_READ) ] = { | |
722 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| | |
723 | SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, | |
724 | [ C(RESULT_MISS) ] = SKL_DEMAND_READ| | |
725 | SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, | |
726 | }, | |
727 | [ C(OP_WRITE) ] = { | |
728 | [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| | |
729 | SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, | |
730 | [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| | |
731 | SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, | |
732 | }, | |
733 | [ C(OP_PREFETCH) ] = { | |
734 | [ C(RESULT_ACCESS) ] = 0x0, | |
735 | [ C(RESULT_MISS) ] = 0x0, | |
736 | }, | |
737 | }, | |
738 | }; | |
739 | ||
74e6543f YZ |
740 | #define SNB_DMND_DATA_RD (1ULL << 0) |
741 | #define SNB_DMND_RFO (1ULL << 1) | |
742 | #define SNB_DMND_IFETCH (1ULL << 2) | |
743 | #define SNB_DMND_WB (1ULL << 3) | |
744 | #define SNB_PF_DATA_RD (1ULL << 4) | |
745 | #define SNB_PF_RFO (1ULL << 5) | |
746 | #define SNB_PF_IFETCH (1ULL << 6) | |
747 | #define SNB_LLC_DATA_RD (1ULL << 7) | |
748 | #define SNB_LLC_RFO (1ULL << 8) | |
749 | #define SNB_LLC_IFETCH (1ULL << 9) | |
750 | #define SNB_BUS_LOCKS (1ULL << 10) | |
751 | #define SNB_STRM_ST (1ULL << 11) | |
752 | #define SNB_OTHER (1ULL << 15) | |
753 | #define SNB_RESP_ANY (1ULL << 16) | |
754 | #define SNB_NO_SUPP (1ULL << 17) | |
755 | #define SNB_LLC_HITM (1ULL << 18) | |
756 | #define SNB_LLC_HITE (1ULL << 19) | |
757 | #define SNB_LLC_HITS (1ULL << 20) | |
758 | #define SNB_LLC_HITF (1ULL << 21) | |
759 | #define SNB_LOCAL (1ULL << 22) | |
760 | #define SNB_REMOTE (0xffULL << 23) | |
761 | #define SNB_SNP_NONE (1ULL << 31) | |
762 | #define SNB_SNP_NOT_NEEDED (1ULL << 32) | |
763 | #define SNB_SNP_MISS (1ULL << 33) | |
764 | #define SNB_NO_FWD (1ULL << 34) | |
765 | #define SNB_SNP_FWD (1ULL << 35) | |
766 | #define SNB_HITM (1ULL << 36) | |
767 | #define SNB_NON_DRAM (1ULL << 37) | |
768 | ||
769 | #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) | |
770 | #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) | |
771 | #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) | |
772 | ||
773 | #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ | |
774 | SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ | |
775 | SNB_HITM) | |
776 | ||
777 | #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) | |
778 | #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) | |
779 | ||
780 | #define SNB_L3_ACCESS SNB_RESP_ANY | |
781 | #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) | |
782 | ||
783 | static __initconst const u64 snb_hw_cache_extra_regs | |
784 | [PERF_COUNT_HW_CACHE_MAX] | |
785 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
786 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
787 | { | |
788 | [ C(LL ) ] = { | |
789 | [ C(OP_READ) ] = { | |
790 | [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, | |
791 | [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, | |
792 | }, | |
793 | [ C(OP_WRITE) ] = { | |
794 | [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, | |
795 | [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, | |
796 | }, | |
797 | [ C(OP_PREFETCH) ] = { | |
798 | [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, | |
799 | [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, | |
800 | }, | |
801 | }, | |
802 | [ C(NODE) ] = { | |
803 | [ C(OP_READ) ] = { | |
804 | [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, | |
805 | [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, | |
806 | }, | |
807 | [ C(OP_WRITE) ] = { | |
808 | [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, | |
809 | [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, | |
810 | }, | |
811 | [ C(OP_PREFETCH) ] = { | |
812 | [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, | |
813 | [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, | |
814 | }, | |
815 | }, | |
816 | }; | |
817 | ||
b06b3d49 LM |
818 | static __initconst const u64 snb_hw_cache_event_ids |
819 | [PERF_COUNT_HW_CACHE_MAX] | |
820 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
821 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
822 | { | |
823 | [ C(L1D) ] = { | |
824 | [ C(OP_READ) ] = { | |
825 | [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ | |
826 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ | |
827 | }, | |
828 | [ C(OP_WRITE) ] = { | |
829 | [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ | |
830 | [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ | |
831 | }, | |
832 | [ C(OP_PREFETCH) ] = { | |
833 | [ C(RESULT_ACCESS) ] = 0x0, | |
834 | [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ | |
835 | }, | |
836 | }, | |
837 | [ C(L1I ) ] = { | |
838 | [ C(OP_READ) ] = { | |
839 | [ C(RESULT_ACCESS) ] = 0x0, | |
840 | [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ | |
841 | }, | |
842 | [ C(OP_WRITE) ] = { | |
843 | [ C(RESULT_ACCESS) ] = -1, | |
844 | [ C(RESULT_MISS) ] = -1, | |
845 | }, | |
846 | [ C(OP_PREFETCH) ] = { | |
847 | [ C(RESULT_ACCESS) ] = 0x0, | |
848 | [ C(RESULT_MISS) ] = 0x0, | |
849 | }, | |
850 | }, | |
851 | [ C(LL ) ] = { | |
b06b3d49 | 852 | [ C(OP_READ) ] = { |
63b6a675 | 853 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
b06b3d49 | 854 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
855 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
856 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
857 | }, |
858 | [ C(OP_WRITE) ] = { | |
63b6a675 | 859 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
b06b3d49 | 860 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
861 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ |
862 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
863 | }, |
864 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 865 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
b06b3d49 | 866 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
867 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
868 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
869 | }, |
870 | }, | |
871 | [ C(DTLB) ] = { | |
872 | [ C(OP_READ) ] = { | |
873 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ | |
874 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ | |
875 | }, | |
876 | [ C(OP_WRITE) ] = { | |
877 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ | |
878 | [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ | |
879 | }, | |
880 | [ C(OP_PREFETCH) ] = { | |
881 | [ C(RESULT_ACCESS) ] = 0x0, | |
882 | [ C(RESULT_MISS) ] = 0x0, | |
883 | }, | |
884 | }, | |
885 | [ C(ITLB) ] = { | |
886 | [ C(OP_READ) ] = { | |
887 | [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ | |
888 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ | |
889 | }, | |
890 | [ C(OP_WRITE) ] = { | |
891 | [ C(RESULT_ACCESS) ] = -1, | |
892 | [ C(RESULT_MISS) ] = -1, | |
893 | }, | |
894 | [ C(OP_PREFETCH) ] = { | |
895 | [ C(RESULT_ACCESS) ] = -1, | |
896 | [ C(RESULT_MISS) ] = -1, | |
897 | }, | |
898 | }, | |
899 | [ C(BPU ) ] = { | |
900 | [ C(OP_READ) ] = { | |
901 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
902 | [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
903 | }, | |
904 | [ C(OP_WRITE) ] = { | |
905 | [ C(RESULT_ACCESS) ] = -1, | |
906 | [ C(RESULT_MISS) ] = -1, | |
907 | }, | |
908 | [ C(OP_PREFETCH) ] = { | |
909 | [ C(RESULT_ACCESS) ] = -1, | |
910 | [ C(RESULT_MISS) ] = -1, | |
911 | }, | |
912 | }, | |
89d6c0b5 PZ |
913 | [ C(NODE) ] = { |
914 | [ C(OP_READ) ] = { | |
74e6543f YZ |
915 | [ C(RESULT_ACCESS) ] = 0x01b7, |
916 | [ C(RESULT_MISS) ] = 0x01b7, | |
89d6c0b5 PZ |
917 | }, |
918 | [ C(OP_WRITE) ] = { | |
74e6543f YZ |
919 | [ C(RESULT_ACCESS) ] = 0x01b7, |
920 | [ C(RESULT_MISS) ] = 0x01b7, | |
89d6c0b5 PZ |
921 | }, |
922 | [ C(OP_PREFETCH) ] = { | |
74e6543f YZ |
923 | [ C(RESULT_ACCESS) ] = 0x01b7, |
924 | [ C(RESULT_MISS) ] = 0x01b7, | |
89d6c0b5 PZ |
925 | }, |
926 | }, | |
927 | ||
b06b3d49 LM |
928 | }; |
929 | ||
0f1b5ca2 AK |
930 | /* |
931 | * Notes on the events: | |
932 | * - data reads do not include code reads (comparable to earlier tables) | |
933 | * - data counts include speculative execution (except L1 write, dtlb, bpu) | |
934 | * - remote node access includes remote memory, remote cache, remote mmio. | |
935 | * - prefetches are not included in the counts because they are not | |
936 | * reliably counted. | |
937 | */ | |
938 | ||
939 | #define HSW_DEMAND_DATA_RD BIT_ULL(0) | |
940 | #define HSW_DEMAND_RFO BIT_ULL(1) | |
941 | #define HSW_ANY_RESPONSE BIT_ULL(16) | |
942 | #define HSW_SUPPLIER_NONE BIT_ULL(17) | |
943 | #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) | |
944 | #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) | |
945 | #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) | |
946 | #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) | |
947 | #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ | |
948 | HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ | |
949 | HSW_L3_MISS_REMOTE_HOP2P) | |
950 | #define HSW_SNOOP_NONE BIT_ULL(31) | |
951 | #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) | |
952 | #define HSW_SNOOP_MISS BIT_ULL(33) | |
953 | #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) | |
954 | #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) | |
955 | #define HSW_SNOOP_HITM BIT_ULL(36) | |
956 | #define HSW_SNOOP_NON_DRAM BIT_ULL(37) | |
957 | #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ | |
958 | HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ | |
959 | HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ | |
960 | HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) | |
961 | #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) | |
962 | #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD | |
963 | #define HSW_DEMAND_WRITE HSW_DEMAND_RFO | |
964 | #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ | |
965 | HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) | |
966 | #define HSW_LLC_ACCESS HSW_ANY_RESPONSE | |
967 | ||
91f1b705 AK |
968 | #define BDW_L3_MISS_LOCAL BIT(26) |
969 | #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ | |
970 | HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ | |
971 | HSW_L3_MISS_REMOTE_HOP2P) | |
972 | ||
973 | ||
0f1b5ca2 AK |
974 | static __initconst const u64 hsw_hw_cache_event_ids |
975 | [PERF_COUNT_HW_CACHE_MAX] | |
976 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
977 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
978 | { | |
979 | [ C(L1D ) ] = { | |
980 | [ C(OP_READ) ] = { | |
981 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
982 | [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ | |
983 | }, | |
984 | [ C(OP_WRITE) ] = { | |
985 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
986 | [ C(RESULT_MISS) ] = 0x0, | |
987 | }, | |
988 | [ C(OP_PREFETCH) ] = { | |
989 | [ C(RESULT_ACCESS) ] = 0x0, | |
990 | [ C(RESULT_MISS) ] = 0x0, | |
991 | }, | |
992 | }, | |
993 | [ C(L1I ) ] = { | |
994 | [ C(OP_READ) ] = { | |
995 | [ C(RESULT_ACCESS) ] = 0x0, | |
996 | [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ | |
997 | }, | |
998 | [ C(OP_WRITE) ] = { | |
999 | [ C(RESULT_ACCESS) ] = -1, | |
1000 | [ C(RESULT_MISS) ] = -1, | |
1001 | }, | |
1002 | [ C(OP_PREFETCH) ] = { | |
1003 | [ C(RESULT_ACCESS) ] = 0x0, | |
1004 | [ C(RESULT_MISS) ] = 0x0, | |
1005 | }, | |
1006 | }, | |
1007 | [ C(LL ) ] = { | |
1008 | [ C(OP_READ) ] = { | |
1009 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1010 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1011 | }, | |
1012 | [ C(OP_WRITE) ] = { | |
1013 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1014 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1015 | }, | |
1016 | [ C(OP_PREFETCH) ] = { | |
1017 | [ C(RESULT_ACCESS) ] = 0x0, | |
1018 | [ C(RESULT_MISS) ] = 0x0, | |
1019 | }, | |
1020 | }, | |
1021 | [ C(DTLB) ] = { | |
1022 | [ C(OP_READ) ] = { | |
1023 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1024 | [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ | |
1025 | }, | |
1026 | [ C(OP_WRITE) ] = { | |
1027 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1028 | [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ | |
1029 | }, | |
1030 | [ C(OP_PREFETCH) ] = { | |
1031 | [ C(RESULT_ACCESS) ] = 0x0, | |
1032 | [ C(RESULT_MISS) ] = 0x0, | |
1033 | }, | |
1034 | }, | |
1035 | [ C(ITLB) ] = { | |
1036 | [ C(OP_READ) ] = { | |
1037 | [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ | |
1038 | [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ | |
1039 | }, | |
1040 | [ C(OP_WRITE) ] = { | |
1041 | [ C(RESULT_ACCESS) ] = -1, | |
1042 | [ C(RESULT_MISS) ] = -1, | |
1043 | }, | |
1044 | [ C(OP_PREFETCH) ] = { | |
1045 | [ C(RESULT_ACCESS) ] = -1, | |
1046 | [ C(RESULT_MISS) ] = -1, | |
1047 | }, | |
1048 | }, | |
1049 | [ C(BPU ) ] = { | |
1050 | [ C(OP_READ) ] = { | |
1051 | [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1052 | [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
1053 | }, | |
1054 | [ C(OP_WRITE) ] = { | |
1055 | [ C(RESULT_ACCESS) ] = -1, | |
1056 | [ C(RESULT_MISS) ] = -1, | |
1057 | }, | |
1058 | [ C(OP_PREFETCH) ] = { | |
1059 | [ C(RESULT_ACCESS) ] = -1, | |
1060 | [ C(RESULT_MISS) ] = -1, | |
1061 | }, | |
1062 | }, | |
1063 | [ C(NODE) ] = { | |
1064 | [ C(OP_READ) ] = { | |
1065 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1066 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1067 | }, | |
1068 | [ C(OP_WRITE) ] = { | |
1069 | [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1070 | [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1071 | }, | |
1072 | [ C(OP_PREFETCH) ] = { | |
1073 | [ C(RESULT_ACCESS) ] = 0x0, | |
1074 | [ C(RESULT_MISS) ] = 0x0, | |
1075 | }, | |
1076 | }, | |
1077 | }; | |
1078 | ||
1079 | static __initconst const u64 hsw_hw_cache_extra_regs | |
1080 | [PERF_COUNT_HW_CACHE_MAX] | |
1081 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1082 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1083 | { | |
1084 | [ C(LL ) ] = { | |
1085 | [ C(OP_READ) ] = { | |
1086 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| | |
1087 | HSW_LLC_ACCESS, | |
1088 | [ C(RESULT_MISS) ] = HSW_DEMAND_READ| | |
1089 | HSW_L3_MISS|HSW_ANY_SNOOP, | |
1090 | }, | |
1091 | [ C(OP_WRITE) ] = { | |
1092 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| | |
1093 | HSW_LLC_ACCESS, | |
1094 | [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| | |
1095 | HSW_L3_MISS|HSW_ANY_SNOOP, | |
1096 | }, | |
1097 | [ C(OP_PREFETCH) ] = { | |
1098 | [ C(RESULT_ACCESS) ] = 0x0, | |
1099 | [ C(RESULT_MISS) ] = 0x0, | |
1100 | }, | |
1101 | }, | |
1102 | [ C(NODE) ] = { | |
1103 | [ C(OP_READ) ] = { | |
1104 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| | |
1105 | HSW_L3_MISS_LOCAL_DRAM| | |
1106 | HSW_SNOOP_DRAM, | |
1107 | [ C(RESULT_MISS) ] = HSW_DEMAND_READ| | |
1108 | HSW_L3_MISS_REMOTE| | |
1109 | HSW_SNOOP_DRAM, | |
1110 | }, | |
1111 | [ C(OP_WRITE) ] = { | |
1112 | [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| | |
1113 | HSW_L3_MISS_LOCAL_DRAM| | |
1114 | HSW_SNOOP_DRAM, | |
1115 | [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| | |
1116 | HSW_L3_MISS_REMOTE| | |
1117 | HSW_SNOOP_DRAM, | |
1118 | }, | |
1119 | [ C(OP_PREFETCH) ] = { | |
1120 | [ C(RESULT_ACCESS) ] = 0x0, | |
1121 | [ C(RESULT_MISS) ] = 0x0, | |
1122 | }, | |
1123 | }, | |
1124 | }; | |
1125 | ||
caaa8be3 | 1126 | static __initconst const u64 westmere_hw_cache_event_ids |
f22f54f4 PZ |
1127 | [PERF_COUNT_HW_CACHE_MAX] |
1128 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1129 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1130 | { | |
1131 | [ C(L1D) ] = { | |
1132 | [ C(OP_READ) ] = { | |
1133 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
1134 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
1135 | }, | |
1136 | [ C(OP_WRITE) ] = { | |
1137 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
1138 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
1139 | }, | |
1140 | [ C(OP_PREFETCH) ] = { | |
1141 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
1142 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
1143 | }, | |
1144 | }, | |
1145 | [ C(L1I ) ] = { | |
1146 | [ C(OP_READ) ] = { | |
1147 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
1148 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
1149 | }, | |
1150 | [ C(OP_WRITE) ] = { | |
1151 | [ C(RESULT_ACCESS) ] = -1, | |
1152 | [ C(RESULT_MISS) ] = -1, | |
1153 | }, | |
1154 | [ C(OP_PREFETCH) ] = { | |
1155 | [ C(RESULT_ACCESS) ] = 0x0, | |
1156 | [ C(RESULT_MISS) ] = 0x0, | |
1157 | }, | |
1158 | }, | |
1159 | [ C(LL ) ] = { | |
1160 | [ C(OP_READ) ] = { | |
63b6a675 | 1161 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
e994d7d2 | 1162 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
1163 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
1164 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 1165 | }, |
e994d7d2 AK |
1166 | /* |
1167 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
1168 | * on RFO. | |
1169 | */ | |
f22f54f4 | 1170 | [ C(OP_WRITE) ] = { |
63b6a675 PZ |
1171 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
1172 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1173 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
e994d7d2 | 1174 | [ C(RESULT_MISS) ] = 0x01b7, |
f22f54f4 PZ |
1175 | }, |
1176 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 1177 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
e994d7d2 | 1178 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
1179 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
1180 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
1181 | }, |
1182 | }, | |
1183 | [ C(DTLB) ] = { | |
1184 | [ C(OP_READ) ] = { | |
1185 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
1186 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
1187 | }, | |
1188 | [ C(OP_WRITE) ] = { | |
1189 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
1190 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
1191 | }, | |
1192 | [ C(OP_PREFETCH) ] = { | |
1193 | [ C(RESULT_ACCESS) ] = 0x0, | |
1194 | [ C(RESULT_MISS) ] = 0x0, | |
1195 | }, | |
1196 | }, | |
1197 | [ C(ITLB) ] = { | |
1198 | [ C(OP_READ) ] = { | |
1199 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
1200 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ | |
1201 | }, | |
1202 | [ C(OP_WRITE) ] = { | |
1203 | [ C(RESULT_ACCESS) ] = -1, | |
1204 | [ C(RESULT_MISS) ] = -1, | |
1205 | }, | |
1206 | [ C(OP_PREFETCH) ] = { | |
1207 | [ C(RESULT_ACCESS) ] = -1, | |
1208 | [ C(RESULT_MISS) ] = -1, | |
1209 | }, | |
1210 | }, | |
1211 | [ C(BPU ) ] = { | |
1212 | [ C(OP_READ) ] = { | |
1213 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1214 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
1215 | }, | |
1216 | [ C(OP_WRITE) ] = { | |
1217 | [ C(RESULT_ACCESS) ] = -1, | |
1218 | [ C(RESULT_MISS) ] = -1, | |
1219 | }, | |
1220 | [ C(OP_PREFETCH) ] = { | |
1221 | [ C(RESULT_ACCESS) ] = -1, | |
1222 | [ C(RESULT_MISS) ] = -1, | |
1223 | }, | |
1224 | }, | |
89d6c0b5 PZ |
1225 | [ C(NODE) ] = { |
1226 | [ C(OP_READ) ] = { | |
1227 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1228 | [ C(RESULT_MISS) ] = 0x01b7, | |
1229 | }, | |
1230 | [ C(OP_WRITE) ] = { | |
1231 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1232 | [ C(RESULT_MISS) ] = 0x01b7, | |
1233 | }, | |
1234 | [ C(OP_PREFETCH) ] = { | |
1235 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1236 | [ C(RESULT_MISS) ] = 0x01b7, | |
1237 | }, | |
1238 | }, | |
f22f54f4 PZ |
1239 | }; |
1240 | ||
e994d7d2 | 1241 | /* |
63b6a675 PZ |
1242 | * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; |
1243 | * See IA32 SDM Vol 3B 30.6.1.3 | |
e994d7d2 AK |
1244 | */ |
1245 | ||
63b6a675 PZ |
1246 | #define NHM_DMND_DATA_RD (1 << 0) |
1247 | #define NHM_DMND_RFO (1 << 1) | |
1248 | #define NHM_DMND_IFETCH (1 << 2) | |
1249 | #define NHM_DMND_WB (1 << 3) | |
1250 | #define NHM_PF_DATA_RD (1 << 4) | |
1251 | #define NHM_PF_DATA_RFO (1 << 5) | |
1252 | #define NHM_PF_IFETCH (1 << 6) | |
1253 | #define NHM_OFFCORE_OTHER (1 << 7) | |
1254 | #define NHM_UNCORE_HIT (1 << 8) | |
1255 | #define NHM_OTHER_CORE_HIT_SNP (1 << 9) | |
1256 | #define NHM_OTHER_CORE_HITM (1 << 10) | |
1257 | /* reserved */ | |
1258 | #define NHM_REMOTE_CACHE_FWD (1 << 12) | |
1259 | #define NHM_REMOTE_DRAM (1 << 13) | |
1260 | #define NHM_LOCAL_DRAM (1 << 14) | |
1261 | #define NHM_NON_DRAM (1 << 15) | |
1262 | ||
87e24f4b PZ |
1263 | #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) |
1264 | #define NHM_REMOTE (NHM_REMOTE_DRAM) | |
63b6a675 PZ |
1265 | |
1266 | #define NHM_DMND_READ (NHM_DMND_DATA_RD) | |
1267 | #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) | |
1268 | #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) | |
1269 | ||
1270 | #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) | |
87e24f4b | 1271 | #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) |
63b6a675 | 1272 | #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) |
e994d7d2 AK |
1273 | |
1274 | static __initconst const u64 nehalem_hw_cache_extra_regs | |
1275 | [PERF_COUNT_HW_CACHE_MAX] | |
1276 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1277 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1278 | { | |
1279 | [ C(LL ) ] = { | |
1280 | [ C(OP_READ) ] = { | |
63b6a675 PZ |
1281 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, |
1282 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, | |
e994d7d2 AK |
1283 | }, |
1284 | [ C(OP_WRITE) ] = { | |
63b6a675 PZ |
1285 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, |
1286 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, | |
e994d7d2 AK |
1287 | }, |
1288 | [ C(OP_PREFETCH) ] = { | |
63b6a675 PZ |
1289 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, |
1290 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, | |
e994d7d2 | 1291 | }, |
89d6c0b5 PZ |
1292 | }, |
1293 | [ C(NODE) ] = { | |
1294 | [ C(OP_READ) ] = { | |
87e24f4b PZ |
1295 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, |
1296 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, | |
89d6c0b5 PZ |
1297 | }, |
1298 | [ C(OP_WRITE) ] = { | |
87e24f4b PZ |
1299 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, |
1300 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, | |
89d6c0b5 PZ |
1301 | }, |
1302 | [ C(OP_PREFETCH) ] = { | |
87e24f4b PZ |
1303 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, |
1304 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, | |
89d6c0b5 PZ |
1305 | }, |
1306 | }, | |
e994d7d2 AK |
1307 | }; |
1308 | ||
caaa8be3 | 1309 | static __initconst const u64 nehalem_hw_cache_event_ids |
f22f54f4 PZ |
1310 | [PERF_COUNT_HW_CACHE_MAX] |
1311 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1312 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1313 | { | |
1314 | [ C(L1D) ] = { | |
1315 | [ C(OP_READ) ] = { | |
f4929bd3 PZ |
1316 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ |
1317 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
f22f54f4 PZ |
1318 | }, |
1319 | [ C(OP_WRITE) ] = { | |
f4929bd3 PZ |
1320 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ |
1321 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
f22f54f4 PZ |
1322 | }, |
1323 | [ C(OP_PREFETCH) ] = { | |
1324 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
1325 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
1326 | }, | |
1327 | }, | |
1328 | [ C(L1I ) ] = { | |
1329 | [ C(OP_READ) ] = { | |
1330 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
1331 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
1332 | }, | |
1333 | [ C(OP_WRITE) ] = { | |
1334 | [ C(RESULT_ACCESS) ] = -1, | |
1335 | [ C(RESULT_MISS) ] = -1, | |
1336 | }, | |
1337 | [ C(OP_PREFETCH) ] = { | |
1338 | [ C(RESULT_ACCESS) ] = 0x0, | |
1339 | [ C(RESULT_MISS) ] = 0x0, | |
1340 | }, | |
1341 | }, | |
1342 | [ C(LL ) ] = { | |
1343 | [ C(OP_READ) ] = { | |
e994d7d2 AK |
1344 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
1345 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1346 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ | |
1347 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 1348 | }, |
e994d7d2 AK |
1349 | /* |
1350 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
1351 | * on RFO. | |
1352 | */ | |
f22f54f4 | 1353 | [ C(OP_WRITE) ] = { |
e994d7d2 AK |
1354 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
1355 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1356 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
1357 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
1358 | }, |
1359 | [ C(OP_PREFETCH) ] = { | |
e994d7d2 AK |
1360 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
1361 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1362 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ | |
1363 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
1364 | }, |
1365 | }, | |
1366 | [ C(DTLB) ] = { | |
1367 | [ C(OP_READ) ] = { | |
1368 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
1369 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
1370 | }, | |
1371 | [ C(OP_WRITE) ] = { | |
1372 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
1373 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
1374 | }, | |
1375 | [ C(OP_PREFETCH) ] = { | |
1376 | [ C(RESULT_ACCESS) ] = 0x0, | |
1377 | [ C(RESULT_MISS) ] = 0x0, | |
1378 | }, | |
1379 | }, | |
1380 | [ C(ITLB) ] = { | |
1381 | [ C(OP_READ) ] = { | |
1382 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
1383 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ | |
1384 | }, | |
1385 | [ C(OP_WRITE) ] = { | |
1386 | [ C(RESULT_ACCESS) ] = -1, | |
1387 | [ C(RESULT_MISS) ] = -1, | |
1388 | }, | |
1389 | [ C(OP_PREFETCH) ] = { | |
1390 | [ C(RESULT_ACCESS) ] = -1, | |
1391 | [ C(RESULT_MISS) ] = -1, | |
1392 | }, | |
1393 | }, | |
1394 | [ C(BPU ) ] = { | |
1395 | [ C(OP_READ) ] = { | |
1396 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1397 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
1398 | }, | |
1399 | [ C(OP_WRITE) ] = { | |
1400 | [ C(RESULT_ACCESS) ] = -1, | |
1401 | [ C(RESULT_MISS) ] = -1, | |
1402 | }, | |
1403 | [ C(OP_PREFETCH) ] = { | |
1404 | [ C(RESULT_ACCESS) ] = -1, | |
1405 | [ C(RESULT_MISS) ] = -1, | |
1406 | }, | |
1407 | }, | |
89d6c0b5 PZ |
1408 | [ C(NODE) ] = { |
1409 | [ C(OP_READ) ] = { | |
1410 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1411 | [ C(RESULT_MISS) ] = 0x01b7, | |
1412 | }, | |
1413 | [ C(OP_WRITE) ] = { | |
1414 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1415 | [ C(RESULT_MISS) ] = 0x01b7, | |
1416 | }, | |
1417 | [ C(OP_PREFETCH) ] = { | |
1418 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1419 | [ C(RESULT_MISS) ] = 0x01b7, | |
1420 | }, | |
1421 | }, | |
f22f54f4 PZ |
1422 | }; |
1423 | ||
caaa8be3 | 1424 | static __initconst const u64 core2_hw_cache_event_ids |
f22f54f4 PZ |
1425 | [PERF_COUNT_HW_CACHE_MAX] |
1426 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1427 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1428 | { | |
1429 | [ C(L1D) ] = { | |
1430 | [ C(OP_READ) ] = { | |
1431 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
1432 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
1433 | }, | |
1434 | [ C(OP_WRITE) ] = { | |
1435 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
1436 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
1437 | }, | |
1438 | [ C(OP_PREFETCH) ] = { | |
1439 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
1440 | [ C(RESULT_MISS) ] = 0, | |
1441 | }, | |
1442 | }, | |
1443 | [ C(L1I ) ] = { | |
1444 | [ C(OP_READ) ] = { | |
1445 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
1446 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
1447 | }, | |
1448 | [ C(OP_WRITE) ] = { | |
1449 | [ C(RESULT_ACCESS) ] = -1, | |
1450 | [ C(RESULT_MISS) ] = -1, | |
1451 | }, | |
1452 | [ C(OP_PREFETCH) ] = { | |
1453 | [ C(RESULT_ACCESS) ] = 0, | |
1454 | [ C(RESULT_MISS) ] = 0, | |
1455 | }, | |
1456 | }, | |
1457 | [ C(LL ) ] = { | |
1458 | [ C(OP_READ) ] = { | |
1459 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
1460 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
1461 | }, | |
1462 | [ C(OP_WRITE) ] = { | |
1463 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
1464 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
1465 | }, | |
1466 | [ C(OP_PREFETCH) ] = { | |
1467 | [ C(RESULT_ACCESS) ] = 0, | |
1468 | [ C(RESULT_MISS) ] = 0, | |
1469 | }, | |
1470 | }, | |
1471 | [ C(DTLB) ] = { | |
1472 | [ C(OP_READ) ] = { | |
1473 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
1474 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
1475 | }, | |
1476 | [ C(OP_WRITE) ] = { | |
1477 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
1478 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
1479 | }, | |
1480 | [ C(OP_PREFETCH) ] = { | |
1481 | [ C(RESULT_ACCESS) ] = 0, | |
1482 | [ C(RESULT_MISS) ] = 0, | |
1483 | }, | |
1484 | }, | |
1485 | [ C(ITLB) ] = { | |
1486 | [ C(OP_READ) ] = { | |
1487 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1488 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
1489 | }, | |
1490 | [ C(OP_WRITE) ] = { | |
1491 | [ C(RESULT_ACCESS) ] = -1, | |
1492 | [ C(RESULT_MISS) ] = -1, | |
1493 | }, | |
1494 | [ C(OP_PREFETCH) ] = { | |
1495 | [ C(RESULT_ACCESS) ] = -1, | |
1496 | [ C(RESULT_MISS) ] = -1, | |
1497 | }, | |
1498 | }, | |
1499 | [ C(BPU ) ] = { | |
1500 | [ C(OP_READ) ] = { | |
1501 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
1502 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
1503 | }, | |
1504 | [ C(OP_WRITE) ] = { | |
1505 | [ C(RESULT_ACCESS) ] = -1, | |
1506 | [ C(RESULT_MISS) ] = -1, | |
1507 | }, | |
1508 | [ C(OP_PREFETCH) ] = { | |
1509 | [ C(RESULT_ACCESS) ] = -1, | |
1510 | [ C(RESULT_MISS) ] = -1, | |
1511 | }, | |
1512 | }, | |
1513 | }; | |
1514 | ||
caaa8be3 | 1515 | static __initconst const u64 atom_hw_cache_event_ids |
f22f54f4 PZ |
1516 | [PERF_COUNT_HW_CACHE_MAX] |
1517 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1518 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1519 | { | |
1520 | [ C(L1D) ] = { | |
1521 | [ C(OP_READ) ] = { | |
1522 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
1523 | [ C(RESULT_MISS) ] = 0, | |
1524 | }, | |
1525 | [ C(OP_WRITE) ] = { | |
1526 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ | |
1527 | [ C(RESULT_MISS) ] = 0, | |
1528 | }, | |
1529 | [ C(OP_PREFETCH) ] = { | |
1530 | [ C(RESULT_ACCESS) ] = 0x0, | |
1531 | [ C(RESULT_MISS) ] = 0, | |
1532 | }, | |
1533 | }, | |
1534 | [ C(L1I ) ] = { | |
1535 | [ C(OP_READ) ] = { | |
1536 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
1537 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
1538 | }, | |
1539 | [ C(OP_WRITE) ] = { | |
1540 | [ C(RESULT_ACCESS) ] = -1, | |
1541 | [ C(RESULT_MISS) ] = -1, | |
1542 | }, | |
1543 | [ C(OP_PREFETCH) ] = { | |
1544 | [ C(RESULT_ACCESS) ] = 0, | |
1545 | [ C(RESULT_MISS) ] = 0, | |
1546 | }, | |
1547 | }, | |
1548 | [ C(LL ) ] = { | |
1549 | [ C(OP_READ) ] = { | |
1550 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
1551 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
1552 | }, | |
1553 | [ C(OP_WRITE) ] = { | |
1554 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
1555 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
1556 | }, | |
1557 | [ C(OP_PREFETCH) ] = { | |
1558 | [ C(RESULT_ACCESS) ] = 0, | |
1559 | [ C(RESULT_MISS) ] = 0, | |
1560 | }, | |
1561 | }, | |
1562 | [ C(DTLB) ] = { | |
1563 | [ C(OP_READ) ] = { | |
1564 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ | |
1565 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ | |
1566 | }, | |
1567 | [ C(OP_WRITE) ] = { | |
1568 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ | |
1569 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ | |
1570 | }, | |
1571 | [ C(OP_PREFETCH) ] = { | |
1572 | [ C(RESULT_ACCESS) ] = 0, | |
1573 | [ C(RESULT_MISS) ] = 0, | |
1574 | }, | |
1575 | }, | |
1576 | [ C(ITLB) ] = { | |
1577 | [ C(OP_READ) ] = { | |
1578 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1579 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
1580 | }, | |
1581 | [ C(OP_WRITE) ] = { | |
1582 | [ C(RESULT_ACCESS) ] = -1, | |
1583 | [ C(RESULT_MISS) ] = -1, | |
1584 | }, | |
1585 | [ C(OP_PREFETCH) ] = { | |
1586 | [ C(RESULT_ACCESS) ] = -1, | |
1587 | [ C(RESULT_MISS) ] = -1, | |
1588 | }, | |
1589 | }, | |
1590 | [ C(BPU ) ] = { | |
1591 | [ C(OP_READ) ] = { | |
1592 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
1593 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
1594 | }, | |
1595 | [ C(OP_WRITE) ] = { | |
1596 | [ C(RESULT_ACCESS) ] = -1, | |
1597 | [ C(RESULT_MISS) ] = -1, | |
1598 | }, | |
1599 | [ C(OP_PREFETCH) ] = { | |
1600 | [ C(RESULT_ACCESS) ] = -1, | |
1601 | [ C(RESULT_MISS) ] = -1, | |
1602 | }, | |
1603 | }, | |
1604 | }; | |
1605 | ||
eb12b8ec AK |
1606 | EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); |
1607 | EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); | |
1608 | /* no_alloc_cycles.not_delivered */ | |
1609 | EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, | |
1610 | "event=0xca,umask=0x50"); | |
1611 | EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); | |
1612 | /* uops_retired.all */ | |
1613 | EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, | |
1614 | "event=0xc2,umask=0x10"); | |
1615 | /* uops_retired.all */ | |
1616 | EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, | |
1617 | "event=0xc2,umask=0x10"); | |
1618 | ||
1619 | static struct attribute *slm_events_attrs[] = { | |
1620 | EVENT_PTR(td_total_slots_slm), | |
1621 | EVENT_PTR(td_total_slots_scale_slm), | |
1622 | EVENT_PTR(td_fetch_bubbles_slm), | |
1623 | EVENT_PTR(td_fetch_bubbles_scale_slm), | |
1624 | EVENT_PTR(td_slots_issued_slm), | |
1625 | EVENT_PTR(td_slots_retired_slm), | |
1626 | NULL | |
1627 | }; | |
1628 | ||
1fa64180 YZ |
1629 | static struct extra_reg intel_slm_extra_regs[] __read_mostly = |
1630 | { | |
1631 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ | |
06c939c1 | 1632 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), |
ae3f011f | 1633 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), |
1fa64180 YZ |
1634 | EVENT_EXTRA_END |
1635 | }; | |
1636 | ||
1637 | #define SLM_DMND_READ SNB_DMND_DATA_RD | |
1638 | #define SLM_DMND_WRITE SNB_DMND_RFO | |
1639 | #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) | |
1640 | ||
1641 | #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) | |
1642 | #define SLM_LLC_ACCESS SNB_RESP_ANY | |
1643 | #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) | |
1644 | ||
1645 | static __initconst const u64 slm_hw_cache_extra_regs | |
1646 | [PERF_COUNT_HW_CACHE_MAX] | |
1647 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1648 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1649 | { | |
1650 | [ C(LL ) ] = { | |
1651 | [ C(OP_READ) ] = { | |
1652 | [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, | |
6d374056 | 1653 | [ C(RESULT_MISS) ] = 0, |
1fa64180 YZ |
1654 | }, |
1655 | [ C(OP_WRITE) ] = { | |
1656 | [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, | |
1657 | [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, | |
1658 | }, | |
1659 | [ C(OP_PREFETCH) ] = { | |
1660 | [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, | |
1661 | [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, | |
1662 | }, | |
1663 | }, | |
1664 | }; | |
1665 | ||
1666 | static __initconst const u64 slm_hw_cache_event_ids | |
1667 | [PERF_COUNT_HW_CACHE_MAX] | |
1668 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1669 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
1670 | { | |
1671 | [ C(L1D) ] = { | |
1672 | [ C(OP_READ) ] = { | |
1673 | [ C(RESULT_ACCESS) ] = 0, | |
1674 | [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ | |
1675 | }, | |
1676 | [ C(OP_WRITE) ] = { | |
1677 | [ C(RESULT_ACCESS) ] = 0, | |
1678 | [ C(RESULT_MISS) ] = 0, | |
1679 | }, | |
1680 | [ C(OP_PREFETCH) ] = { | |
1681 | [ C(RESULT_ACCESS) ] = 0, | |
1682 | [ C(RESULT_MISS) ] = 0, | |
1683 | }, | |
1684 | }, | |
1685 | [ C(L1I ) ] = { | |
1686 | [ C(OP_READ) ] = { | |
1687 | [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ | |
1688 | [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ | |
1689 | }, | |
1690 | [ C(OP_WRITE) ] = { | |
1691 | [ C(RESULT_ACCESS) ] = -1, | |
1692 | [ C(RESULT_MISS) ] = -1, | |
1693 | }, | |
1694 | [ C(OP_PREFETCH) ] = { | |
1695 | [ C(RESULT_ACCESS) ] = 0, | |
1696 | [ C(RESULT_MISS) ] = 0, | |
1697 | }, | |
1698 | }, | |
1699 | [ C(LL ) ] = { | |
1700 | [ C(OP_READ) ] = { | |
1701 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ | |
1702 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
6d374056 | 1703 | [ C(RESULT_MISS) ] = 0, |
1fa64180 YZ |
1704 | }, |
1705 | [ C(OP_WRITE) ] = { | |
1706 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ | |
1707 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1708 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
1709 | [ C(RESULT_MISS) ] = 0x01b7, | |
1710 | }, | |
1711 | [ C(OP_PREFETCH) ] = { | |
1712 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ | |
1713 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
1714 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ | |
1715 | [ C(RESULT_MISS) ] = 0x01b7, | |
1716 | }, | |
1717 | }, | |
1718 | [ C(DTLB) ] = { | |
1719 | [ C(OP_READ) ] = { | |
1720 | [ C(RESULT_ACCESS) ] = 0, | |
1721 | [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ | |
1722 | }, | |
1723 | [ C(OP_WRITE) ] = { | |
1724 | [ C(RESULT_ACCESS) ] = 0, | |
1725 | [ C(RESULT_MISS) ] = 0, | |
1726 | }, | |
1727 | [ C(OP_PREFETCH) ] = { | |
1728 | [ C(RESULT_ACCESS) ] = 0, | |
1729 | [ C(RESULT_MISS) ] = 0, | |
1730 | }, | |
1731 | }, | |
1732 | [ C(ITLB) ] = { | |
1733 | [ C(OP_READ) ] = { | |
1734 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
6d374056 | 1735 | [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ |
1fa64180 YZ |
1736 | }, |
1737 | [ C(OP_WRITE) ] = { | |
1738 | [ C(RESULT_ACCESS) ] = -1, | |
1739 | [ C(RESULT_MISS) ] = -1, | |
1740 | }, | |
1741 | [ C(OP_PREFETCH) ] = { | |
1742 | [ C(RESULT_ACCESS) ] = -1, | |
1743 | [ C(RESULT_MISS) ] = -1, | |
1744 | }, | |
1745 | }, | |
1746 | [ C(BPU ) ] = { | |
1747 | [ C(OP_READ) ] = { | |
1748 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
1749 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
1750 | }, | |
1751 | [ C(OP_WRITE) ] = { | |
1752 | [ C(RESULT_ACCESS) ] = -1, | |
1753 | [ C(RESULT_MISS) ] = -1, | |
1754 | }, | |
1755 | [ C(OP_PREFETCH) ] = { | |
1756 | [ C(RESULT_ACCESS) ] = -1, | |
1757 | [ C(RESULT_MISS) ] = -1, | |
1758 | }, | |
1759 | }, | |
1760 | }; | |
1761 | ||
ed827adb KL |
1762 | EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); |
1763 | EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); | |
1764 | /* UOPS_NOT_DELIVERED.ANY */ | |
1765 | EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); | |
1766 | /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ | |
1767 | EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); | |
1768 | /* UOPS_RETIRED.ANY */ | |
1769 | EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); | |
1770 | /* UOPS_ISSUED.ANY */ | |
1771 | EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); | |
1772 | ||
1773 | static struct attribute *glm_events_attrs[] = { | |
1774 | EVENT_PTR(td_total_slots_glm), | |
1775 | EVENT_PTR(td_total_slots_scale_glm), | |
1776 | EVENT_PTR(td_fetch_bubbles_glm), | |
1777 | EVENT_PTR(td_recovery_bubbles_glm), | |
1778 | EVENT_PTR(td_slots_issued_glm), | |
1779 | EVENT_PTR(td_slots_retired_glm), | |
1780 | NULL | |
1781 | }; | |
1782 | ||
8b92c3a7 KL |
1783 | static struct extra_reg intel_glm_extra_regs[] __read_mostly = { |
1784 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ | |
1785 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), | |
1786 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), | |
1787 | EVENT_EXTRA_END | |
1788 | }; | |
1789 | ||
1790 | #define GLM_DEMAND_DATA_RD BIT_ULL(0) | |
1791 | #define GLM_DEMAND_RFO BIT_ULL(1) | |
1792 | #define GLM_ANY_RESPONSE BIT_ULL(16) | |
1793 | #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) | |
1794 | #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD | |
1795 | #define GLM_DEMAND_WRITE GLM_DEMAND_RFO | |
1796 | #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) | |
1797 | #define GLM_LLC_ACCESS GLM_ANY_RESPONSE | |
1798 | #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) | |
1799 | #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) | |
1800 | ||
1801 | static __initconst const u64 glm_hw_cache_event_ids | |
1802 | [PERF_COUNT_HW_CACHE_MAX] | |
1803 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1804 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1805 | [C(L1D)] = { | |
1806 | [C(OP_READ)] = { | |
1807 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1808 | [C(RESULT_MISS)] = 0x0, | |
1809 | }, | |
1810 | [C(OP_WRITE)] = { | |
1811 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1812 | [C(RESULT_MISS)] = 0x0, | |
1813 | }, | |
1814 | [C(OP_PREFETCH)] = { | |
1815 | [C(RESULT_ACCESS)] = 0x0, | |
1816 | [C(RESULT_MISS)] = 0x0, | |
1817 | }, | |
1818 | }, | |
1819 | [C(L1I)] = { | |
1820 | [C(OP_READ)] = { | |
1821 | [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ | |
1822 | [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ | |
1823 | }, | |
1824 | [C(OP_WRITE)] = { | |
1825 | [C(RESULT_ACCESS)] = -1, | |
1826 | [C(RESULT_MISS)] = -1, | |
1827 | }, | |
1828 | [C(OP_PREFETCH)] = { | |
1829 | [C(RESULT_ACCESS)] = 0x0, | |
1830 | [C(RESULT_MISS)] = 0x0, | |
1831 | }, | |
1832 | }, | |
1833 | [C(LL)] = { | |
1834 | [C(OP_READ)] = { | |
1835 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1836 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1837 | }, | |
1838 | [C(OP_WRITE)] = { | |
1839 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1840 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1841 | }, | |
1842 | [C(OP_PREFETCH)] = { | |
1843 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1844 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1845 | }, | |
1846 | }, | |
1847 | [C(DTLB)] = { | |
1848 | [C(OP_READ)] = { | |
1849 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1850 | [C(RESULT_MISS)] = 0x0, | |
1851 | }, | |
1852 | [C(OP_WRITE)] = { | |
1853 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1854 | [C(RESULT_MISS)] = 0x0, | |
1855 | }, | |
1856 | [C(OP_PREFETCH)] = { | |
1857 | [C(RESULT_ACCESS)] = 0x0, | |
1858 | [C(RESULT_MISS)] = 0x0, | |
1859 | }, | |
1860 | }, | |
1861 | [C(ITLB)] = { | |
1862 | [C(OP_READ)] = { | |
1863 | [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1864 | [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ | |
1865 | }, | |
1866 | [C(OP_WRITE)] = { | |
1867 | [C(RESULT_ACCESS)] = -1, | |
1868 | [C(RESULT_MISS)] = -1, | |
1869 | }, | |
1870 | [C(OP_PREFETCH)] = { | |
1871 | [C(RESULT_ACCESS)] = -1, | |
1872 | [C(RESULT_MISS)] = -1, | |
1873 | }, | |
1874 | }, | |
1875 | [C(BPU)] = { | |
1876 | [C(OP_READ)] = { | |
1877 | [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1878 | [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
1879 | }, | |
1880 | [C(OP_WRITE)] = { | |
1881 | [C(RESULT_ACCESS)] = -1, | |
1882 | [C(RESULT_MISS)] = -1, | |
1883 | }, | |
1884 | [C(OP_PREFETCH)] = { | |
1885 | [C(RESULT_ACCESS)] = -1, | |
1886 | [C(RESULT_MISS)] = -1, | |
1887 | }, | |
1888 | }, | |
1889 | }; | |
1890 | ||
1891 | static __initconst const u64 glm_hw_cache_extra_regs | |
1892 | [PERF_COUNT_HW_CACHE_MAX] | |
1893 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1894 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1895 | [C(LL)] = { | |
1896 | [C(OP_READ)] = { | |
1897 | [C(RESULT_ACCESS)] = GLM_DEMAND_READ| | |
1898 | GLM_LLC_ACCESS, | |
1899 | [C(RESULT_MISS)] = GLM_DEMAND_READ| | |
1900 | GLM_LLC_MISS, | |
1901 | }, | |
1902 | [C(OP_WRITE)] = { | |
1903 | [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| | |
1904 | GLM_LLC_ACCESS, | |
1905 | [C(RESULT_MISS)] = GLM_DEMAND_WRITE| | |
1906 | GLM_LLC_MISS, | |
1907 | }, | |
1908 | [C(OP_PREFETCH)] = { | |
1909 | [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| | |
1910 | GLM_LLC_ACCESS, | |
1911 | [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| | |
1912 | GLM_LLC_MISS, | |
1913 | }, | |
1914 | }, | |
1915 | }; | |
1916 | ||
dd0b06b5 KL |
1917 | static __initconst const u64 glp_hw_cache_event_ids |
1918 | [PERF_COUNT_HW_CACHE_MAX] | |
1919 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
1920 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
1921 | [C(L1D)] = { | |
1922 | [C(OP_READ)] = { | |
1923 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1924 | [C(RESULT_MISS)] = 0x0, | |
1925 | }, | |
1926 | [C(OP_WRITE)] = { | |
1927 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1928 | [C(RESULT_MISS)] = 0x0, | |
1929 | }, | |
1930 | [C(OP_PREFETCH)] = { | |
1931 | [C(RESULT_ACCESS)] = 0x0, | |
1932 | [C(RESULT_MISS)] = 0x0, | |
1933 | }, | |
1934 | }, | |
1935 | [C(L1I)] = { | |
1936 | [C(OP_READ)] = { | |
1937 | [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ | |
1938 | [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ | |
1939 | }, | |
1940 | [C(OP_WRITE)] = { | |
1941 | [C(RESULT_ACCESS)] = -1, | |
1942 | [C(RESULT_MISS)] = -1, | |
1943 | }, | |
1944 | [C(OP_PREFETCH)] = { | |
1945 | [C(RESULT_ACCESS)] = 0x0, | |
1946 | [C(RESULT_MISS)] = 0x0, | |
1947 | }, | |
1948 | }, | |
1949 | [C(LL)] = { | |
1950 | [C(OP_READ)] = { | |
1951 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1952 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1953 | }, | |
1954 | [C(OP_WRITE)] = { | |
1955 | [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1956 | [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ | |
1957 | }, | |
1958 | [C(OP_PREFETCH)] = { | |
1959 | [C(RESULT_ACCESS)] = 0x0, | |
1960 | [C(RESULT_MISS)] = 0x0, | |
1961 | }, | |
1962 | }, | |
1963 | [C(DTLB)] = { | |
1964 | [C(OP_READ)] = { | |
1965 | [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
1966 | [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ | |
1967 | }, | |
1968 | [C(OP_WRITE)] = { | |
1969 | [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ | |
1970 | [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ | |
1971 | }, | |
1972 | [C(OP_PREFETCH)] = { | |
1973 | [C(RESULT_ACCESS)] = 0x0, | |
1974 | [C(RESULT_MISS)] = 0x0, | |
1975 | }, | |
1976 | }, | |
1977 | [C(ITLB)] = { | |
1978 | [C(OP_READ)] = { | |
1979 | [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
1980 | [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ | |
1981 | }, | |
1982 | [C(OP_WRITE)] = { | |
1983 | [C(RESULT_ACCESS)] = -1, | |
1984 | [C(RESULT_MISS)] = -1, | |
1985 | }, | |
1986 | [C(OP_PREFETCH)] = { | |
1987 | [C(RESULT_ACCESS)] = -1, | |
1988 | [C(RESULT_MISS)] = -1, | |
1989 | }, | |
1990 | }, | |
1991 | [C(BPU)] = { | |
1992 | [C(OP_READ)] = { | |
1993 | [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
1994 | [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
1995 | }, | |
1996 | [C(OP_WRITE)] = { | |
1997 | [C(RESULT_ACCESS)] = -1, | |
1998 | [C(RESULT_MISS)] = -1, | |
1999 | }, | |
2000 | [C(OP_PREFETCH)] = { | |
2001 | [C(RESULT_ACCESS)] = -1, | |
2002 | [C(RESULT_MISS)] = -1, | |
2003 | }, | |
2004 | }, | |
2005 | }; | |
2006 | ||
2007 | static __initconst const u64 glp_hw_cache_extra_regs | |
2008 | [PERF_COUNT_HW_CACHE_MAX] | |
2009 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
2010 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
2011 | [C(LL)] = { | |
2012 | [C(OP_READ)] = { | |
2013 | [C(RESULT_ACCESS)] = GLM_DEMAND_READ| | |
2014 | GLM_LLC_ACCESS, | |
2015 | [C(RESULT_MISS)] = GLM_DEMAND_READ| | |
2016 | GLM_LLC_MISS, | |
2017 | }, | |
2018 | [C(OP_WRITE)] = { | |
2019 | [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| | |
2020 | GLM_LLC_ACCESS, | |
2021 | [C(RESULT_MISS)] = GLM_DEMAND_WRITE| | |
2022 | GLM_LLC_MISS, | |
2023 | }, | |
2024 | [C(OP_PREFETCH)] = { | |
2025 | [C(RESULT_ACCESS)] = 0x0, | |
2026 | [C(RESULT_MISS)] = 0x0, | |
2027 | }, | |
2028 | }, | |
2029 | }; | |
2030 | ||
6daeb873 KL |
2031 | #define TNT_LOCAL_DRAM BIT_ULL(26) |
2032 | #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD | |
2033 | #define TNT_DEMAND_WRITE GLM_DEMAND_RFO | |
2034 | #define TNT_LLC_ACCESS GLM_ANY_RESPONSE | |
2035 | #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ | |
2036 | SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) | |
2037 | #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) | |
2038 | ||
2039 | static __initconst const u64 tnt_hw_cache_extra_regs | |
2040 | [PERF_COUNT_HW_CACHE_MAX] | |
2041 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
2042 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
2043 | [C(LL)] = { | |
2044 | [C(OP_READ)] = { | |
2045 | [C(RESULT_ACCESS)] = TNT_DEMAND_READ| | |
2046 | TNT_LLC_ACCESS, | |
2047 | [C(RESULT_MISS)] = TNT_DEMAND_READ| | |
2048 | TNT_LLC_MISS, | |
2049 | }, | |
2050 | [C(OP_WRITE)] = { | |
2051 | [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| | |
2052 | TNT_LLC_ACCESS, | |
2053 | [C(RESULT_MISS)] = TNT_DEMAND_WRITE| | |
2054 | TNT_LLC_MISS, | |
2055 | }, | |
2056 | [C(OP_PREFETCH)] = { | |
2057 | [C(RESULT_ACCESS)] = 0x0, | |
2058 | [C(RESULT_MISS)] = 0x0, | |
2059 | }, | |
2060 | }, | |
2061 | }; | |
2062 | ||
c2208046 KL |
2063 | EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); |
2064 | EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); | |
2065 | EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); | |
2066 | EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); | |
2067 | ||
2068 | static struct attribute *tnt_events_attrs[] = { | |
2069 | EVENT_PTR(td_fe_bound_tnt), | |
2070 | EVENT_PTR(td_retiring_tnt), | |
2071 | EVENT_PTR(td_bad_spec_tnt), | |
2072 | EVENT_PTR(td_be_bound_tnt), | |
2073 | NULL, | |
2074 | }; | |
2075 | ||
6daeb873 KL |
2076 | static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { |
2077 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ | |
0813c405 KL |
2078 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), |
2079 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), | |
6daeb873 KL |
2080 | EVENT_EXTRA_END |
2081 | }; | |
2082 | ||
f83d2f91 KL |
2083 | static struct extra_reg intel_grt_extra_regs[] __read_mostly = { |
2084 | /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ | |
2085 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), | |
2086 | INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), | |
2087 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), | |
2088 | EVENT_EXTRA_END | |
2089 | }; | |
2090 | ||
1e7b9390 HC |
2091 | #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ |
2092 | #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ | |
2093 | #define KNL_MCDRAM_LOCAL BIT_ULL(21) | |
2094 | #define KNL_MCDRAM_FAR BIT_ULL(22) | |
2095 | #define KNL_DDR_LOCAL BIT_ULL(23) | |
2096 | #define KNL_DDR_FAR BIT_ULL(24) | |
2097 | #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ | |
2098 | KNL_DDR_LOCAL | KNL_DDR_FAR) | |
2099 | #define KNL_L2_READ SLM_DMND_READ | |
2100 | #define KNL_L2_WRITE SLM_DMND_WRITE | |
2101 | #define KNL_L2_PREFETCH SLM_DMND_PREFETCH | |
2102 | #define KNL_L2_ACCESS SLM_LLC_ACCESS | |
2103 | #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ | |
2104 | KNL_DRAM_ANY | SNB_SNP_ANY | \ | |
2105 | SNB_NON_DRAM) | |
2106 | ||
2107 | static __initconst const u64 knl_hw_cache_extra_regs | |
2108 | [PERF_COUNT_HW_CACHE_MAX] | |
2109 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
2110 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
2111 | [C(LL)] = { | |
2112 | [C(OP_READ)] = { | |
2113 | [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, | |
2114 | [C(RESULT_MISS)] = 0, | |
2115 | }, | |
2116 | [C(OP_WRITE)] = { | |
2117 | [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, | |
2118 | [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, | |
2119 | }, | |
2120 | [C(OP_PREFETCH)] = { | |
2121 | [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, | |
2122 | [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, | |
2123 | }, | |
2124 | }, | |
2125 | }; | |
2126 | ||
1a78d937 | 2127 | /* |
c3d266c8 KL |
2128 | * Used from PMIs where the LBRs are already disabled. |
2129 | * | |
2130 | * This function could be called consecutively. It is required to remain in | |
2131 | * disabled state if called consecutively. | |
2132 | * | |
2133 | * During consecutive calls, the same disable value will be written to related | |
cecf6235 AS |
2134 | * registers, so the PMU state remains unchanged. |
2135 | * | |
2136 | * intel_bts events don't coexist with intel PMU's BTS events because of | |
2137 | * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them | |
2138 | * disabled around intel PMU's event batching etc, only inside the PMI handler. | |
6c1c07b3 KL |
2139 | * |
2140 | * Avoid PEBS_ENABLE MSR access in PMIs. | |
2141 | * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. | |
2142 | * It doesn't matter if the PEBS is enabled or not. | |
2143 | * Usually, the PEBS status are not changed in PMIs. It's unnecessary to | |
2144 | * access PEBS_ENABLE MSR in disable_all()/enable_all(). | |
2145 | * However, there are some cases which may change PEBS status, e.g. PMI | |
2146 | * throttle. The PEBS_ENABLE should be updated where the status changes. | |
1a78d937 AK |
2147 | */ |
2148 | static void __intel_pmu_disable_all(void) | |
f22f54f4 | 2149 | { |
89cbc767 | 2150 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f22f54f4 PZ |
2151 | |
2152 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
2153 | ||
15c7ad51 | 2154 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) |
f22f54f4 | 2155 | intel_pmu_disable_bts(); |
1a78d937 AK |
2156 | } |
2157 | ||
2158 | static void intel_pmu_disable_all(void) | |
2159 | { | |
2160 | __intel_pmu_disable_all(); | |
6c1c07b3 | 2161 | intel_pmu_pebs_disable_all(); |
caff2bef | 2162 | intel_pmu_lbr_disable_all(); |
f22f54f4 PZ |
2163 | } |
2164 | ||
1a78d937 | 2165 | static void __intel_pmu_enable_all(int added, bool pmi) |
f22f54f4 | 2166 | { |
89cbc767 | 2167 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
fc4b8fca | 2168 | u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); |
f22f54f4 | 2169 | |
1a78d937 | 2170 | intel_pmu_lbr_enable_all(pmi); |
144d31e6 | 2171 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, |
fc4b8fca | 2172 | intel_ctrl & ~cpuc->intel_ctrl_guest_mask); |
f22f54f4 | 2173 | |
15c7ad51 | 2174 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { |
f22f54f4 | 2175 | struct perf_event *event = |
15c7ad51 | 2176 | cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
f22f54f4 PZ |
2177 | |
2178 | if (WARN_ON_ONCE(!event)) | |
2179 | return; | |
2180 | ||
2181 | intel_pmu_enable_bts(event->hw.config); | |
cecf6235 | 2182 | } |
f22f54f4 PZ |
2183 | } |
2184 | ||
1a78d937 AK |
2185 | static void intel_pmu_enable_all(int added) |
2186 | { | |
6c1c07b3 | 2187 | intel_pmu_pebs_enable_all(); |
1a78d937 AK |
2188 | __intel_pmu_enable_all(added, false); |
2189 | } | |
2190 | ||
11164cd4 PZ |
2191 | /* |
2192 | * Workaround for: | |
2193 | * Intel Errata AAK100 (model 26) | |
2194 | * Intel Errata AAP53 (model 30) | |
40b91cd1 | 2195 | * Intel Errata BD53 (model 44) |
11164cd4 | 2196 | * |
351af072 ZY |
2197 | * The official story: |
2198 | * These chips need to be 'reset' when adding counters by programming the | |
2199 | * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either | |
2200 | * in sequence on the same PMC or on different PMCs. | |
2201 | * | |
d9f6e12f | 2202 | * In practice it appears some of these events do in fact count, and |
a97673a1 | 2203 | * we need to program all 4 events. |
11164cd4 | 2204 | */ |
351af072 | 2205 | static void intel_pmu_nhm_workaround(void) |
11164cd4 | 2206 | { |
89cbc767 | 2207 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
351af072 ZY |
2208 | static const unsigned long nhm_magic[4] = { |
2209 | 0x4300B5, | |
2210 | 0x4300D2, | |
2211 | 0x4300B1, | |
2212 | 0x4300B1 | |
2213 | }; | |
2214 | struct perf_event *event; | |
2215 | int i; | |
11164cd4 | 2216 | |
351af072 ZY |
2217 | /* |
2218 | * The Errata requires below steps: | |
2219 | * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; | |
2220 | * 2) Configure 4 PERFEVTSELx with the magic events and clear | |
2221 | * the corresponding PMCx; | |
2222 | * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; | |
2223 | * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; | |
2224 | * 5) Clear 4 pairs of ERFEVTSELx and PMCx; | |
2225 | */ | |
11164cd4 | 2226 | |
351af072 ZY |
2227 | /* |
2228 | * The real steps we choose are a little different from above. | |
2229 | * A) To reduce MSR operations, we don't run step 1) as they | |
2230 | * are already cleared before this function is called; | |
2231 | * B) Call x86_perf_event_update to save PMCx before configuring | |
2232 | * PERFEVTSELx with magic number; | |
2233 | * C) With step 5), we do clear only when the PERFEVTSELx is | |
2234 | * not used currently. | |
2235 | * D) Call x86_perf_event_set_period to restore PMCx; | |
2236 | */ | |
11164cd4 | 2237 | |
351af072 ZY |
2238 | /* We always operate 4 pairs of PERF Counters */ |
2239 | for (i = 0; i < 4; i++) { | |
2240 | event = cpuc->events[i]; | |
2241 | if (event) | |
2242 | x86_perf_event_update(event); | |
2243 | } | |
11164cd4 | 2244 | |
351af072 ZY |
2245 | for (i = 0; i < 4; i++) { |
2246 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); | |
2247 | wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); | |
2248 | } | |
2249 | ||
2250 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); | |
2251 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); | |
11164cd4 | 2252 | |
351af072 ZY |
2253 | for (i = 0; i < 4; i++) { |
2254 | event = cpuc->events[i]; | |
2255 | ||
2256 | if (event) { | |
2257 | x86_perf_event_set_period(event); | |
31fa58af | 2258 | __x86_pmu_enable_event(&event->hw, |
351af072 ZY |
2259 | ARCH_PERFMON_EVENTSEL_ENABLE); |
2260 | } else | |
2261 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); | |
11164cd4 | 2262 | } |
351af072 ZY |
2263 | } |
2264 | ||
2265 | static void intel_pmu_nhm_enable_all(int added) | |
2266 | { | |
2267 | if (added) | |
2268 | intel_pmu_nhm_workaround(); | |
11164cd4 PZ |
2269 | intel_pmu_enable_all(added); |
2270 | } | |
2271 | ||
400816f6 PZI |
2272 | static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) |
2273 | { | |
2274 | u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; | |
2275 | ||
2276 | if (cpuc->tfa_shadow != val) { | |
2277 | cpuc->tfa_shadow = val; | |
2278 | wrmsrl(MSR_TSX_FORCE_ABORT, val); | |
2279 | } | |
2280 | } | |
2281 | ||
2282 | static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) | |
2283 | { | |
2284 | /* | |
2285 | * We're going to use PMC3, make sure TFA is set before we touch it. | |
2286 | */ | |
1a81542a | 2287 | if (cntr == 3) |
400816f6 PZI |
2288 | intel_set_tfa(cpuc, true); |
2289 | } | |
2290 | ||
2291 | static void intel_tfa_pmu_enable_all(int added) | |
2292 | { | |
2293 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2294 | ||
2295 | /* | |
2296 | * If we find PMC3 is no longer used when we enable the PMU, we can | |
2297 | * clear TFA. | |
2298 | */ | |
2299 | if (!test_bit(3, cpuc->active_mask)) | |
2300 | intel_set_tfa(cpuc, false); | |
2301 | ||
2302 | intel_pmu_enable_all(added); | |
2303 | } | |
2304 | ||
f22f54f4 PZ |
2305 | static inline u64 intel_pmu_get_status(void) |
2306 | { | |
2307 | u64 status; | |
2308 | ||
2309 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
2310 | ||
2311 | return status; | |
2312 | } | |
2313 | ||
2314 | static inline void intel_pmu_ack_status(u64 ack) | |
2315 | { | |
2316 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
2317 | } | |
2318 | ||
027440b5 LX |
2319 | static inline bool event_is_checkpointed(struct perf_event *event) |
2320 | { | |
2321 | return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; | |
2322 | } | |
2323 | ||
2324 | static inline void intel_set_masks(struct perf_event *event, int idx) | |
2325 | { | |
2326 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2327 | ||
2328 | if (event->attr.exclude_host) | |
2329 | __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); | |
2330 | if (event->attr.exclude_guest) | |
2331 | __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); | |
2332 | if (event_is_checkpointed(event)) | |
2333 | __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); | |
2334 | } | |
2335 | ||
2336 | static inline void intel_clear_masks(struct perf_event *event, int idx) | |
f22f54f4 | 2337 | { |
027440b5 LX |
2338 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2339 | ||
2340 | __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); | |
2341 | __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); | |
2342 | __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); | |
2343 | } | |
2344 | ||
2345 | static void intel_pmu_disable_fixed(struct perf_event *event) | |
2346 | { | |
2347 | struct hw_perf_event *hwc = &event->hw; | |
f22f54f4 | 2348 | u64 ctrl_val, mask; |
7b2c05a1 | 2349 | int idx = hwc->idx; |
f22f54f4 | 2350 | |
7b2c05a1 KL |
2351 | if (is_topdown_idx(idx)) { |
2352 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2353 | ||
2354 | /* | |
2355 | * When there are other active TopDown events, | |
2356 | * don't disable the fixed counter 3. | |
2357 | */ | |
2358 | if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) | |
2359 | return; | |
2360 | idx = INTEL_PMC_IDX_FIXED_SLOTS; | |
2361 | } | |
f22f54f4 | 2362 | |
7b2c05a1 KL |
2363 | intel_clear_masks(event, idx); |
2364 | ||
2365 | mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); | |
f22f54f4 PZ |
2366 | rdmsrl(hwc->config_base, ctrl_val); |
2367 | ctrl_val &= ~mask; | |
7645a24c | 2368 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
2369 | } |
2370 | ||
ca037701 | 2371 | static void intel_pmu_disable_event(struct perf_event *event) |
f22f54f4 | 2372 | { |
aff3d91a | 2373 | struct hw_perf_event *hwc = &event->hw; |
027440b5 | 2374 | int idx = hwc->idx; |
aff3d91a | 2375 | |
58da7dbe KL |
2376 | switch (idx) { |
2377 | case 0 ... INTEL_PMC_IDX_FIXED - 1: | |
027440b5 LX |
2378 | intel_clear_masks(event, idx); |
2379 | x86_pmu_disable_event(event); | |
58da7dbe KL |
2380 | break; |
2381 | case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: | |
7b2c05a1 | 2382 | case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: |
027440b5 | 2383 | intel_pmu_disable_fixed(event); |
58da7dbe KL |
2384 | break; |
2385 | case INTEL_PMC_IDX_FIXED_BTS: | |
f22f54f4 PZ |
2386 | intel_pmu_disable_bts(); |
2387 | intel_pmu_drain_bts_buffer(); | |
58da7dbe KL |
2388 | return; |
2389 | case INTEL_PMC_IDX_FIXED_VLBR: | |
e1ad1ac2 | 2390 | intel_clear_masks(event, idx); |
58da7dbe KL |
2391 | break; |
2392 | default: | |
2393 | intel_clear_masks(event, idx); | |
2394 | pr_warn("Failed to disable the event with invalid index %d\n", | |
2395 | idx); | |
2396 | return; | |
2397 | } | |
f22f54f4 | 2398 | |
6f55967a JO |
2399 | /* |
2400 | * Needs to be called after x86_pmu_disable_event, | |
2401 | * so we don't trigger the event without PEBS bit set. | |
2402 | */ | |
2403 | if (unlikely(event->attr.precise_ip)) | |
2404 | intel_pmu_pebs_disable(event); | |
f22f54f4 PZ |
2405 | } |
2406 | ||
68f7082f PZ |
2407 | static void intel_pmu_del_event(struct perf_event *event) |
2408 | { | |
2409 | if (needs_branch_stack(event)) | |
2410 | intel_pmu_lbr_del(event); | |
2411 | if (event->attr.precise_ip) | |
2412 | intel_pmu_pebs_del(event); | |
2413 | } | |
2414 | ||
59a854e2 KL |
2415 | static int icl_set_topdown_event_period(struct perf_event *event) |
2416 | { | |
2417 | struct hw_perf_event *hwc = &event->hw; | |
2418 | s64 left = local64_read(&hwc->period_left); | |
2419 | ||
2420 | /* | |
2421 | * The values in PERF_METRICS MSR are derived from fixed counter 3. | |
2422 | * Software should start both registers, PERF_METRICS and fixed | |
2423 | * counter 3, from zero. | |
2424 | * Clear PERF_METRICS and Fixed counter 3 in initialization. | |
2425 | * After that, both MSRs will be cleared for each read. | |
2426 | * Don't need to clear them again. | |
2427 | */ | |
2428 | if (left == x86_pmu.max_period) { | |
2429 | wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); | |
2430 | wrmsrl(MSR_PERF_METRICS, 0); | |
2cb5383b KL |
2431 | hwc->saved_slots = 0; |
2432 | hwc->saved_metric = 0; | |
2433 | } | |
2434 | ||
2435 | if ((hwc->saved_slots) && is_slots_event(event)) { | |
2436 | wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); | |
2437 | wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); | |
59a854e2 KL |
2438 | } |
2439 | ||
2440 | perf_event_update_userpage(event); | |
2441 | ||
2442 | return 0; | |
2443 | } | |
2444 | ||
f83d2f91 KL |
2445 | static int adl_set_topdown_event_period(struct perf_event *event) |
2446 | { | |
2447 | struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); | |
2448 | ||
2449 | if (pmu->cpu_type != hybrid_big) | |
2450 | return 0; | |
2451 | ||
2452 | return icl_set_topdown_event_period(event); | |
2453 | } | |
2454 | ||
59a854e2 KL |
2455 | static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) |
2456 | { | |
2457 | u32 val; | |
2458 | ||
2459 | /* | |
2460 | * The metric is reported as an 8bit integer fraction | |
d9f6e12f | 2461 | * summing up to 0xff. |
59a854e2 KL |
2462 | * slots-in-metric = (Metric / 0xff) * slots |
2463 | */ | |
2464 | val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; | |
2465 | return mul_u64_u32_div(slots, val, 0xff); | |
2466 | } | |
2467 | ||
2cb5383b | 2468 | static u64 icl_get_topdown_value(struct perf_event *event, |
59a854e2 KL |
2469 | u64 slots, u64 metrics) |
2470 | { | |
2471 | int idx = event->hw.idx; | |
2472 | u64 delta; | |
2473 | ||
2474 | if (is_metric_idx(idx)) | |
2475 | delta = icl_get_metrics_event_value(metrics, slots, idx); | |
2476 | else | |
2477 | delta = slots; | |
2478 | ||
2cb5383b KL |
2479 | return delta; |
2480 | } | |
2481 | ||
2482 | static void __icl_update_topdown_event(struct perf_event *event, | |
2483 | u64 slots, u64 metrics, | |
2484 | u64 last_slots, u64 last_metrics) | |
2485 | { | |
2486 | u64 delta, last = 0; | |
2487 | ||
2488 | delta = icl_get_topdown_value(event, slots, metrics); | |
2489 | if (last_slots) | |
2490 | last = icl_get_topdown_value(event, last_slots, last_metrics); | |
2491 | ||
2492 | /* | |
2493 | * The 8bit integer fraction of metric may be not accurate, | |
2494 | * especially when the changes is very small. | |
2495 | * For example, if only a few bad_spec happens, the fraction | |
2496 | * may be reduced from 1 to 0. If so, the bad_spec event value | |
2497 | * will be 0 which is definitely less than the last value. | |
2498 | * Avoid update event->count for this case. | |
2499 | */ | |
2500 | if (delta > last) { | |
2501 | delta -= last; | |
2502 | local64_add(delta, &event->count); | |
2503 | } | |
2504 | } | |
2505 | ||
628d923a KL |
2506 | static void update_saved_topdown_regs(struct perf_event *event, u64 slots, |
2507 | u64 metrics, int metric_end) | |
2cb5383b KL |
2508 | { |
2509 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2510 | struct perf_event *other; | |
2511 | int idx; | |
2512 | ||
2513 | event->hw.saved_slots = slots; | |
2514 | event->hw.saved_metric = metrics; | |
2515 | ||
628d923a | 2516 | for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { |
2cb5383b KL |
2517 | if (!is_topdown_idx(idx)) |
2518 | continue; | |
2519 | other = cpuc->events[idx]; | |
2520 | other->hw.saved_slots = slots; | |
2521 | other->hw.saved_metric = metrics; | |
2522 | } | |
59a854e2 KL |
2523 | } |
2524 | ||
2525 | /* | |
2526 | * Update all active Topdown events. | |
2527 | * | |
2528 | * The PERF_METRICS and Fixed counter 3 are read separately. The values may be | |
2529 | * modify by a NMI. PMU has to be disabled before calling this function. | |
2530 | */ | |
628d923a KL |
2531 | |
2532 | static u64 intel_update_topdown_event(struct perf_event *event, int metric_end) | |
59a854e2 KL |
2533 | { |
2534 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2535 | struct perf_event *other; | |
2536 | u64 slots, metrics; | |
2cb5383b | 2537 | bool reset = true; |
59a854e2 KL |
2538 | int idx; |
2539 | ||
2540 | /* read Fixed counter 3 */ | |
2541 | rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); | |
2542 | if (!slots) | |
2543 | return 0; | |
2544 | ||
2545 | /* read PERF_METRICS */ | |
2546 | rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); | |
2547 | ||
628d923a | 2548 | for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { |
59a854e2 KL |
2549 | if (!is_topdown_idx(idx)) |
2550 | continue; | |
2551 | other = cpuc->events[idx]; | |
2cb5383b KL |
2552 | __icl_update_topdown_event(other, slots, metrics, |
2553 | event ? event->hw.saved_slots : 0, | |
2554 | event ? event->hw.saved_metric : 0); | |
59a854e2 KL |
2555 | } |
2556 | ||
2557 | /* | |
2558 | * Check and update this event, which may have been cleared | |
2559 | * in active_mask e.g. x86_pmu_stop() | |
2560 | */ | |
2cb5383b KL |
2561 | if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { |
2562 | __icl_update_topdown_event(event, slots, metrics, | |
2563 | event->hw.saved_slots, | |
2564 | event->hw.saved_metric); | |
59a854e2 | 2565 | |
2cb5383b KL |
2566 | /* |
2567 | * In x86_pmu_stop(), the event is cleared in active_mask first, | |
2568 | * then drain the delta, which indicates context switch for | |
2569 | * counting. | |
2570 | * Save metric and slots for context switch. | |
2571 | * Don't need to reset the PERF_METRICS and Fixed counter 3. | |
2572 | * Because the values will be restored in next schedule in. | |
2573 | */ | |
628d923a | 2574 | update_saved_topdown_regs(event, slots, metrics, metric_end); |
2cb5383b KL |
2575 | reset = false; |
2576 | } | |
2577 | ||
2578 | if (reset) { | |
2579 | /* The fixed counter 3 has to be written before the PERF_METRICS. */ | |
2580 | wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); | |
2581 | wrmsrl(MSR_PERF_METRICS, 0); | |
2582 | if (event) | |
628d923a | 2583 | update_saved_topdown_regs(event, 0, 0, metric_end); |
2cb5383b | 2584 | } |
59a854e2 KL |
2585 | |
2586 | return slots; | |
2587 | } | |
2588 | ||
628d923a KL |
2589 | static u64 icl_update_topdown_event(struct perf_event *event) |
2590 | { | |
1ab5f235 KL |
2591 | return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + |
2592 | x86_pmu.num_topdown_events - 1); | |
628d923a KL |
2593 | } |
2594 | ||
f83d2f91 KL |
2595 | static u64 adl_update_topdown_event(struct perf_event *event) |
2596 | { | |
2597 | struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); | |
2598 | ||
2599 | if (pmu->cpu_type != hybrid_big) | |
2600 | return 0; | |
2601 | ||
2602 | return icl_update_topdown_event(event); | |
2603 | } | |
2604 | ||
2605 | ||
7b2c05a1 KL |
2606 | static void intel_pmu_read_topdown_event(struct perf_event *event) |
2607 | { | |
2608 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2609 | ||
2610 | /* Only need to call update_topdown_event() once for group read. */ | |
2611 | if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && | |
2612 | !is_slots_event(event)) | |
2613 | return; | |
2614 | ||
2615 | perf_pmu_disable(event->pmu); | |
2616 | x86_pmu.update_topdown_event(event); | |
2617 | perf_pmu_enable(event->pmu); | |
2618 | } | |
2619 | ||
ceb90d9e KL |
2620 | static void intel_pmu_read_event(struct perf_event *event) |
2621 | { | |
2622 | if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) | |
2623 | intel_pmu_auto_reload_read(event); | |
7b2c05a1 KL |
2624 | else if (is_topdown_count(event) && x86_pmu.update_topdown_event) |
2625 | intel_pmu_read_topdown_event(event); | |
ceb90d9e KL |
2626 | else |
2627 | x86_perf_event_update(event); | |
2628 | } | |
2629 | ||
4f08b625 | 2630 | static void intel_pmu_enable_fixed(struct perf_event *event) |
f22f54f4 | 2631 | { |
4f08b625 | 2632 | struct hw_perf_event *hwc = &event->hw; |
4f08b625 | 2633 | u64 ctrl_val, mask, bits = 0; |
7b2c05a1 KL |
2634 | int idx = hwc->idx; |
2635 | ||
2636 | if (is_topdown_idx(idx)) { | |
2637 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2638 | /* | |
2639 | * When there are other active TopDown events, | |
2640 | * don't enable the fixed counter 3 again. | |
2641 | */ | |
2642 | if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) | |
2643 | return; | |
2644 | ||
2645 | idx = INTEL_PMC_IDX_FIXED_SLOTS; | |
2646 | } | |
2647 | ||
2648 | intel_set_masks(event, idx); | |
f22f54f4 PZ |
2649 | |
2650 | /* | |
4f08b625 | 2651 | * Enable IRQ generation (0x8), if not PEBS, |
f22f54f4 PZ |
2652 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) |
2653 | * if requested: | |
2654 | */ | |
4f08b625 KL |
2655 | if (!event->attr.precise_ip) |
2656 | bits |= 0x8; | |
f22f54f4 PZ |
2657 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) |
2658 | bits |= 0x2; | |
2659 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
2660 | bits |= 0x1; | |
2661 | ||
2662 | /* | |
2663 | * ANY bit is supported in v3 and up | |
2664 | */ | |
2665 | if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) | |
2666 | bits |= 0x4; | |
2667 | ||
7b2c05a1 | 2668 | idx -= INTEL_PMC_IDX_FIXED; |
f22f54f4 PZ |
2669 | bits <<= (idx * 4); |
2670 | mask = 0xfULL << (idx * 4); | |
2671 | ||
c22497f5 KL |
2672 | if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { |
2673 | bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); | |
2674 | mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); | |
2675 | } | |
2676 | ||
f22f54f4 PZ |
2677 | rdmsrl(hwc->config_base, ctrl_val); |
2678 | ctrl_val &= ~mask; | |
2679 | ctrl_val |= bits; | |
7645a24c | 2680 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
2681 | } |
2682 | ||
aff3d91a | 2683 | static void intel_pmu_enable_event(struct perf_event *event) |
f22f54f4 | 2684 | { |
aff3d91a | 2685 | struct hw_perf_event *hwc = &event->hw; |
027440b5 | 2686 | int idx = hwc->idx; |
2b9e344d | 2687 | |
4f08b625 KL |
2688 | if (unlikely(event->attr.precise_ip)) |
2689 | intel_pmu_pebs_enable(event); | |
2690 | ||
58da7dbe KL |
2691 | switch (idx) { |
2692 | case 0 ... INTEL_PMC_IDX_FIXED - 1: | |
027440b5 LX |
2693 | intel_set_masks(event, idx); |
2694 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); | |
58da7dbe KL |
2695 | break; |
2696 | case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: | |
7b2c05a1 | 2697 | case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: |
4f08b625 | 2698 | intel_pmu_enable_fixed(event); |
58da7dbe KL |
2699 | break; |
2700 | case INTEL_PMC_IDX_FIXED_BTS: | |
027440b5 LX |
2701 | if (!__this_cpu_read(cpu_hw_events.enabled)) |
2702 | return; | |
2703 | intel_pmu_enable_bts(hwc->config); | |
58da7dbe KL |
2704 | break; |
2705 | case INTEL_PMC_IDX_FIXED_VLBR: | |
e1ad1ac2 | 2706 | intel_set_masks(event, idx); |
58da7dbe KL |
2707 | break; |
2708 | default: | |
2709 | pr_warn("Failed to enable the event with invalid index %d\n", | |
2710 | idx); | |
2711 | } | |
f22f54f4 PZ |
2712 | } |
2713 | ||
68f7082f PZ |
2714 | static void intel_pmu_add_event(struct perf_event *event) |
2715 | { | |
2716 | if (event->attr.precise_ip) | |
2717 | intel_pmu_pebs_add(event); | |
2718 | if (needs_branch_stack(event)) | |
2719 | intel_pmu_lbr_add(event); | |
2720 | } | |
2721 | ||
f22f54f4 PZ |
2722 | /* |
2723 | * Save and restart an expired event. Called by NMI contexts, | |
2724 | * so it has to be careful about preempting normal event ops: | |
2725 | */ | |
de0428a7 | 2726 | int intel_pmu_save_and_restart(struct perf_event *event) |
f22f54f4 | 2727 | { |
cc2ad4ba | 2728 | x86_perf_event_update(event); |
2dbf0116 AK |
2729 | /* |
2730 | * For a checkpointed counter always reset back to 0. This | |
2731 | * avoids a situation where the counter overflows, aborts the | |
2732 | * transaction and is then set back to shortly before the | |
2733 | * overflow, and overflows and aborts again. | |
2734 | */ | |
2735 | if (unlikely(event_is_checkpointed(event))) { | |
2736 | /* No race with NMIs because the counter should not be armed */ | |
2737 | wrmsrl(event->hw.event_base, 0); | |
2738 | local64_set(&event->hw.prev_count, 0); | |
2739 | } | |
cc2ad4ba | 2740 | return x86_perf_event_set_period(event); |
f22f54f4 PZ |
2741 | } |
2742 | ||
2743 | static void intel_pmu_reset(void) | |
2744 | { | |
0a3aee0d | 2745 | struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); |
fc4b8fca | 2746 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
d4b294bf KL |
2747 | int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); |
2748 | int num_counters = hybrid(cpuc->pmu, num_counters); | |
f22f54f4 PZ |
2749 | unsigned long flags; |
2750 | int idx; | |
2751 | ||
d4b294bf | 2752 | if (!num_counters) |
f22f54f4 PZ |
2753 | return; |
2754 | ||
2755 | local_irq_save(flags); | |
2756 | ||
c767a54b | 2757 | pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); |
f22f54f4 | 2758 | |
d4b294bf | 2759 | for (idx = 0; idx < num_counters; idx++) { |
715c85b1 PA |
2760 | wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); |
2761 | wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); | |
f22f54f4 | 2762 | } |
d4b294bf | 2763 | for (idx = 0; idx < num_counters_fixed; idx++) { |
fc4b8fca | 2764 | if (fixed_counter_disabled(idx, cpuc->pmu)) |
32451614 | 2765 | continue; |
715c85b1 | 2766 | wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); |
32451614 | 2767 | } |
948b1bb8 | 2768 | |
f22f54f4 PZ |
2769 | if (ds) |
2770 | ds->bts_index = ds->bts_buffer_base; | |
2771 | ||
8882edf7 AK |
2772 | /* Ack all overflows and disable fixed counters */ |
2773 | if (x86_pmu.version >= 2) { | |
2774 | intel_pmu_ack_status(intel_pmu_get_status()); | |
2775 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
2776 | } | |
2777 | ||
2778 | /* Reset LBRs and LBR freezing */ | |
2779 | if (x86_pmu.lbr_nr) { | |
2780 | update_debugctlmsr(get_debugctlmsr() & | |
2781 | ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); | |
2782 | } | |
2783 | ||
f22f54f4 PZ |
2784 | local_irq_restore(flags); |
2785 | } | |
2786 | ||
ba12d20e | 2787 | static int handle_pmi_common(struct pt_regs *regs, u64 status) |
f22f54f4 PZ |
2788 | { |
2789 | struct perf_sample_data data; | |
ba12d20e | 2790 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ee35baf3 | 2791 | struct perf_guest_info_callbacks *guest_cbs; |
ba12d20e KL |
2792 | int bit; |
2793 | int handled = 0; | |
fc4b8fca | 2794 | u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); |
f22f54f4 PZ |
2795 | |
2796 | inc_irq_stat(apic_perf_irqs); | |
ca037701 | 2797 | |
b292d7a1 | 2798 | /* |
d8020bee AK |
2799 | * Ignore a range of extra bits in status that do not indicate |
2800 | * overflow by themselves. | |
b292d7a1 | 2801 | */ |
d8020bee AK |
2802 | status &= ~(GLOBAL_STATUS_COND_CHG | |
2803 | GLOBAL_STATUS_ASIF | | |
2804 | GLOBAL_STATUS_LBRS_FROZEN); | |
2805 | if (!status) | |
ba12d20e | 2806 | return 0; |
daa864b8 SE |
2807 | /* |
2808 | * In case multiple PEBS events are sampled at the same time, | |
2809 | * it is possible to have GLOBAL_STATUS bit 62 set indicating | |
2810 | * PEBS buffer overflow and also seeing at most 3 PEBS counters | |
2811 | * having their bits set in the status register. This is a sign | |
2812 | * that there was at least one PEBS record pending at the time | |
2813 | * of the PMU interrupt. PEBS counters must only be processed | |
2814 | * via the drain_pebs() calls and not via the regular sample | |
2815 | * processing loop coming after that the function, otherwise | |
2816 | * phony regular samples may be generated in the sampling buffer | |
2817 | * not marked with the EXACT tag. Another possibility is to have | |
163b0991 | 2818 | * one PEBS event and at least one non-PEBS event which overflows |
daa864b8 SE |
2819 | * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will |
2820 | * not be set, yet the overflow status bit for the PEBS counter will | |
2821 | * be on Skylake. | |
2822 | * | |
2823 | * To avoid this problem, we systematically ignore the PEBS-enabled | |
2824 | * counters from the GLOBAL_STATUS mask and we always process PEBS | |
2825 | * events via drain_pebs(). | |
2826 | */ | |
ec71a398 KL |
2827 | if (x86_pmu.flags & PMU_FL_PEBS_ALL) |
2828 | status &= ~cpuc->pebs_enabled; | |
2829 | else | |
2830 | status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); | |
b292d7a1 | 2831 | |
ca037701 PZ |
2832 | /* |
2833 | * PEBS overflow sets bit 62 in the global status register | |
2834 | */ | |
60a2a271 | 2835 | if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { |
6c1c07b3 KL |
2836 | u64 pebs_enabled = cpuc->pebs_enabled; |
2837 | ||
de725dec | 2838 | handled++; |
9dfa9a5c | 2839 | x86_pmu.drain_pebs(regs, &data); |
fc4b8fca | 2840 | status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; |
6c1c07b3 KL |
2841 | |
2842 | /* | |
2843 | * PMI throttle may be triggered, which stops the PEBS event. | |
2844 | * Although cpuc->pebs_enabled is updated accordingly, the | |
2845 | * MSR_IA32_PEBS_ENABLE is not updated. Because the | |
2846 | * cpuc->enabled has been forced to 0 in PMI. | |
2847 | * Update the MSR if pebs_enabled is changed. | |
2848 | */ | |
2849 | if (pebs_enabled != cpuc->pebs_enabled) | |
2850 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); | |
de725dec | 2851 | } |
ca037701 | 2852 | |
52ca9ced AS |
2853 | /* |
2854 | * Intel PT | |
2855 | */ | |
60a2a271 | 2856 | if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { |
52ca9ced | 2857 | handled++; |
ee35baf3 SC |
2858 | |
2859 | guest_cbs = perf_get_guest_cbs(); | |
2860 | if (unlikely(guest_cbs && guest_cbs->is_in_guest() && | |
2861 | guest_cbs->handle_intel_pt_intr)) | |
2862 | guest_cbs->handle_intel_pt_intr(); | |
8479e04e LK |
2863 | else |
2864 | intel_pt_interrupt(); | |
52ca9ced AS |
2865 | } |
2866 | ||
7b2c05a1 | 2867 | /* |
d9f6e12f | 2868 | * Intel Perf metrics |
7b2c05a1 KL |
2869 | */ |
2870 | if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { | |
2871 | handled++; | |
2872 | if (x86_pmu.update_topdown_event) | |
2873 | x86_pmu.update_topdown_event(NULL); | |
2874 | } | |
2875 | ||
2dbf0116 | 2876 | /* |
2b9e344d PZ |
2877 | * Checkpointed counters can lead to 'spurious' PMIs because the |
2878 | * rollback caused by the PMI will have cleared the overflow status | |
2879 | * bit. Therefore always force probe these counters. | |
2dbf0116 | 2880 | */ |
2b9e344d | 2881 | status |= cpuc->intel_cp_status; |
2dbf0116 | 2882 | |
984b3f57 | 2883 | for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
f22f54f4 PZ |
2884 | struct perf_event *event = cpuc->events[bit]; |
2885 | ||
de725dec PZ |
2886 | handled++; |
2887 | ||
f22f54f4 PZ |
2888 | if (!test_bit(bit, cpuc->active_mask)) |
2889 | continue; | |
2890 | ||
2891 | if (!intel_pmu_save_and_restart(event)) | |
2892 | continue; | |
2893 | ||
fd0d000b | 2894 | perf_sample_data_init(&data, 0, event->hw.last_period); |
f22f54f4 | 2895 | |
60ce0fbd SE |
2896 | if (has_branch_stack(event)) |
2897 | data.br_stack = &cpuc->lbr_stack; | |
2898 | ||
a8b0ca17 | 2899 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 2900 | x86_pmu_stop(event, 0); |
f22f54f4 PZ |
2901 | } |
2902 | ||
ba12d20e KL |
2903 | return handled; |
2904 | } | |
2905 | ||
2906 | /* | |
2907 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
2908 | * rules apply: | |
2909 | */ | |
2910 | static int intel_pmu_handle_irq(struct pt_regs *regs) | |
2911 | { | |
acade637 KL |
2912 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2913 | bool late_ack = hybrid_bit(cpuc->pmu, late_ack); | |
2914 | bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); | |
ba12d20e KL |
2915 | int loops; |
2916 | u64 status; | |
2917 | int handled; | |
2918 | int pmu_enabled; | |
2919 | ||
ba12d20e KL |
2920 | /* |
2921 | * Save the PMU state. | |
2922 | * It needs to be restored when leaving the handler. | |
2923 | */ | |
2924 | pmu_enabled = cpuc->enabled; | |
2925 | /* | |
acade637 KL |
2926 | * In general, the early ACK is only applied for old platforms. |
2927 | * For the big core starts from Haswell, the late ACK should be | |
2928 | * applied. | |
2929 | * For the small core after Tremont, we have to do the ACK right | |
2930 | * before re-enabling counters, which is in the middle of the | |
2931 | * NMI handler. | |
ba12d20e | 2932 | */ |
acade637 | 2933 | if (!late_ack && !mid_ack) |
ba12d20e KL |
2934 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
2935 | intel_bts_disable_local(); | |
2936 | cpuc->enabled = 0; | |
2937 | __intel_pmu_disable_all(); | |
2938 | handled = intel_pmu_drain_bts_buffer(); | |
2939 | handled += intel_bts_interrupt(); | |
2940 | status = intel_pmu_get_status(); | |
2941 | if (!status) | |
2942 | goto done; | |
2943 | ||
2944 | loops = 0; | |
2945 | again: | |
2946 | intel_pmu_lbr_read(); | |
2947 | intel_pmu_ack_status(status); | |
2948 | if (++loops > 100) { | |
2949 | static bool warned; | |
2950 | ||
2951 | if (!warned) { | |
2952 | WARN(1, "perfevents: irq loop stuck!\n"); | |
2953 | perf_event_print_debug(); | |
2954 | warned = true; | |
2955 | } | |
2956 | intel_pmu_reset(); | |
2957 | goto done; | |
2958 | } | |
2959 | ||
2960 | handled += handle_pmi_common(regs, status); | |
2961 | ||
f22f54f4 PZ |
2962 | /* |
2963 | * Repeat if there is more work to be done: | |
2964 | */ | |
2965 | status = intel_pmu_get_status(); | |
2966 | if (status) | |
2967 | goto again; | |
2968 | ||
3fb2b8dd | 2969 | done: |
acade637 KL |
2970 | if (mid_ack) |
2971 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
c3d266c8 | 2972 | /* Only restore PMU state when it's active. See x86_pmu_disable(). */ |
82d71ed0 KL |
2973 | cpuc->enabled = pmu_enabled; |
2974 | if (pmu_enabled) | |
c3d266c8 | 2975 | __intel_pmu_enable_all(0, true); |
cecf6235 | 2976 | intel_bts_enable_local(); |
c3d266c8 | 2977 | |
72db5596 AK |
2978 | /* |
2979 | * Only unmask the NMI after the overflow counters | |
2980 | * have been reset. This avoids spurious NMIs on | |
2981 | * Haswell CPUs. | |
2982 | */ | |
acade637 | 2983 | if (late_ack) |
72db5596 | 2984 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
de725dec | 2985 | return handled; |
f22f54f4 PZ |
2986 | } |
2987 | ||
f22f54f4 | 2988 | static struct event_constraint * |
ca037701 | 2989 | intel_bts_constraints(struct perf_event *event) |
f22f54f4 | 2990 | { |
67266c10 | 2991 | if (unlikely(intel_pmu_has_bts(event))) |
f22f54f4 | 2992 | return &bts_constraint; |
ca037701 | 2993 | |
f22f54f4 PZ |
2994 | return NULL; |
2995 | } | |
2996 | ||
097e4311 LX |
2997 | /* |
2998 | * Note: matches a fake event, like Fixed2. | |
2999 | */ | |
3000 | static struct event_constraint * | |
3001 | intel_vlbr_constraints(struct perf_event *event) | |
3002 | { | |
3003 | struct event_constraint *c = &vlbr_constraint; | |
3004 | ||
13e6e32d LX |
3005 | if (unlikely(constraint_match(c, event->hw.config))) { |
3006 | event->hw.flags |= c->flags; | |
097e4311 | 3007 | return c; |
13e6e32d | 3008 | } |
097e4311 LX |
3009 | |
3010 | return NULL; | |
3011 | } | |
3012 | ||
183af736 KL |
3013 | static int intel_alt_er(struct cpu_hw_events *cpuc, |
3014 | int idx, u64 config) | |
b79e8941 | 3015 | { |
183af736 | 3016 | struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); |
e01d8718 PZ |
3017 | int alt_idx = idx; |
3018 | ||
9a5e3fb5 | 3019 | if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) |
5a425294 | 3020 | return idx; |
b79e8941 | 3021 | |
5a425294 | 3022 | if (idx == EXTRA_REG_RSP_0) |
ae3f011f | 3023 | alt_idx = EXTRA_REG_RSP_1; |
5a425294 PZ |
3024 | |
3025 | if (idx == EXTRA_REG_RSP_1) | |
ae3f011f | 3026 | alt_idx = EXTRA_REG_RSP_0; |
5a425294 | 3027 | |
183af736 | 3028 | if (config & ~extra_regs[alt_idx].valid_mask) |
ae3f011f KL |
3029 | return idx; |
3030 | ||
3031 | return alt_idx; | |
5a425294 PZ |
3032 | } |
3033 | ||
3034 | static void intel_fixup_er(struct perf_event *event, int idx) | |
3035 | { | |
183af736 | 3036 | struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); |
5a425294 PZ |
3037 | event->hw.extra_reg.idx = idx; |
3038 | ||
3039 | if (idx == EXTRA_REG_RSP_0) { | |
b79e8941 | 3040 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; |
183af736 | 3041 | event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; |
b79e8941 | 3042 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; |
5a425294 PZ |
3043 | } else if (idx == EXTRA_REG_RSP_1) { |
3044 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; | |
183af736 | 3045 | event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; |
5a425294 | 3046 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; |
b79e8941 | 3047 | } |
b79e8941 PZ |
3048 | } |
3049 | ||
efc9f05d SE |
3050 | /* |
3051 | * manage allocation of shared extra msr for certain events | |
3052 | * | |
3053 | * sharing can be: | |
3054 | * per-cpu: to be shared between the various events on a single PMU | |
3055 | * per-core: per-cpu + shared by HT threads | |
3056 | */ | |
a7e3ed1e | 3057 | static struct event_constraint * |
efc9f05d | 3058 | __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, |
b36817e8 SE |
3059 | struct perf_event *event, |
3060 | struct hw_perf_event_extra *reg) | |
a7e3ed1e | 3061 | { |
efc9f05d | 3062 | struct event_constraint *c = &emptyconstraint; |
a7e3ed1e | 3063 | struct er_account *era; |
cd8a38d3 | 3064 | unsigned long flags; |
5a425294 | 3065 | int idx = reg->idx; |
a7e3ed1e | 3066 | |
5a425294 PZ |
3067 | /* |
3068 | * reg->alloc can be set due to existing state, so for fake cpuc we | |
3069 | * need to ignore this, otherwise we might fail to allocate proper fake | |
3070 | * state for this extra reg constraint. Also see the comment below. | |
3071 | */ | |
3072 | if (reg->alloc && !cpuc->is_fake) | |
b36817e8 | 3073 | return NULL; /* call x86_get_event_constraint() */ |
a7e3ed1e | 3074 | |
b79e8941 | 3075 | again: |
5a425294 | 3076 | era = &cpuc->shared_regs->regs[idx]; |
cd8a38d3 SE |
3077 | /* |
3078 | * we use spin_lock_irqsave() to avoid lockdep issues when | |
3079 | * passing a fake cpuc | |
3080 | */ | |
3081 | raw_spin_lock_irqsave(&era->lock, flags); | |
efc9f05d SE |
3082 | |
3083 | if (!atomic_read(&era->ref) || era->config == reg->config) { | |
3084 | ||
5a425294 PZ |
3085 | /* |
3086 | * If its a fake cpuc -- as per validate_{group,event}() we | |
3087 | * shouldn't touch event state and we can avoid doing so | |
3088 | * since both will only call get_event_constraints() once | |
3089 | * on each event, this avoids the need for reg->alloc. | |
3090 | * | |
3091 | * Not doing the ER fixup will only result in era->reg being | |
3092 | * wrong, but since we won't actually try and program hardware | |
3093 | * this isn't a problem either. | |
3094 | */ | |
3095 | if (!cpuc->is_fake) { | |
3096 | if (idx != reg->idx) | |
3097 | intel_fixup_er(event, idx); | |
3098 | ||
3099 | /* | |
3100 | * x86_schedule_events() can call get_event_constraints() | |
3101 | * multiple times on events in the case of incremental | |
3102 | * scheduling(). reg->alloc ensures we only do the ER | |
3103 | * allocation once. | |
3104 | */ | |
3105 | reg->alloc = 1; | |
3106 | } | |
3107 | ||
efc9f05d SE |
3108 | /* lock in msr value */ |
3109 | era->config = reg->config; | |
3110 | era->reg = reg->reg; | |
3111 | ||
3112 | /* one more user */ | |
3113 | atomic_inc(&era->ref); | |
3114 | ||
a7e3ed1e | 3115 | /* |
b36817e8 SE |
3116 | * need to call x86_get_event_constraint() |
3117 | * to check if associated event has constraints | |
a7e3ed1e | 3118 | */ |
b36817e8 | 3119 | c = NULL; |
5a425294 | 3120 | } else { |
183af736 | 3121 | idx = intel_alt_er(cpuc, idx, reg->config); |
5a425294 PZ |
3122 | if (idx != reg->idx) { |
3123 | raw_spin_unlock_irqrestore(&era->lock, flags); | |
3124 | goto again; | |
3125 | } | |
a7e3ed1e | 3126 | } |
cd8a38d3 | 3127 | raw_spin_unlock_irqrestore(&era->lock, flags); |
a7e3ed1e | 3128 | |
efc9f05d SE |
3129 | return c; |
3130 | } | |
3131 | ||
3132 | static void | |
3133 | __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, | |
3134 | struct hw_perf_event_extra *reg) | |
3135 | { | |
3136 | struct er_account *era; | |
3137 | ||
3138 | /* | |
5a425294 PZ |
3139 | * Only put constraint if extra reg was actually allocated. Also takes |
3140 | * care of event which do not use an extra shared reg. | |
3141 | * | |
3142 | * Also, if this is a fake cpuc we shouldn't touch any event state | |
3143 | * (reg->alloc) and we don't care about leaving inconsistent cpuc state | |
3144 | * either since it'll be thrown out. | |
efc9f05d | 3145 | */ |
5a425294 | 3146 | if (!reg->alloc || cpuc->is_fake) |
efc9f05d SE |
3147 | return; |
3148 | ||
3149 | era = &cpuc->shared_regs->regs[reg->idx]; | |
3150 | ||
3151 | /* one fewer user */ | |
3152 | atomic_dec(&era->ref); | |
3153 | ||
3154 | /* allocate again next time */ | |
3155 | reg->alloc = 0; | |
3156 | } | |
3157 | ||
3158 | static struct event_constraint * | |
3159 | intel_shared_regs_constraints(struct cpu_hw_events *cpuc, | |
3160 | struct perf_event *event) | |
3161 | { | |
b36817e8 SE |
3162 | struct event_constraint *c = NULL, *d; |
3163 | struct hw_perf_event_extra *xreg, *breg; | |
3164 | ||
3165 | xreg = &event->hw.extra_reg; | |
3166 | if (xreg->idx != EXTRA_REG_NONE) { | |
3167 | c = __intel_shared_reg_get_constraints(cpuc, event, xreg); | |
3168 | if (c == &emptyconstraint) | |
3169 | return c; | |
3170 | } | |
3171 | breg = &event->hw.branch_reg; | |
3172 | if (breg->idx != EXTRA_REG_NONE) { | |
3173 | d = __intel_shared_reg_get_constraints(cpuc, event, breg); | |
3174 | if (d == &emptyconstraint) { | |
3175 | __intel_shared_reg_put_constraints(cpuc, xreg); | |
3176 | c = d; | |
3177 | } | |
3178 | } | |
efc9f05d | 3179 | return c; |
a7e3ed1e AK |
3180 | } |
3181 | ||
de0428a7 | 3182 | struct event_constraint * |
79cba822 SE |
3183 | x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
3184 | struct perf_event *event) | |
de0428a7 | 3185 | { |
24ee38ff | 3186 | struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); |
de0428a7 KW |
3187 | struct event_constraint *c; |
3188 | ||
24ee38ff KL |
3189 | if (event_constraints) { |
3190 | for_each_event_constraint(c, event_constraints) { | |
63b79f6e | 3191 | if (constraint_match(c, event->hw.config)) { |
9fac2cf3 | 3192 | event->hw.flags |= c->flags; |
de0428a7 | 3193 | return c; |
9fac2cf3 | 3194 | } |
de0428a7 KW |
3195 | } |
3196 | } | |
3197 | ||
eaacf07d | 3198 | return &hybrid_var(cpuc->pmu, unconstrained); |
de0428a7 KW |
3199 | } |
3200 | ||
f22f54f4 | 3201 | static struct event_constraint * |
e979121b | 3202 | __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
79cba822 | 3203 | struct perf_event *event) |
f22f54f4 PZ |
3204 | { |
3205 | struct event_constraint *c; | |
3206 | ||
097e4311 LX |
3207 | c = intel_vlbr_constraints(event); |
3208 | if (c) | |
3209 | return c; | |
3210 | ||
ca037701 PZ |
3211 | c = intel_bts_constraints(event); |
3212 | if (c) | |
3213 | return c; | |
3214 | ||
687805e4 | 3215 | c = intel_shared_regs_constraints(cpuc, event); |
f22f54f4 PZ |
3216 | if (c) |
3217 | return c; | |
3218 | ||
687805e4 | 3219 | c = intel_pebs_constraints(event); |
a7e3ed1e AK |
3220 | if (c) |
3221 | return c; | |
3222 | ||
79cba822 | 3223 | return x86_get_event_constraints(cpuc, idx, event); |
f22f54f4 PZ |
3224 | } |
3225 | ||
e979121b MD |
3226 | static void |
3227 | intel_start_scheduling(struct cpu_hw_events *cpuc) | |
3228 | { | |
3229 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
1c565833 | 3230 | struct intel_excl_states *xl; |
e979121b | 3231 | int tid = cpuc->excl_thread_id; |
e979121b MD |
3232 | |
3233 | /* | |
3234 | * nothing needed if in group validation mode | |
3235 | */ | |
b37609c3 | 3236 | if (cpuc->is_fake || !is_ht_workaround_enabled()) |
e979121b | 3237 | return; |
b37609c3 | 3238 | |
e979121b MD |
3239 | /* |
3240 | * no exclusion needed | |
3241 | */ | |
17186ccd | 3242 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b MD |
3243 | return; |
3244 | ||
e979121b MD |
3245 | xl = &excl_cntrs->states[tid]; |
3246 | ||
3247 | xl->sched_started = true; | |
e979121b MD |
3248 | /* |
3249 | * lock shared state until we are done scheduling | |
3250 | * in stop_event_scheduling() | |
3251 | * makes scheduling appear as a transaction | |
3252 | */ | |
e979121b | 3253 | raw_spin_lock(&excl_cntrs->lock); |
e979121b MD |
3254 | } |
3255 | ||
0c41e756 PZ |
3256 | static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) |
3257 | { | |
3258 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
3259 | struct event_constraint *c = cpuc->event_constraint[idx]; | |
3260 | struct intel_excl_states *xl; | |
3261 | int tid = cpuc->excl_thread_id; | |
3262 | ||
3263 | if (cpuc->is_fake || !is_ht_workaround_enabled()) | |
3264 | return; | |
3265 | ||
3266 | if (WARN_ON_ONCE(!excl_cntrs)) | |
3267 | return; | |
3268 | ||
3269 | if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) | |
3270 | return; | |
3271 | ||
3272 | xl = &excl_cntrs->states[tid]; | |
3273 | ||
3274 | lockdep_assert_held(&excl_cntrs->lock); | |
3275 | ||
1fe684e3 | 3276 | if (c->flags & PERF_X86_EVENT_EXCL) |
43ef205b | 3277 | xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; |
1fe684e3 | 3278 | else |
43ef205b | 3279 | xl->state[cntr] = INTEL_EXCL_SHARED; |
0c41e756 PZ |
3280 | } |
3281 | ||
e979121b MD |
3282 | static void |
3283 | intel_stop_scheduling(struct cpu_hw_events *cpuc) | |
3284 | { | |
3285 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
1c565833 | 3286 | struct intel_excl_states *xl; |
e979121b | 3287 | int tid = cpuc->excl_thread_id; |
e979121b MD |
3288 | |
3289 | /* | |
3290 | * nothing needed if in group validation mode | |
3291 | */ | |
b37609c3 | 3292 | if (cpuc->is_fake || !is_ht_workaround_enabled()) |
e979121b MD |
3293 | return; |
3294 | /* | |
3295 | * no exclusion needed | |
3296 | */ | |
17186ccd | 3297 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b MD |
3298 | return; |
3299 | ||
e979121b MD |
3300 | xl = &excl_cntrs->states[tid]; |
3301 | ||
e979121b MD |
3302 | xl->sched_started = false; |
3303 | /* | |
3304 | * release shared state lock (acquired in intel_start_scheduling()) | |
3305 | */ | |
3306 | raw_spin_unlock(&excl_cntrs->lock); | |
3307 | } | |
3308 | ||
11f8b2d6 PZI |
3309 | static struct event_constraint * |
3310 | dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) | |
3311 | { | |
3312 | WARN_ON_ONCE(!cpuc->constraint_list); | |
3313 | ||
3314 | if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { | |
3315 | struct event_constraint *cx; | |
3316 | ||
3317 | /* | |
3318 | * grab pre-allocated constraint entry | |
3319 | */ | |
3320 | cx = &cpuc->constraint_list[idx]; | |
3321 | ||
3322 | /* | |
3323 | * initialize dynamic constraint | |
3324 | * with static constraint | |
3325 | */ | |
3326 | *cx = *c; | |
3327 | ||
3328 | /* | |
3329 | * mark constraint as dynamic | |
3330 | */ | |
3331 | cx->flags |= PERF_X86_EVENT_DYNAMIC; | |
3332 | c = cx; | |
3333 | } | |
3334 | ||
3335 | return c; | |
3336 | } | |
3337 | ||
e979121b MD |
3338 | static struct event_constraint * |
3339 | intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, | |
3340 | int idx, struct event_constraint *c) | |
3341 | { | |
e979121b | 3342 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; |
1c565833 | 3343 | struct intel_excl_states *xlo; |
e979121b | 3344 | int tid = cpuc->excl_thread_id; |
c090cb70 | 3345 | int is_excl, i, w; |
e979121b MD |
3346 | |
3347 | /* | |
3348 | * validating a group does not require | |
3349 | * enforcing cross-thread exclusion | |
3350 | */ | |
b37609c3 SE |
3351 | if (cpuc->is_fake || !is_ht_workaround_enabled()) |
3352 | return c; | |
3353 | ||
3354 | /* | |
3355 | * no exclusion needed | |
3356 | */ | |
17186ccd | 3357 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b | 3358 | return c; |
e979121b | 3359 | |
e979121b MD |
3360 | /* |
3361 | * because we modify the constraint, we need | |
3362 | * to make a copy. Static constraints come | |
3363 | * from static const tables. | |
3364 | * | |
3365 | * only needed when constraint has not yet | |
3366 | * been cloned (marked dynamic) | |
3367 | */ | |
11f8b2d6 | 3368 | c = dyn_constraint(cpuc, c, idx); |
e979121b MD |
3369 | |
3370 | /* | |
3371 | * From here on, the constraint is dynamic. | |
3372 | * Either it was just allocated above, or it | |
3373 | * was allocated during a earlier invocation | |
3374 | * of this function | |
3375 | */ | |
3376 | ||
1c565833 PZ |
3377 | /* |
3378 | * state of sibling HT | |
3379 | */ | |
3380 | xlo = &excl_cntrs->states[tid ^ 1]; | |
3381 | ||
3382 | /* | |
3383 | * event requires exclusive counter access | |
3384 | * across HT threads | |
3385 | */ | |
3386 | is_excl = c->flags & PERF_X86_EVENT_EXCL; | |
3387 | if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { | |
3388 | event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; | |
3389 | if (!cpuc->n_excl++) | |
3390 | WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); | |
3391 | } | |
3392 | ||
e979121b MD |
3393 | /* |
3394 | * Modify static constraint with current dynamic | |
3395 | * state of thread | |
3396 | * | |
3397 | * EXCLUSIVE: sibling counter measuring exclusive event | |
3398 | * SHARED : sibling counter measuring non-exclusive event | |
3399 | * UNUSED : sibling counter unused | |
3400 | */ | |
c090cb70 | 3401 | w = c->weight; |
aaf932e8 | 3402 | for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { |
e979121b MD |
3403 | /* |
3404 | * exclusive event in sibling counter | |
3405 | * our corresponding counter cannot be used | |
3406 | * regardless of our event | |
3407 | */ | |
c090cb70 | 3408 | if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { |
aaf932e8 | 3409 | __clear_bit(i, c->idxmsk); |
c090cb70 PZ |
3410 | w--; |
3411 | continue; | |
3412 | } | |
e979121b MD |
3413 | /* |
3414 | * if measuring an exclusive event, sibling | |
3415 | * measuring non-exclusive, then counter cannot | |
3416 | * be used | |
3417 | */ | |
c090cb70 | 3418 | if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { |
aaf932e8 | 3419 | __clear_bit(i, c->idxmsk); |
c090cb70 PZ |
3420 | w--; |
3421 | continue; | |
3422 | } | |
e979121b MD |
3423 | } |
3424 | ||
e979121b MD |
3425 | /* |
3426 | * if we return an empty mask, then switch | |
3427 | * back to static empty constraint to avoid | |
3428 | * the cost of freeing later on | |
3429 | */ | |
c090cb70 | 3430 | if (!w) |
aaf932e8 | 3431 | c = &emptyconstraint; |
e979121b | 3432 | |
c090cb70 PZ |
3433 | c->weight = w; |
3434 | ||
aaf932e8 | 3435 | return c; |
e979121b MD |
3436 | } |
3437 | ||
3438 | static struct event_constraint * | |
3439 | intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
3440 | struct perf_event *event) | |
3441 | { | |
21d65555 | 3442 | struct event_constraint *c1, *c2; |
e979121b | 3443 | |
21d65555 | 3444 | c1 = cpuc->event_constraint[idx]; |
ebfb4988 | 3445 | |
e979121b MD |
3446 | /* |
3447 | * first time only | |
3448 | * - static constraint: no change across incremental scheduling calls | |
3449 | * - dynamic constraint: handled by intel_get_excl_constraints() | |
3450 | */ | |
a90738c2 | 3451 | c2 = __intel_get_event_constraints(cpuc, idx, event); |
109717de PZ |
3452 | if (c1) { |
3453 | WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); | |
a90738c2 SE |
3454 | bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); |
3455 | c1->weight = c2->weight; | |
3456 | c2 = c1; | |
3457 | } | |
e979121b MD |
3458 | |
3459 | if (cpuc->excl_cntrs) | |
a90738c2 | 3460 | return intel_get_excl_constraints(cpuc, event, idx, c2); |
e979121b | 3461 | |
a90738c2 | 3462 | return c2; |
e979121b MD |
3463 | } |
3464 | ||
3465 | static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, | |
3466 | struct perf_event *event) | |
3467 | { | |
3468 | struct hw_perf_event *hwc = &event->hw; | |
3469 | struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; | |
e979121b | 3470 | int tid = cpuc->excl_thread_id; |
1c565833 | 3471 | struct intel_excl_states *xl; |
e979121b MD |
3472 | |
3473 | /* | |
3474 | * nothing needed if in group validation mode | |
3475 | */ | |
3476 | if (cpuc->is_fake) | |
3477 | return; | |
3478 | ||
17186ccd | 3479 | if (WARN_ON_ONCE(!excl_cntrs)) |
e979121b MD |
3480 | return; |
3481 | ||
cc1790cf PZ |
3482 | if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { |
3483 | hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; | |
3484 | if (!--cpuc->n_excl) | |
3485 | WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); | |
3486 | } | |
e979121b MD |
3487 | |
3488 | /* | |
ba040653 PZ |
3489 | * If event was actually assigned, then mark the counter state as |
3490 | * unused now. | |
e979121b | 3491 | */ |
ba040653 PZ |
3492 | if (hwc->idx >= 0) { |
3493 | xl = &excl_cntrs->states[tid]; | |
3494 | ||
3495 | /* | |
3496 | * put_constraint may be called from x86_schedule_events() | |
3497 | * which already has the lock held so here make locking | |
3498 | * conditional. | |
3499 | */ | |
3500 | if (!xl->sched_started) | |
3501 | raw_spin_lock(&excl_cntrs->lock); | |
e979121b | 3502 | |
1c565833 | 3503 | xl->state[hwc->idx] = INTEL_EXCL_UNUSED; |
e979121b | 3504 | |
ba040653 PZ |
3505 | if (!xl->sched_started) |
3506 | raw_spin_unlock(&excl_cntrs->lock); | |
3507 | } | |
e979121b MD |
3508 | } |
3509 | ||
efc9f05d SE |
3510 | static void |
3511 | intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, | |
a7e3ed1e AK |
3512 | struct perf_event *event) |
3513 | { | |
efc9f05d | 3514 | struct hw_perf_event_extra *reg; |
a7e3ed1e | 3515 | |
efc9f05d SE |
3516 | reg = &event->hw.extra_reg; |
3517 | if (reg->idx != EXTRA_REG_NONE) | |
3518 | __intel_shared_reg_put_constraints(cpuc, reg); | |
b36817e8 SE |
3519 | |
3520 | reg = &event->hw.branch_reg; | |
3521 | if (reg->idx != EXTRA_REG_NONE) | |
3522 | __intel_shared_reg_put_constraints(cpuc, reg); | |
efc9f05d | 3523 | } |
a7e3ed1e | 3524 | |
efc9f05d SE |
3525 | static void intel_put_event_constraints(struct cpu_hw_events *cpuc, |
3526 | struct perf_event *event) | |
3527 | { | |
3528 | intel_put_shared_regs_event_constraints(cpuc, event); | |
e979121b MD |
3529 | |
3530 | /* | |
3531 | * is PMU has exclusive counter restrictions, then | |
3532 | * all events are subject to and must call the | |
3533 | * put_excl_constraints() routine | |
3534 | */ | |
b371b594 | 3535 | if (cpuc->excl_cntrs) |
e979121b | 3536 | intel_put_excl_constraints(cpuc, event); |
e979121b MD |
3537 | } |
3538 | ||
0780c927 | 3539 | static void intel_pebs_aliases_core2(struct perf_event *event) |
b4cdc5c2 | 3540 | { |
0780c927 | 3541 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { |
7639dae0 PZ |
3542 | /* |
3543 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
3544 | * (0x003c) so that we can use it with PEBS. | |
3545 | * | |
3546 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
3547 | * PEBS capable. However we can use INST_RETIRED.ANY_P | |
3548 | * (0x00c0), which is a PEBS capable event, to get the same | |
3549 | * count. | |
3550 | * | |
3551 | * INST_RETIRED.ANY_P counts the number of cycles that retires | |
3552 | * CNTMASK instructions. By setting CNTMASK to a value (16) | |
3553 | * larger than the maximum number of instructions that can be | |
3554 | * retired per cycle (4) and then inverting the condition, we | |
3555 | * count all cycles that retire 16 or less instructions, which | |
3556 | * is every cycle. | |
3557 | * | |
3558 | * Thereby we gain a PEBS capable cycle counter. | |
3559 | */ | |
f9b4eeb8 PZ |
3560 | u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); |
3561 | ||
0780c927 PZ |
3562 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); |
3563 | event->hw.config = alt_config; | |
3564 | } | |
3565 | } | |
3566 | ||
3567 | static void intel_pebs_aliases_snb(struct perf_event *event) | |
3568 | { | |
3569 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { | |
3570 | /* | |
3571 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
3572 | * (0x003c) so that we can use it with PEBS. | |
3573 | * | |
3574 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
3575 | * PEBS capable. However we can use UOPS_RETIRED.ALL | |
3576 | * (0x01c2), which is a PEBS capable event, to get the same | |
3577 | * count. | |
3578 | * | |
3579 | * UOPS_RETIRED.ALL counts the number of cycles that retires | |
3580 | * CNTMASK micro-ops. By setting CNTMASK to a value (16) | |
3581 | * larger than the maximum number of micro-ops that can be | |
3582 | * retired per cycle (4) and then inverting the condition, we | |
3583 | * count all cycles that retire 16 or less micro-ops, which | |
3584 | * is every cycle. | |
3585 | * | |
3586 | * Thereby we gain a PEBS capable cycle counter. | |
3587 | */ | |
3588 | u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); | |
7639dae0 PZ |
3589 | |
3590 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); | |
3591 | event->hw.config = alt_config; | |
3592 | } | |
0780c927 PZ |
3593 | } |
3594 | ||
72469764 AK |
3595 | static void intel_pebs_aliases_precdist(struct perf_event *event) |
3596 | { | |
3597 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { | |
3598 | /* | |
3599 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
3600 | * (0x003c) so that we can use it with PEBS. | |
3601 | * | |
3602 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
3603 | * PEBS capable. However we can use INST_RETIRED.PREC_DIST | |
3604 | * (0x01c0), which is a PEBS capable event, to get the same | |
3605 | * count. | |
3606 | * | |
3607 | * The PREC_DIST event has special support to minimize sample | |
3608 | * shadowing effects. One drawback is that it can be | |
3609 | * only programmed on counter 1, but that seems like an | |
3610 | * acceptable trade off. | |
3611 | */ | |
3612 | u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); | |
3613 | ||
3614 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); | |
3615 | event->hw.config = alt_config; | |
3616 | } | |
3617 | } | |
3618 | ||
3619 | static void intel_pebs_aliases_ivb(struct perf_event *event) | |
3620 | { | |
3621 | if (event->attr.precise_ip < 3) | |
3622 | return intel_pebs_aliases_snb(event); | |
3623 | return intel_pebs_aliases_precdist(event); | |
3624 | } | |
3625 | ||
3626 | static void intel_pebs_aliases_skl(struct perf_event *event) | |
3627 | { | |
3628 | if (event->attr.precise_ip < 3) | |
3629 | return intel_pebs_aliases_core2(event); | |
3630 | return intel_pebs_aliases_precdist(event); | |
3631 | } | |
3632 | ||
174afc3e | 3633 | static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) |
a7b58d21 | 3634 | { |
174afc3e | 3635 | unsigned long flags = x86_pmu.large_pebs_flags; |
a7b58d21 AK |
3636 | |
3637 | if (event->attr.use_clockid) | |
3638 | flags &= ~PERF_SAMPLE_TIME; | |
a47ba4d7 AK |
3639 | if (!event->attr.exclude_kernel) |
3640 | flags &= ~PERF_SAMPLE_REGS_USER; | |
9d5dcc93 | 3641 | if (event->attr.sample_regs_user & ~PEBS_GP_REGS) |
a47ba4d7 | 3642 | flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); |
a7b58d21 AK |
3643 | return flags; |
3644 | } | |
3645 | ||
ed6101bb JO |
3646 | static int intel_pmu_bts_config(struct perf_event *event) |
3647 | { | |
3648 | struct perf_event_attr *attr = &event->attr; | |
ed6101bb | 3649 | |
67266c10 | 3650 | if (unlikely(intel_pmu_has_bts(event))) { |
ed6101bb JO |
3651 | /* BTS is not supported by this architecture. */ |
3652 | if (!x86_pmu.bts_active) | |
3653 | return -EOPNOTSUPP; | |
3654 | ||
3655 | /* BTS is currently only allowed for user-mode. */ | |
3656 | if (!attr->exclude_kernel) | |
3657 | return -EOPNOTSUPP; | |
3658 | ||
472de49f JO |
3659 | /* BTS is not allowed for precise events. */ |
3660 | if (attr->precise_ip) | |
3661 | return -EOPNOTSUPP; | |
3662 | ||
ed6101bb JO |
3663 | /* disallow bts if conflicting events are present */ |
3664 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
3665 | return -EBUSY; | |
3666 | ||
3667 | event->destroy = hw_perf_lbr_event_destroy; | |
3668 | } | |
3669 | ||
3670 | return 0; | |
3671 | } | |
3672 | ||
3673 | static int core_pmu_hw_config(struct perf_event *event) | |
3674 | { | |
3675 | int ret = x86_pmu_hw_config(event); | |
3676 | ||
3677 | if (ret) | |
3678 | return ret; | |
3679 | ||
3680 | return intel_pmu_bts_config(event); | |
3681 | } | |
3682 | ||
1ab5f235 KL |
3683 | #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ |
3684 | ((x86_pmu.num_topdown_events - 1) << 8)) | |
3685 | ||
3686 | static bool is_available_metric_event(struct perf_event *event) | |
3687 | { | |
3688 | return is_metric_event(event) && | |
3689 | event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; | |
3690 | } | |
3691 | ||
61b985e3 KL |
3692 | static inline bool is_mem_loads_event(struct perf_event *event) |
3693 | { | |
3694 | return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); | |
3695 | } | |
3696 | ||
3697 | static inline bool is_mem_loads_aux_event(struct perf_event *event) | |
3698 | { | |
3699 | return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); | |
3700 | } | |
3701 | ||
f83d2f91 KL |
3702 | static inline bool require_mem_loads_aux_event(struct perf_event *event) |
3703 | { | |
3704 | if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) | |
3705 | return false; | |
3706 | ||
3707 | if (is_hybrid()) | |
3708 | return hybrid_pmu(event->pmu)->cpu_type == hybrid_big; | |
3709 | ||
3710 | return true; | |
3711 | } | |
3712 | ||
d0946a88 KL |
3713 | static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) |
3714 | { | |
3715 | union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); | |
3716 | ||
3717 | return test_bit(idx, (unsigned long *)&intel_cap->capabilities); | |
3718 | } | |
61b985e3 | 3719 | |
0780c927 PZ |
3720 | static int intel_pmu_hw_config(struct perf_event *event) |
3721 | { | |
3722 | int ret = x86_pmu_hw_config(event); | |
3723 | ||
ed6101bb JO |
3724 | if (ret) |
3725 | return ret; | |
3726 | ||
3727 | ret = intel_pmu_bts_config(event); | |
0780c927 PZ |
3728 | if (ret) |
3729 | return ret; | |
3730 | ||
851559e3 | 3731 | if (event->attr.precise_ip) { |
2dc0572f KL |
3732 | if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) |
3733 | return -EINVAL; | |
3734 | ||
c7a28657 | 3735 | if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { |
851559e3 | 3736 | event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; |
a7b58d21 | 3737 | if (!(event->attr.sample_type & |
afbef301 | 3738 | ~intel_pmu_large_pebs_flags(event))) { |
174afc3e | 3739 | event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; |
afbef301 KL |
3740 | event->attach_state |= PERF_ATTACH_SCHED_CB; |
3741 | } | |
3569c0d7 | 3742 | } |
851559e3 YZ |
3743 | if (x86_pmu.pebs_aliases) |
3744 | x86_pmu.pebs_aliases(event); | |
6cbc304f PZ |
3745 | |
3746 | if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) | |
3747 | event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; | |
851559e3 | 3748 | } |
7639dae0 | 3749 | |
a46a2300 | 3750 | if (needs_branch_stack(event)) { |
60ce0fbd SE |
3751 | ret = intel_pmu_setup_lbr_filter(event); |
3752 | if (ret) | |
3753 | return ret; | |
afbef301 | 3754 | event->attach_state |= PERF_ATTACH_SCHED_CB; |
48070342 AS |
3755 | |
3756 | /* | |
3757 | * BTS is set up earlier in this path, so don't account twice | |
3758 | */ | |
67266c10 | 3759 | if (!unlikely(intel_pmu_has_bts(event))) { |
48070342 AS |
3760 | /* disallow lbr if conflicting events are present */ |
3761 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
3762 | return -EBUSY; | |
3763 | ||
3764 | event->destroy = hw_perf_lbr_event_destroy; | |
3765 | } | |
60ce0fbd SE |
3766 | } |
3767 | ||
42880f72 AS |
3768 | if (event->attr.aux_output) { |
3769 | if (!event->attr.precise_ip) | |
3770 | return -EINVAL; | |
3771 | ||
3772 | event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; | |
3773 | } | |
3774 | ||
d9977c43 KL |
3775 | if ((event->attr.type == PERF_TYPE_HARDWARE) || |
3776 | (event->attr.type == PERF_TYPE_HW_CACHE)) | |
b4cdc5c2 PZ |
3777 | return 0; |
3778 | ||
7b2c05a1 KL |
3779 | /* |
3780 | * Config Topdown slots and metric events | |
3781 | * | |
3782 | * The slots event on Fixed Counter 3 can support sampling, | |
3783 | * which will be handled normally in x86_perf_event_update(). | |
3784 | * | |
3785 | * Metric events don't support sampling and require being paired | |
3786 | * with a slots event as group leader. When the slots event | |
3787 | * is used in a metrics group, it too cannot support sampling. | |
3788 | */ | |
d0946a88 | 3789 | if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { |
7b2c05a1 KL |
3790 | if (event->attr.config1 || event->attr.config2) |
3791 | return -EINVAL; | |
3792 | ||
3793 | /* | |
3794 | * The TopDown metrics events and slots event don't | |
3795 | * support any filters. | |
3796 | */ | |
3797 | if (event->attr.config & X86_ALL_EVENT_FLAGS) | |
3798 | return -EINVAL; | |
3799 | ||
1ab5f235 | 3800 | if (is_available_metric_event(event)) { |
7b2c05a1 KL |
3801 | struct perf_event *leader = event->group_leader; |
3802 | ||
3803 | /* The metric events don't support sampling. */ | |
3804 | if (is_sampling_event(event)) | |
3805 | return -EINVAL; | |
3806 | ||
3807 | /* The metric events require a slots group leader. */ | |
3808 | if (!is_slots_event(leader)) | |
3809 | return -EINVAL; | |
3810 | ||
3811 | /* | |
3812 | * The leader/SLOTS must not be a sampling event for | |
3813 | * metric use; hardware requires it starts at 0 when used | |
3814 | * in conjunction with MSR_PERF_METRICS. | |
3815 | */ | |
3816 | if (is_sampling_event(leader)) | |
3817 | return -EINVAL; | |
3818 | ||
3819 | event->event_caps |= PERF_EV_CAP_SIBLING; | |
3820 | /* | |
3821 | * Only once we have a METRICs sibling do we | |
3822 | * need TopDown magic. | |
3823 | */ | |
3824 | leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; | |
3825 | event->hw.flags |= PERF_X86_EVENT_TOPDOWN; | |
7b2c05a1 KL |
3826 | } |
3827 | } | |
3828 | ||
61b985e3 KL |
3829 | /* |
3830 | * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR | |
3831 | * doesn't function quite right. As a work-around it needs to always be | |
3832 | * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). | |
3833 | * The actual count of this second event is irrelevant it just needs | |
3834 | * to be active to make the first event function correctly. | |
3835 | * | |
3836 | * In a group, the auxiliary event must be in front of the load latency | |
3837 | * event. The rule is to simplify the implementation of the check. | |
3838 | * That's because perf cannot have a complete group at the moment. | |
3839 | */ | |
f83d2f91 | 3840 | if (require_mem_loads_aux_event(event) && |
61b985e3 KL |
3841 | (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && |
3842 | is_mem_loads_event(event)) { | |
3843 | struct perf_event *leader = event->group_leader; | |
3844 | struct perf_event *sibling = NULL; | |
3845 | ||
3846 | if (!is_mem_loads_aux_event(leader)) { | |
3847 | for_each_sibling_event(sibling, leader) { | |
3848 | if (is_mem_loads_aux_event(sibling)) | |
3849 | break; | |
3850 | } | |
3851 | if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) | |
3852 | return -ENODATA; | |
3853 | } | |
3854 | } | |
3855 | ||
b4cdc5c2 PZ |
3856 | if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) |
3857 | return 0; | |
3858 | ||
3859 | if (x86_pmu.version < 3) | |
3860 | return -EINVAL; | |
3861 | ||
da97e184 JFG |
3862 | ret = perf_allow_cpu(&event->attr); |
3863 | if (ret) | |
3864 | return ret; | |
b4cdc5c2 PZ |
3865 | |
3866 | event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; | |
3867 | ||
3868 | return 0; | |
3869 | } | |
3870 | ||
144d31e6 GN |
3871 | static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) |
3872 | { | |
89cbc767 | 3873 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
144d31e6 | 3874 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; |
fc4b8fca | 3875 | u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); |
144d31e6 GN |
3876 | |
3877 | arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; | |
fc4b8fca KL |
3878 | arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask; |
3879 | arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask; | |
9b545c04 AK |
3880 | if (x86_pmu.flags & PMU_FL_PEBS_ALL) |
3881 | arr[0].guest &= ~cpuc->pebs_enabled; | |
3882 | else | |
3883 | arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); | |
3884 | *nr = 1; | |
3885 | ||
3886 | if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { | |
3887 | /* | |
3888 | * If PMU counter has PEBS enabled it is not enough to | |
3889 | * disable counter on a guest entry since PEBS memory | |
3890 | * write can overshoot guest entry and corrupt guest | |
3891 | * memory. Disabling PEBS solves the problem. | |
3892 | * | |
3893 | * Don't do this if the CPU already enforces it. | |
3894 | */ | |
3895 | arr[1].msr = MSR_IA32_PEBS_ENABLE; | |
3896 | arr[1].host = cpuc->pebs_enabled; | |
3897 | arr[1].guest = 0; | |
3898 | *nr = 2; | |
3899 | } | |
144d31e6 | 3900 | |
144d31e6 GN |
3901 | return arr; |
3902 | } | |
3903 | ||
3904 | static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) | |
3905 | { | |
89cbc767 | 3906 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
144d31e6 GN |
3907 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; |
3908 | int idx; | |
3909 | ||
3910 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
3911 | struct perf_event *event = cpuc->events[idx]; | |
3912 | ||
3913 | arr[idx].msr = x86_pmu_config_addr(idx); | |
3914 | arr[idx].host = arr[idx].guest = 0; | |
3915 | ||
3916 | if (!test_bit(idx, cpuc->active_mask)) | |
3917 | continue; | |
3918 | ||
3919 | arr[idx].host = arr[idx].guest = | |
3920 | event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; | |
3921 | ||
3922 | if (event->attr.exclude_host) | |
3923 | arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
3924 | else if (event->attr.exclude_guest) | |
3925 | arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
3926 | } | |
3927 | ||
3928 | *nr = x86_pmu.num_counters; | |
3929 | return arr; | |
3930 | } | |
3931 | ||
3932 | static void core_pmu_enable_event(struct perf_event *event) | |
3933 | { | |
3934 | if (!event->attr.exclude_host) | |
3935 | x86_pmu_enable_event(event); | |
3936 | } | |
3937 | ||
3938 | static void core_pmu_enable_all(int added) | |
3939 | { | |
89cbc767 | 3940 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
144d31e6 GN |
3941 | int idx; |
3942 | ||
3943 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
3944 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; | |
3945 | ||
3946 | if (!test_bit(idx, cpuc->active_mask) || | |
3947 | cpuc->events[idx]->attr.exclude_host) | |
3948 | continue; | |
3949 | ||
3950 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); | |
3951 | } | |
3952 | } | |
3953 | ||
3a632cb2 AK |
3954 | static int hsw_hw_config(struct perf_event *event) |
3955 | { | |
3956 | int ret = intel_pmu_hw_config(event); | |
3957 | ||
3958 | if (ret) | |
3959 | return ret; | |
3960 | if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) | |
3961 | return 0; | |
3962 | event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); | |
3963 | ||
3964 | /* | |
3965 | * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with | |
3966 | * PEBS or in ANY thread mode. Since the results are non-sensical forbid | |
3967 | * this combination. | |
3968 | */ | |
3969 | if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && | |
3970 | ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || | |
3971 | event->attr.precise_ip > 0)) | |
3972 | return -EOPNOTSUPP; | |
3973 | ||
2dbf0116 AK |
3974 | if (event_is_checkpointed(event)) { |
3975 | /* | |
3976 | * Sampling of checkpointed events can cause situations where | |
3977 | * the CPU constantly aborts because of a overflow, which is | |
3978 | * then checkpointed back and ignored. Forbid checkpointing | |
3979 | * for sampling. | |
3980 | * | |
3981 | * But still allow a long sampling period, so that perf stat | |
3982 | * from KVM works. | |
3983 | */ | |
3984 | if (event->attr.sample_period > 0 && | |
3985 | event->attr.sample_period < 0x7fffffff) | |
3986 | return -EOPNOTSUPP; | |
3987 | } | |
3a632cb2 AK |
3988 | return 0; |
3989 | } | |
3990 | ||
dd0b06b5 KL |
3991 | static struct event_constraint counter0_constraint = |
3992 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); | |
3993 | ||
3a632cb2 AK |
3994 | static struct event_constraint counter2_constraint = |
3995 | EVENT_CONSTRAINT(0, 0x4, 0); | |
3996 | ||
60176089 KL |
3997 | static struct event_constraint fixed0_constraint = |
3998 | FIXED_EVENT_CONSTRAINT(0x00c0, 0); | |
3999 | ||
6daeb873 KL |
4000 | static struct event_constraint fixed0_counter0_constraint = |
4001 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); | |
4002 | ||
3a632cb2 | 4003 | static struct event_constraint * |
79cba822 SE |
4004 | hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
4005 | struct perf_event *event) | |
3a632cb2 | 4006 | { |
79cba822 SE |
4007 | struct event_constraint *c; |
4008 | ||
4009 | c = intel_get_event_constraints(cpuc, idx, event); | |
3a632cb2 AK |
4010 | |
4011 | /* Handle special quirk on in_tx_checkpointed only in counter 2 */ | |
4012 | if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { | |
4013 | if (c->idxmsk64 & (1U << 2)) | |
4014 | return &counter2_constraint; | |
4015 | return &emptyconstraint; | |
4016 | } | |
4017 | ||
4018 | return c; | |
4019 | } | |
4020 | ||
60176089 KL |
4021 | static struct event_constraint * |
4022 | icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
4023 | struct perf_event *event) | |
4024 | { | |
4025 | /* | |
4026 | * Fixed counter 0 has less skid. | |
4027 | * Force instruction:ppp in Fixed counter 0 | |
4028 | */ | |
4029 | if ((event->attr.precise_ip == 3) && | |
4030 | constraint_match(&fixed0_constraint, event->hw.config)) | |
4031 | return &fixed0_constraint; | |
4032 | ||
4033 | return hsw_get_event_constraints(cpuc, idx, event); | |
4034 | } | |
4035 | ||
61b985e3 KL |
4036 | static struct event_constraint * |
4037 | spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
4038 | struct perf_event *event) | |
4039 | { | |
4040 | struct event_constraint *c; | |
4041 | ||
4042 | c = icl_get_event_constraints(cpuc, idx, event); | |
4043 | ||
4044 | /* | |
4045 | * The :ppp indicates the Precise Distribution (PDist) facility, which | |
4046 | * is only supported on the GP counter 0. If a :ppp event which is not | |
4047 | * available on the GP counter 0, error out. | |
1d5c7880 | 4048 | * Exception: Instruction PDIR is only available on the fixed counter 0. |
61b985e3 | 4049 | */ |
1d5c7880 KL |
4050 | if ((event->attr.precise_ip == 3) && |
4051 | !constraint_match(&fixed0_constraint, event->hw.config)) { | |
61b985e3 KL |
4052 | if (c->idxmsk64 & BIT_ULL(0)) |
4053 | return &counter0_constraint; | |
4054 | ||
4055 | return &emptyconstraint; | |
4056 | } | |
4057 | ||
4058 | return c; | |
4059 | } | |
4060 | ||
dd0b06b5 KL |
4061 | static struct event_constraint * |
4062 | glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
4063 | struct perf_event *event) | |
4064 | { | |
4065 | struct event_constraint *c; | |
4066 | ||
4067 | /* :ppp means to do reduced skid PEBS which is PMC0 only. */ | |
4068 | if (event->attr.precise_ip == 3) | |
4069 | return &counter0_constraint; | |
4070 | ||
4071 | c = intel_get_event_constraints(cpuc, idx, event); | |
4072 | ||
4073 | return c; | |
4074 | } | |
4075 | ||
6daeb873 KL |
4076 | static struct event_constraint * |
4077 | tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
4078 | struct perf_event *event) | |
4079 | { | |
4080 | struct event_constraint *c; | |
4081 | ||
4082 | /* | |
4083 | * :ppp means to do reduced skid PEBS, | |
4084 | * which is available on PMC0 and fixed counter 0. | |
4085 | */ | |
4086 | if (event->attr.precise_ip == 3) { | |
4087 | /* Force instruction:ppp on PMC0 and Fixed counter 0 */ | |
4088 | if (constraint_match(&fixed0_constraint, event->hw.config)) | |
4089 | return &fixed0_counter0_constraint; | |
4090 | ||
4091 | return &counter0_constraint; | |
4092 | } | |
4093 | ||
4094 | c = intel_get_event_constraints(cpuc, idx, event); | |
4095 | ||
4096 | return c; | |
4097 | } | |
4098 | ||
400816f6 PZI |
4099 | static bool allow_tsx_force_abort = true; |
4100 | ||
4101 | static struct event_constraint * | |
4102 | tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
4103 | struct perf_event *event) | |
4104 | { | |
4105 | struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); | |
4106 | ||
4107 | /* | |
4108 | * Without TFA we must not use PMC3. | |
4109 | */ | |
21d65555 | 4110 | if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { |
400816f6 PZI |
4111 | c = dyn_constraint(cpuc, c, idx); |
4112 | c->idxmsk64 &= ~(1ULL << 3); | |
4113 | c->weight--; | |
4114 | } | |
4115 | ||
4116 | return c; | |
4117 | } | |
4118 | ||
f83d2f91 KL |
4119 | static struct event_constraint * |
4120 | adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, | |
4121 | struct perf_event *event) | |
4122 | { | |
4123 | struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); | |
4124 | ||
4125 | if (pmu->cpu_type == hybrid_big) | |
4126 | return spr_get_event_constraints(cpuc, idx, event); | |
4127 | else if (pmu->cpu_type == hybrid_small) | |
4128 | return tnt_get_event_constraints(cpuc, idx, event); | |
4129 | ||
4130 | WARN_ON(1); | |
4131 | return &emptyconstraint; | |
4132 | } | |
4133 | ||
4134 | static int adl_hw_config(struct perf_event *event) | |
4135 | { | |
4136 | struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); | |
4137 | ||
4138 | if (pmu->cpu_type == hybrid_big) | |
4139 | return hsw_hw_config(event); | |
4140 | else if (pmu->cpu_type == hybrid_small) | |
4141 | return intel_pmu_hw_config(event); | |
4142 | ||
4143 | WARN_ON(1); | |
4144 | return -EOPNOTSUPP; | |
4145 | } | |
4146 | ||
4147 | static u8 adl_get_hybrid_cpu_type(void) | |
4148 | { | |
4149 | return hybrid_big; | |
4150 | } | |
4151 | ||
294fe0f5 AK |
4152 | /* |
4153 | * Broadwell: | |
4154 | * | |
4155 | * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared | |
4156 | * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine | |
4157 | * the two to enforce a minimum period of 128 (the smallest value that has bits | |
4158 | * 0-5 cleared and >= 100). | |
4159 | * | |
4160 | * Because of how the code in x86_perf_event_set_period() works, the truncation | |
4161 | * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period | |
4162 | * to make up for the 'lost' events due to carrying the 'error' in period_left. | |
4163 | * | |
4164 | * Therefore the effective (average) period matches the requested period, | |
4165 | * despite coarser hardware granularity. | |
4166 | */ | |
f605cfca | 4167 | static u64 bdw_limit_period(struct perf_event *event, u64 left) |
294fe0f5 AK |
4168 | { |
4169 | if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == | |
4170 | X86_CONFIG(.event=0xc0, .umask=0x01)) { | |
4171 | if (left < 128) | |
4172 | left = 128; | |
e5ea9b54 | 4173 | left &= ~0x3fULL; |
294fe0f5 AK |
4174 | } |
4175 | return left; | |
4176 | } | |
4177 | ||
44d3bbb6 JH |
4178 | static u64 nhm_limit_period(struct perf_event *event, u64 left) |
4179 | { | |
4180 | return max(left, 32ULL); | |
4181 | } | |
4182 | ||
61b985e3 KL |
4183 | static u64 spr_limit_period(struct perf_event *event, u64 left) |
4184 | { | |
4185 | if (event->attr.precise_ip == 3) | |
4186 | return max(left, 128ULL); | |
4187 | ||
4188 | return left; | |
4189 | } | |
4190 | ||
641cc938 JO |
4191 | PMU_FORMAT_ATTR(event, "config:0-7" ); |
4192 | PMU_FORMAT_ATTR(umask, "config:8-15" ); | |
4193 | PMU_FORMAT_ATTR(edge, "config:18" ); | |
4194 | PMU_FORMAT_ATTR(pc, "config:19" ); | |
4195 | PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ | |
4196 | PMU_FORMAT_ATTR(inv, "config:23" ); | |
4197 | PMU_FORMAT_ATTR(cmask, "config:24-31" ); | |
3a632cb2 AK |
4198 | PMU_FORMAT_ATTR(in_tx, "config:32"); |
4199 | PMU_FORMAT_ATTR(in_tx_cp, "config:33"); | |
641cc938 JO |
4200 | |
4201 | static struct attribute *intel_arch_formats_attr[] = { | |
4202 | &format_attr_event.attr, | |
4203 | &format_attr_umask.attr, | |
4204 | &format_attr_edge.attr, | |
4205 | &format_attr_pc.attr, | |
4206 | &format_attr_inv.attr, | |
4207 | &format_attr_cmask.attr, | |
4208 | NULL, | |
4209 | }; | |
4210 | ||
0bf79d44 JO |
4211 | ssize_t intel_event_sysfs_show(char *page, u64 config) |
4212 | { | |
4213 | u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); | |
4214 | ||
4215 | return x86_event_sysfs_show(page, config, event); | |
4216 | } | |
4217 | ||
d01b1f96 | 4218 | static struct intel_shared_regs *allocate_shared_regs(int cpu) |
efc9f05d SE |
4219 | { |
4220 | struct intel_shared_regs *regs; | |
4221 | int i; | |
4222 | ||
4223 | regs = kzalloc_node(sizeof(struct intel_shared_regs), | |
4224 | GFP_KERNEL, cpu_to_node(cpu)); | |
4225 | if (regs) { | |
4226 | /* | |
4227 | * initialize the locks to keep lockdep happy | |
4228 | */ | |
4229 | for (i = 0; i < EXTRA_REG_MAX; i++) | |
4230 | raw_spin_lock_init(®s->regs[i].lock); | |
4231 | ||
4232 | regs->core_id = -1; | |
4233 | } | |
4234 | return regs; | |
4235 | } | |
4236 | ||
6f6539ca MD |
4237 | static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) |
4238 | { | |
4239 | struct intel_excl_cntrs *c; | |
6f6539ca MD |
4240 | |
4241 | c = kzalloc_node(sizeof(struct intel_excl_cntrs), | |
4242 | GFP_KERNEL, cpu_to_node(cpu)); | |
4243 | if (c) { | |
4244 | raw_spin_lock_init(&c->lock); | |
6f6539ca MD |
4245 | c->core_id = -1; |
4246 | } | |
4247 | return c; | |
4248 | } | |
4249 | ||
a7e3ed1e | 4250 | |
d01b1f96 PZI |
4251 | int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) |
4252 | { | |
c22497f5 KL |
4253 | cpuc->pebs_record_size = x86_pmu.pebs_record_size; |
4254 | ||
183af736 | 4255 | if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { |
6f6539ca MD |
4256 | cpuc->shared_regs = allocate_shared_regs(cpu); |
4257 | if (!cpuc->shared_regs) | |
dbc72b7a | 4258 | goto err; |
6f6539ca | 4259 | } |
69092624 | 4260 | |
400816f6 | 4261 | if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { |
6f6539ca MD |
4262 | size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); |
4263 | ||
d01b1f96 | 4264 | cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); |
6f6539ca | 4265 | if (!cpuc->constraint_list) |
dbc72b7a | 4266 | goto err_shared_regs; |
400816f6 | 4267 | } |
6f6539ca | 4268 | |
400816f6 | 4269 | if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { |
6f6539ca | 4270 | cpuc->excl_cntrs = allocate_excl_cntrs(cpu); |
dbc72b7a PZ |
4271 | if (!cpuc->excl_cntrs) |
4272 | goto err_constraint_list; | |
4273 | ||
6f6539ca MD |
4274 | cpuc->excl_thread_id = 0; |
4275 | } | |
a7e3ed1e | 4276 | |
95ca792c | 4277 | return 0; |
dbc72b7a PZ |
4278 | |
4279 | err_constraint_list: | |
4280 | kfree(cpuc->constraint_list); | |
4281 | cpuc->constraint_list = NULL; | |
4282 | ||
4283 | err_shared_regs: | |
4284 | kfree(cpuc->shared_regs); | |
4285 | cpuc->shared_regs = NULL; | |
4286 | ||
4287 | err: | |
95ca792c | 4288 | return -ENOMEM; |
a7e3ed1e AK |
4289 | } |
4290 | ||
d01b1f96 PZI |
4291 | static int intel_pmu_cpu_prepare(int cpu) |
4292 | { | |
4293 | return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); | |
4294 | } | |
4295 | ||
6089327f KL |
4296 | static void flip_smm_bit(void *data) |
4297 | { | |
4298 | unsigned long set = *(unsigned long *)data; | |
4299 | ||
4300 | if (set > 0) { | |
4301 | msr_set_bit(MSR_IA32_DEBUGCTLMSR, | |
4302 | DEBUGCTLMSR_FREEZE_IN_SMM_BIT); | |
4303 | } else { | |
4304 | msr_clear_bit(MSR_IA32_DEBUGCTLMSR, | |
4305 | DEBUGCTLMSR_FREEZE_IN_SMM_BIT); | |
4306 | } | |
4307 | } | |
4308 | ||
d9977c43 KL |
4309 | static bool init_hybrid_pmu(int cpu) |
4310 | { | |
4311 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
4312 | u8 cpu_type = get_this_hybrid_cpu_type(); | |
4313 | struct x86_hybrid_pmu *pmu = NULL; | |
4314 | int i; | |
4315 | ||
4316 | if (!cpu_type && x86_pmu.get_hybrid_cpu_type) | |
4317 | cpu_type = x86_pmu.get_hybrid_cpu_type(); | |
4318 | ||
4319 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { | |
4320 | if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { | |
4321 | pmu = &x86_pmu.hybrid_pmu[i]; | |
4322 | break; | |
4323 | } | |
4324 | } | |
4325 | if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { | |
4326 | cpuc->pmu = NULL; | |
4327 | return false; | |
4328 | } | |
4329 | ||
4330 | /* Only check and dump the PMU information for the first CPU */ | |
4331 | if (!cpumask_empty(&pmu->supported_cpus)) | |
4332 | goto end; | |
4333 | ||
4334 | if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) | |
4335 | return false; | |
4336 | ||
4337 | pr_info("%s PMU driver: ", pmu->name); | |
4338 | ||
4339 | if (pmu->intel_cap.pebs_output_pt_available) | |
4340 | pr_cont("PEBS-via-PT "); | |
4341 | ||
4342 | pr_cont("\n"); | |
4343 | ||
4344 | x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed, | |
4345 | pmu->intel_ctrl); | |
4346 | ||
4347 | end: | |
4348 | cpumask_set_cpu(cpu, &pmu->supported_cpus); | |
4349 | cpuc->pmu = &pmu->pmu; | |
4350 | ||
4351 | x86_pmu_update_cpu_context(&pmu->pmu, cpu); | |
4352 | ||
4353 | return true; | |
4354 | } | |
4355 | ||
74846d35 PZ |
4356 | static void intel_pmu_cpu_starting(int cpu) |
4357 | { | |
a7e3ed1e AK |
4358 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
4359 | int core_id = topology_core_id(cpu); | |
4360 | int i; | |
4361 | ||
d9977c43 KL |
4362 | if (is_hybrid() && !init_hybrid_pmu(cpu)) |
4363 | return; | |
4364 | ||
69092624 LM |
4365 | init_debug_store_on_cpu(cpu); |
4366 | /* | |
4367 | * Deal with CPUs that don't clear their LBRs on power-up. | |
4368 | */ | |
4369 | intel_pmu_lbr_reset(); | |
4370 | ||
b36817e8 SE |
4371 | cpuc->lbr_sel = NULL; |
4372 | ||
d7262457 PZ |
4373 | if (x86_pmu.flags & PMU_FL_TFA) { |
4374 | WARN_ON_ONCE(cpuc->tfa_shadow); | |
4375 | cpuc->tfa_shadow = ~0ULL; | |
4376 | intel_set_tfa(cpuc, false); | |
4377 | } | |
4378 | ||
4e949e9b KL |
4379 | if (x86_pmu.version > 1) |
4380 | flip_smm_bit(&x86_pmu.attr_freeze_on_smi); | |
6089327f | 4381 | |
d0946a88 KL |
4382 | /* |
4383 | * Disable perf metrics if any added CPU doesn't support it. | |
4384 | * | |
4385 | * Turn off the check for a hybrid architecture, because the | |
4386 | * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate | |
4387 | * the architecture features. The perf metrics is a model-specific | |
4388 | * feature for now. The corresponding bit should always be 0 on | |
4389 | * a hybrid platform, e.g., Alder Lake. | |
4390 | */ | |
4391 | if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { | |
80a5ce11 KL |
4392 | union perf_capabilities perf_cap; |
4393 | ||
4394 | rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); | |
4395 | if (!perf_cap.perf_metrics) { | |
4396 | x86_pmu.intel_cap.perf_metrics = 0; | |
4397 | x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); | |
4398 | } | |
4399 | } | |
4400 | ||
b36817e8 | 4401 | if (!cpuc->shared_regs) |
69092624 LM |
4402 | return; |
4403 | ||
9a5e3fb5 | 4404 | if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { |
06931e62 | 4405 | for_each_cpu(i, topology_sibling_cpumask(cpu)) { |
b36817e8 | 4406 | struct intel_shared_regs *pc; |
a7e3ed1e | 4407 | |
b36817e8 SE |
4408 | pc = per_cpu(cpu_hw_events, i).shared_regs; |
4409 | if (pc && pc->core_id == core_id) { | |
8f04b853 | 4410 | cpuc->kfree_on_online[0] = cpuc->shared_regs; |
b36817e8 SE |
4411 | cpuc->shared_regs = pc; |
4412 | break; | |
4413 | } | |
a7e3ed1e | 4414 | } |
b36817e8 SE |
4415 | cpuc->shared_regs->core_id = core_id; |
4416 | cpuc->shared_regs->refcnt++; | |
a7e3ed1e AK |
4417 | } |
4418 | ||
b36817e8 SE |
4419 | if (x86_pmu.lbr_sel_map) |
4420 | cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; | |
6f6539ca MD |
4421 | |
4422 | if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { | |
06931e62 | 4423 | for_each_cpu(i, topology_sibling_cpumask(cpu)) { |
4e71de79 | 4424 | struct cpu_hw_events *sibling; |
6f6539ca MD |
4425 | struct intel_excl_cntrs *c; |
4426 | ||
4e71de79 ZC |
4427 | sibling = &per_cpu(cpu_hw_events, i); |
4428 | c = sibling->excl_cntrs; | |
6f6539ca MD |
4429 | if (c && c->core_id == core_id) { |
4430 | cpuc->kfree_on_online[1] = cpuc->excl_cntrs; | |
4431 | cpuc->excl_cntrs = c; | |
4e71de79 ZC |
4432 | if (!sibling->excl_thread_id) |
4433 | cpuc->excl_thread_id = 1; | |
6f6539ca MD |
4434 | break; |
4435 | } | |
4436 | } | |
4437 | cpuc->excl_cntrs->core_id = core_id; | |
4438 | cpuc->excl_cntrs->refcnt++; | |
4439 | } | |
74846d35 PZ |
4440 | } |
4441 | ||
d01b1f96 | 4442 | static void free_excl_cntrs(struct cpu_hw_events *cpuc) |
74846d35 | 4443 | { |
6f6539ca | 4444 | struct intel_excl_cntrs *c; |
a7e3ed1e | 4445 | |
6f6539ca MD |
4446 | c = cpuc->excl_cntrs; |
4447 | if (c) { | |
4448 | if (c->core_id == -1 || --c->refcnt == 0) | |
4449 | kfree(c); | |
4450 | cpuc->excl_cntrs = NULL; | |
6f6539ca | 4451 | } |
400816f6 PZI |
4452 | |
4453 | kfree(cpuc->constraint_list); | |
4454 | cpuc->constraint_list = NULL; | |
b37609c3 | 4455 | } |
a7e3ed1e | 4456 | |
b37609c3 | 4457 | static void intel_pmu_cpu_dying(int cpu) |
602cae04 PZ |
4458 | { |
4459 | fini_debug_store_on_cpu(cpu); | |
602cae04 PZ |
4460 | } |
4461 | ||
d01b1f96 | 4462 | void intel_cpuc_finish(struct cpu_hw_events *cpuc) |
b37609c3 | 4463 | { |
b37609c3 SE |
4464 | struct intel_shared_regs *pc; |
4465 | ||
4466 | pc = cpuc->shared_regs; | |
4467 | if (pc) { | |
4468 | if (pc->core_id == -1 || --pc->refcnt == 0) | |
4469 | kfree(pc); | |
4470 | cpuc->shared_regs = NULL; | |
e979121b MD |
4471 | } |
4472 | ||
d01b1f96 PZI |
4473 | free_excl_cntrs(cpuc); |
4474 | } | |
4475 | ||
4476 | static void intel_pmu_cpu_dead(int cpu) | |
4477 | { | |
d9977c43 KL |
4478 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
4479 | ||
4480 | intel_cpuc_finish(cpuc); | |
4481 | ||
4482 | if (is_hybrid() && cpuc->pmu) | |
4483 | cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); | |
74846d35 PZ |
4484 | } |
4485 | ||
9c964efa YZ |
4486 | static void intel_pmu_sched_task(struct perf_event_context *ctx, |
4487 | bool sched_in) | |
4488 | { | |
df6c3db8 JO |
4489 | intel_pmu_pebs_sched_task(ctx, sched_in); |
4490 | intel_pmu_lbr_sched_task(ctx, sched_in); | |
9c964efa YZ |
4491 | } |
4492 | ||
c2b98a86 AB |
4493 | static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, |
4494 | struct perf_event_context *next) | |
4495 | { | |
4496 | intel_pmu_lbr_swap_task_ctx(prev, next); | |
4497 | } | |
4498 | ||
81ec3f3c JO |
4499 | static int intel_pmu_check_period(struct perf_event *event, u64 value) |
4500 | { | |
4501 | return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; | |
4502 | } | |
4503 | ||
42880f72 AS |
4504 | static int intel_pmu_aux_output_match(struct perf_event *event) |
4505 | { | |
4506 | if (!x86_pmu.intel_cap.pebs_output_pt_available) | |
4507 | return 0; | |
4508 | ||
4509 | return is_intel_pt_event(event); | |
4510 | } | |
4511 | ||
f83d2f91 KL |
4512 | static int intel_pmu_filter_match(struct perf_event *event) |
4513 | { | |
4514 | struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); | |
4515 | unsigned int cpu = smp_processor_id(); | |
4516 | ||
4517 | return cpumask_test_cpu(cpu, &pmu->supported_cpus); | |
4518 | } | |
4519 | ||
641cc938 JO |
4520 | PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); |
4521 | ||
a63fcab4 SE |
4522 | PMU_FORMAT_ATTR(ldlat, "config1:0-15"); |
4523 | ||
d0dc8494 AK |
4524 | PMU_FORMAT_ATTR(frontend, "config1:0-23"); |
4525 | ||
641cc938 JO |
4526 | static struct attribute *intel_arch3_formats_attr[] = { |
4527 | &format_attr_event.attr, | |
4528 | &format_attr_umask.attr, | |
4529 | &format_attr_edge.attr, | |
4530 | &format_attr_pc.attr, | |
4531 | &format_attr_any.attr, | |
4532 | &format_attr_inv.attr, | |
4533 | &format_attr_cmask.attr, | |
a5df70c3 AK |
4534 | NULL, |
4535 | }; | |
4536 | ||
4537 | static struct attribute *hsw_format_attr[] = { | |
3a632cb2 AK |
4538 | &format_attr_in_tx.attr, |
4539 | &format_attr_in_tx_cp.attr, | |
a5df70c3 AK |
4540 | &format_attr_offcore_rsp.attr, |
4541 | &format_attr_ldlat.attr, | |
4542 | NULL | |
4543 | }; | |
641cc938 | 4544 | |
a5df70c3 AK |
4545 | static struct attribute *nhm_format_attr[] = { |
4546 | &format_attr_offcore_rsp.attr, | |
4547 | &format_attr_ldlat.attr, | |
4548 | NULL | |
4549 | }; | |
4550 | ||
4551 | static struct attribute *slm_format_attr[] = { | |
4552 | &format_attr_offcore_rsp.attr, | |
4553 | NULL | |
641cc938 JO |
4554 | }; |
4555 | ||
d0dc8494 AK |
4556 | static struct attribute *skl_format_attr[] = { |
4557 | &format_attr_frontend.attr, | |
4558 | NULL, | |
4559 | }; | |
4560 | ||
3b6e0421 JO |
4561 | static __initconst const struct x86_pmu core_pmu = { |
4562 | .name = "core", | |
4563 | .handle_irq = x86_pmu_handle_irq, | |
4564 | .disable_all = x86_pmu_disable_all, | |
4565 | .enable_all = core_pmu_enable_all, | |
4566 | .enable = core_pmu_enable_event, | |
4567 | .disable = x86_pmu_disable_event, | |
ed6101bb | 4568 | .hw_config = core_pmu_hw_config, |
3b6e0421 JO |
4569 | .schedule_events = x86_schedule_events, |
4570 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, | |
4571 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
4572 | .event_map = intel_pmu_event_map, | |
4573 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), | |
4574 | .apic = 1, | |
174afc3e | 4575 | .large_pebs_flags = LARGE_PEBS_FLAGS, |
a7b58d21 | 4576 | |
3b6e0421 JO |
4577 | /* |
4578 | * Intel PMCs cannot be accessed sanely above 32-bit width, | |
4579 | * so we install an artificial 1<<31 period regardless of | |
4580 | * the generic event period: | |
4581 | */ | |
4582 | .max_period = (1ULL<<31) - 1, | |
4583 | .get_event_constraints = intel_get_event_constraints, | |
4584 | .put_event_constraints = intel_put_event_constraints, | |
4585 | .event_constraints = intel_core_event_constraints, | |
4586 | .guest_get_msrs = core_guest_get_msrs, | |
4587 | .format_attrs = intel_arch_formats_attr, | |
4588 | .events_sysfs_show = intel_event_sysfs_show, | |
4589 | ||
4590 | /* | |
4591 | * Virtual (or funny metal) CPU can define x86_pmu.extra_regs | |
4592 | * together with PMU version 1 and thus be using core_pmu with | |
4593 | * shared_regs. We need following callbacks here to allocate | |
4594 | * it properly. | |
4595 | */ | |
4596 | .cpu_prepare = intel_pmu_cpu_prepare, | |
4597 | .cpu_starting = intel_pmu_cpu_starting, | |
4598 | .cpu_dying = intel_pmu_cpu_dying, | |
602cae04 | 4599 | .cpu_dead = intel_pmu_cpu_dead, |
81ec3f3c JO |
4600 | |
4601 | .check_period = intel_pmu_check_period, | |
9f354a72 KL |
4602 | |
4603 | .lbr_reset = intel_pmu_lbr_reset_64, | |
c301b1d8 | 4604 | .lbr_read = intel_pmu_lbr_read_64, |
799571bf KL |
4605 | .lbr_save = intel_pmu_lbr_save, |
4606 | .lbr_restore = intel_pmu_lbr_restore, | |
3b6e0421 JO |
4607 | }; |
4608 | ||
caaa8be3 | 4609 | static __initconst const struct x86_pmu intel_pmu = { |
f22f54f4 PZ |
4610 | .name = "Intel", |
4611 | .handle_irq = intel_pmu_handle_irq, | |
4612 | .disable_all = intel_pmu_disable_all, | |
4613 | .enable_all = intel_pmu_enable_all, | |
4614 | .enable = intel_pmu_enable_event, | |
4615 | .disable = intel_pmu_disable_event, | |
68f7082f PZ |
4616 | .add = intel_pmu_add_event, |
4617 | .del = intel_pmu_del_event, | |
ceb90d9e | 4618 | .read = intel_pmu_read_event, |
b4cdc5c2 | 4619 | .hw_config = intel_pmu_hw_config, |
a072738e | 4620 | .schedule_events = x86_schedule_events, |
f22f54f4 PZ |
4621 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
4622 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
4623 | .event_map = intel_pmu_event_map, | |
f22f54f4 PZ |
4624 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
4625 | .apic = 1, | |
174afc3e | 4626 | .large_pebs_flags = LARGE_PEBS_FLAGS, |
f22f54f4 PZ |
4627 | /* |
4628 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
4629 | * so we install an artificial 1<<31 period regardless of | |
4630 | * the generic event period: | |
4631 | */ | |
4632 | .max_period = (1ULL << 31) - 1, | |
3f6da390 | 4633 | .get_event_constraints = intel_get_event_constraints, |
a7e3ed1e | 4634 | .put_event_constraints = intel_put_event_constraints, |
0780c927 | 4635 | .pebs_aliases = intel_pebs_aliases_core2, |
3f6da390 | 4636 | |
641cc938 | 4637 | .format_attrs = intel_arch3_formats_attr, |
0bf79d44 | 4638 | .events_sysfs_show = intel_event_sysfs_show, |
641cc938 | 4639 | |
a7e3ed1e | 4640 | .cpu_prepare = intel_pmu_cpu_prepare, |
74846d35 PZ |
4641 | .cpu_starting = intel_pmu_cpu_starting, |
4642 | .cpu_dying = intel_pmu_cpu_dying, | |
602cae04 PZ |
4643 | .cpu_dead = intel_pmu_cpu_dead, |
4644 | ||
144d31e6 | 4645 | .guest_get_msrs = intel_guest_get_msrs, |
9c964efa | 4646 | .sched_task = intel_pmu_sched_task, |
c2b98a86 | 4647 | .swap_task_ctx = intel_pmu_swap_task_ctx, |
81ec3f3c JO |
4648 | |
4649 | .check_period = intel_pmu_check_period, | |
42880f72 AS |
4650 | |
4651 | .aux_output_match = intel_pmu_aux_output_match, | |
9f354a72 KL |
4652 | |
4653 | .lbr_reset = intel_pmu_lbr_reset_64, | |
c301b1d8 | 4654 | .lbr_read = intel_pmu_lbr_read_64, |
799571bf KL |
4655 | .lbr_save = intel_pmu_lbr_save, |
4656 | .lbr_restore = intel_pmu_lbr_restore, | |
e07c9e66 PZ |
4657 | |
4658 | /* | |
4659 | * SMM has access to all 4 rings and while traditionally SMM code only | |
4660 | * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. | |
4661 | * | |
4662 | * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction | |
4663 | * between SMM or not, this results in what should be pure userspace | |
4664 | * counters including SMM data. | |
4665 | * | |
4666 | * This is a clear privilege issue, therefore globally disable | |
4667 | * counting SMM by default. | |
4668 | */ | |
4669 | .attr_freeze_on_smi = 1, | |
f22f54f4 PZ |
4670 | }; |
4671 | ||
c1d6f42f | 4672 | static __init void intel_clovertown_quirk(void) |
3c44780b PZ |
4673 | { |
4674 | /* | |
4675 | * PEBS is unreliable due to: | |
4676 | * | |
4677 | * AJ67 - PEBS may experience CPL leaks | |
4678 | * AJ68 - PEBS PMI may be delayed by one event | |
4679 | * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] | |
4680 | * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS | |
4681 | * | |
4682 | * AJ67 could be worked around by restricting the OS/USR flags. | |
4683 | * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. | |
4684 | * | |
4685 | * AJ106 could possibly be worked around by not allowing LBR | |
4686 | * usage from PEBS, including the fixup. | |
4687 | * AJ68 could possibly be worked around by always programming | |
ec75a716 | 4688 | * a pebs_event_reset[0] value and coping with the lost events. |
3c44780b PZ |
4689 | * |
4690 | * But taken together it might just make sense to not enable PEBS on | |
4691 | * these chips. | |
4692 | */ | |
c767a54b | 4693 | pr_warn("PEBS disabled due to CPU errata\n"); |
3c44780b PZ |
4694 | x86_pmu.pebs = 0; |
4695 | x86_pmu.pebs_constraints = NULL; | |
4696 | } | |
4697 | ||
9b545c04 | 4698 | static const struct x86_cpu_desc isolation_ucodes[] = { |
c66f78a6 | 4699 | INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), |
af239c44 | 4700 | INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), |
5e741407 | 4701 | INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), |
9b545c04 AK |
4702 | INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), |
4703 | INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), | |
c66f78a6 | 4704 | INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), |
5e741407 | 4705 | INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), |
5ebb34ed PZ |
4706 | INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), |
4707 | INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), | |
4708 | INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), | |
4709 | INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), | |
4b2f1e59 | 4710 | INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014), |
9b545c04 AK |
4711 | INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), |
4712 | INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), | |
b3c3361f JM |
4713 | INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000), |
4714 | INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000), | |
4715 | INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000), | |
af239c44 | 4716 | INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), |
c66f78a6 PZ |
4717 | INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), |
4718 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), | |
af239c44 PZ |
4719 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), |
4720 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), | |
4721 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), | |
4722 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), | |
c66f78a6 PZ |
4723 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), |
4724 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), | |
4725 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), | |
4726 | INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), | |
9b545c04 AK |
4727 | {} |
4728 | }; | |
4729 | ||
4730 | static void intel_check_pebs_isolation(void) | |
4731 | { | |
4732 | x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); | |
4733 | } | |
4734 | ||
4735 | static __init void intel_pebs_isolation_quirk(void) | |
4736 | { | |
4737 | WARN_ON_ONCE(x86_pmu.check_microcode); | |
4738 | x86_pmu.check_microcode = intel_check_pebs_isolation; | |
4739 | intel_check_pebs_isolation(); | |
4740 | } | |
4741 | ||
a96fff8d KL |
4742 | static const struct x86_cpu_desc pebs_ucodes[] = { |
4743 | INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), | |
4744 | INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), | |
4745 | INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), | |
4746 | {} | |
4747 | }; | |
c93dc84c | 4748 | |
a96fff8d KL |
4749 | static bool intel_snb_pebs_broken(void) |
4750 | { | |
4751 | return !x86_cpu_has_min_microcode_rev(pebs_ucodes); | |
c93dc84c PZ |
4752 | } |
4753 | ||
4754 | static void intel_snb_check_microcode(void) | |
4755 | { | |
a96fff8d | 4756 | if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) |
c93dc84c PZ |
4757 | return; |
4758 | ||
4759 | /* | |
4760 | * Serialized by the microcode lock.. | |
4761 | */ | |
4762 | if (x86_pmu.pebs_broken) { | |
4763 | pr_info("PEBS enabled due to microcode update\n"); | |
4764 | x86_pmu.pebs_broken = 0; | |
4765 | } else { | |
4766 | pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); | |
4767 | x86_pmu.pebs_broken = 1; | |
4768 | } | |
4769 | } | |
4770 | ||
19fc9ddd DCC |
4771 | static bool is_lbr_from(unsigned long msr) |
4772 | { | |
4773 | unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; | |
4774 | ||
4775 | return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; | |
4776 | } | |
4777 | ||
338b522c KL |
4778 | /* |
4779 | * Under certain circumstances, access certain MSR may cause #GP. | |
4780 | * The function tests if the input MSR can be safely accessed. | |
4781 | */ | |
4782 | static bool check_msr(unsigned long msr, u64 mask) | |
4783 | { | |
4784 | u64 val_old, val_new, val_tmp; | |
4785 | ||
d0e1a507 JO |
4786 | /* |
4787 | * Disable the check for real HW, so we don't | |
d9f6e12f | 4788 | * mess with potentially enabled registers: |
d0e1a507 | 4789 | */ |
5ea3f6fb | 4790 | if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) |
d0e1a507 JO |
4791 | return true; |
4792 | ||
338b522c KL |
4793 | /* |
4794 | * Read the current value, change it and read it back to see if it | |
4795 | * matches, this is needed to detect certain hardware emulators | |
4796 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4797 | */ | |
4798 | if (rdmsrl_safe(msr, &val_old)) | |
4799 | return false; | |
4800 | ||
4801 | /* | |
4802 | * Only change the bits which can be updated by wrmsrl. | |
4803 | */ | |
4804 | val_tmp = val_old ^ mask; | |
19fc9ddd DCC |
4805 | |
4806 | if (is_lbr_from(msr)) | |
4807 | val_tmp = lbr_from_signext_quirk_wr(val_tmp); | |
4808 | ||
338b522c KL |
4809 | if (wrmsrl_safe(msr, val_tmp) || |
4810 | rdmsrl_safe(msr, &val_new)) | |
4811 | return false; | |
4812 | ||
19fc9ddd DCC |
4813 | /* |
4814 | * Quirk only affects validation in wrmsr(), so wrmsrl()'s value | |
4815 | * should equal rdmsrl()'s even with the quirk. | |
4816 | */ | |
338b522c KL |
4817 | if (val_new != val_tmp) |
4818 | return false; | |
4819 | ||
19fc9ddd DCC |
4820 | if (is_lbr_from(msr)) |
4821 | val_old = lbr_from_signext_quirk_wr(val_old); | |
4822 | ||
338b522c KL |
4823 | /* Here it's sure that the MSR can be safely accessed. |
4824 | * Restore the old value and return. | |
4825 | */ | |
4826 | wrmsrl(msr, val_old); | |
4827 | ||
4828 | return true; | |
4829 | } | |
4830 | ||
c1d6f42f | 4831 | static __init void intel_sandybridge_quirk(void) |
6a600a8b | 4832 | { |
c93dc84c | 4833 | x86_pmu.check_microcode = intel_snb_check_microcode; |
1ba143a5 | 4834 | cpus_read_lock(); |
c93dc84c | 4835 | intel_snb_check_microcode(); |
1ba143a5 | 4836 | cpus_read_unlock(); |
6a600a8b PZ |
4837 | } |
4838 | ||
c1d6f42f PZ |
4839 | static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { |
4840 | { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, | |
4841 | { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, | |
4842 | { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, | |
4843 | { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, | |
4844 | { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, | |
4845 | { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, | |
4846 | { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, | |
ffb871bc GN |
4847 | }; |
4848 | ||
c1d6f42f PZ |
4849 | static __init void intel_arch_events_quirk(void) |
4850 | { | |
4851 | int bit; | |
4852 | ||
d9f6e12f | 4853 | /* disable event that reported as not present by cpuid */ |
c1d6f42f PZ |
4854 | for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { |
4855 | intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; | |
c767a54b JP |
4856 | pr_warn("CPUID marked event: \'%s\' unavailable\n", |
4857 | intel_arch_events_map[bit].name); | |
c1d6f42f PZ |
4858 | } |
4859 | } | |
4860 | ||
4861 | static __init void intel_nehalem_quirk(void) | |
4862 | { | |
4863 | union cpuid10_ebx ebx; | |
4864 | ||
4865 | ebx.full = x86_pmu.events_maskl; | |
4866 | if (ebx.split.no_branch_misses_retired) { | |
4867 | /* | |
4868 | * Erratum AAJ80 detected, we work it around by using | |
4869 | * the BR_MISP_EXEC.ANY event. This will over-count | |
4870 | * branch-misses, but it's still much better than the | |
4871 | * architectural event which is often completely bogus: | |
4872 | */ | |
4873 | intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; | |
4874 | ebx.split.no_branch_misses_retired = 0; | |
4875 | x86_pmu.events_maskl = ebx.full; | |
c767a54b | 4876 | pr_info("CPU erratum AAJ80 worked around\n"); |
c1d6f42f PZ |
4877 | } |
4878 | } | |
4879 | ||
93fcf72c MD |
4880 | /* |
4881 | * enable software workaround for errata: | |
4882 | * SNB: BJ122 | |
4883 | * IVB: BV98 | |
4884 | * HSW: HSD29 | |
4885 | * | |
4886 | * Only needed when HT is enabled. However detecting | |
b37609c3 SE |
4887 | * if HT is enabled is difficult (model specific). So instead, |
4888 | * we enable the workaround in the early boot, and verify if | |
4889 | * it is needed in a later initcall phase once we have valid | |
4890 | * topology information to check if HT is actually enabled | |
93fcf72c MD |
4891 | */ |
4892 | static __init void intel_ht_bug(void) | |
4893 | { | |
b37609c3 | 4894 | x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; |
93fcf72c | 4895 | |
93fcf72c | 4896 | x86_pmu.start_scheduling = intel_start_scheduling; |
0c41e756 | 4897 | x86_pmu.commit_scheduling = intel_commit_scheduling; |
93fcf72c | 4898 | x86_pmu.stop_scheduling = intel_stop_scheduling; |
93fcf72c MD |
4899 | } |
4900 | ||
7f2ee91f IM |
4901 | EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); |
4902 | EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") | |
f9134f36 | 4903 | |
4b2c4f1f | 4904 | /* Haswell special events */ |
7f2ee91f IM |
4905 | EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); |
4906 | EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); | |
4907 | EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); | |
4908 | EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); | |
4909 | EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); | |
4910 | EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); | |
4911 | EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); | |
4912 | EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); | |
4913 | EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); | |
4914 | EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); | |
4915 | EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); | |
4916 | EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); | |
4b2c4f1f | 4917 | |
f9134f36 | 4918 | static struct attribute *hsw_events_attrs[] = { |
58ba4d5a AK |
4919 | EVENT_PTR(td_slots_issued), |
4920 | EVENT_PTR(td_slots_retired), | |
4921 | EVENT_PTR(td_fetch_bubbles), | |
4922 | EVENT_PTR(td_total_slots), | |
4923 | EVENT_PTR(td_total_slots_scale), | |
4924 | EVENT_PTR(td_recovery_bubbles), | |
4925 | EVENT_PTR(td_recovery_bubbles_scale), | |
4926 | NULL | |
4927 | }; | |
4928 | ||
d4ae5529 JO |
4929 | static struct attribute *hsw_mem_events_attrs[] = { |
4930 | EVENT_PTR(mem_ld_hsw), | |
4931 | EVENT_PTR(mem_st_hsw), | |
4932 | NULL, | |
4933 | }; | |
4934 | ||
58ba4d5a | 4935 | static struct attribute *hsw_tsx_events_attrs[] = { |
4b2c4f1f AK |
4936 | EVENT_PTR(tx_start), |
4937 | EVENT_PTR(tx_commit), | |
4938 | EVENT_PTR(tx_abort), | |
4939 | EVENT_PTR(tx_capacity), | |
4940 | EVENT_PTR(tx_conflict), | |
4941 | EVENT_PTR(el_start), | |
4942 | EVENT_PTR(el_commit), | |
4943 | EVENT_PTR(el_abort), | |
4944 | EVENT_PTR(el_capacity), | |
4945 | EVENT_PTR(el_conflict), | |
4946 | EVENT_PTR(cycles_t), | |
4947 | EVENT_PTR(cycles_ct), | |
f9134f36 AK |
4948 | NULL |
4949 | }; | |
4950 | ||
60176089 KL |
4951 | EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); |
4952 | EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); | |
4953 | EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); | |
4954 | EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); | |
4955 | ||
4956 | static struct attribute *icl_events_attrs[] = { | |
4957 | EVENT_PTR(mem_ld_hsw), | |
4958 | EVENT_PTR(mem_st_hsw), | |
4959 | NULL, | |
4960 | }; | |
4961 | ||
59a854e2 KL |
4962 | static struct attribute *icl_td_events_attrs[] = { |
4963 | EVENT_PTR(slots), | |
4964 | EVENT_PTR(td_retiring), | |
4965 | EVENT_PTR(td_bad_spec), | |
4966 | EVENT_PTR(td_fe_bound), | |
4967 | EVENT_PTR(td_be_bound), | |
4968 | NULL, | |
4969 | }; | |
4970 | ||
60176089 KL |
4971 | static struct attribute *icl_tsx_events_attrs[] = { |
4972 | EVENT_PTR(tx_start), | |
4973 | EVENT_PTR(tx_abort), | |
4974 | EVENT_PTR(tx_commit), | |
4975 | EVENT_PTR(tx_capacity_read), | |
4976 | EVENT_PTR(tx_capacity_write), | |
4977 | EVENT_PTR(tx_conflict), | |
4978 | EVENT_PTR(el_start), | |
4979 | EVENT_PTR(el_abort), | |
4980 | EVENT_PTR(el_commit), | |
4981 | EVENT_PTR(el_capacity_read), | |
4982 | EVENT_PTR(el_capacity_write), | |
4983 | EVENT_PTR(el_conflict), | |
4984 | EVENT_PTR(cycles_t), | |
4985 | EVENT_PTR(cycles_ct), | |
4986 | NULL, | |
4987 | }; | |
4988 | ||
61b985e3 KL |
4989 | |
4990 | EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); | |
4991 | EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); | |
4992 | ||
4993 | static struct attribute *spr_events_attrs[] = { | |
4994 | EVENT_PTR(mem_ld_hsw), | |
4995 | EVENT_PTR(mem_st_spr), | |
4996 | EVENT_PTR(mem_ld_aux), | |
4997 | NULL, | |
4998 | }; | |
4999 | ||
5000 | static struct attribute *spr_td_events_attrs[] = { | |
5001 | EVENT_PTR(slots), | |
5002 | EVENT_PTR(td_retiring), | |
5003 | EVENT_PTR(td_bad_spec), | |
5004 | EVENT_PTR(td_fe_bound), | |
5005 | EVENT_PTR(td_be_bound), | |
5006 | EVENT_PTR(td_heavy_ops), | |
5007 | EVENT_PTR(td_br_mispredict), | |
5008 | EVENT_PTR(td_fetch_lat), | |
5009 | EVENT_PTR(td_mem_bound), | |
5010 | NULL, | |
5011 | }; | |
5012 | ||
5013 | static struct attribute *spr_tsx_events_attrs[] = { | |
5014 | EVENT_PTR(tx_start), | |
5015 | EVENT_PTR(tx_abort), | |
5016 | EVENT_PTR(tx_commit), | |
5017 | EVENT_PTR(tx_capacity_read), | |
5018 | EVENT_PTR(tx_capacity_write), | |
5019 | EVENT_PTR(tx_conflict), | |
5020 | EVENT_PTR(cycles_t), | |
5021 | EVENT_PTR(cycles_ct), | |
5022 | NULL, | |
5023 | }; | |
5024 | ||
6089327f KL |
5025 | static ssize_t freeze_on_smi_show(struct device *cdev, |
5026 | struct device_attribute *attr, | |
5027 | char *buf) | |
5028 | { | |
5029 | return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); | |
5030 | } | |
5031 | ||
5032 | static DEFINE_MUTEX(freeze_on_smi_mutex); | |
5033 | ||
5034 | static ssize_t freeze_on_smi_store(struct device *cdev, | |
5035 | struct device_attribute *attr, | |
5036 | const char *buf, size_t count) | |
5037 | { | |
5038 | unsigned long val; | |
5039 | ssize_t ret; | |
5040 | ||
5041 | ret = kstrtoul(buf, 0, &val); | |
5042 | if (ret) | |
5043 | return ret; | |
5044 | ||
5045 | if (val > 1) | |
5046 | return -EINVAL; | |
5047 | ||
5048 | mutex_lock(&freeze_on_smi_mutex); | |
5049 | ||
5050 | if (x86_pmu.attr_freeze_on_smi == val) | |
5051 | goto done; | |
5052 | ||
5053 | x86_pmu.attr_freeze_on_smi = val; | |
5054 | ||
eda8a2c5 | 5055 | cpus_read_lock(); |
6089327f | 5056 | on_each_cpu(flip_smm_bit, &val, 1); |
eda8a2c5 | 5057 | cpus_read_unlock(); |
6089327f KL |
5058 | done: |
5059 | mutex_unlock(&freeze_on_smi_mutex); | |
5060 | ||
5061 | return count; | |
5062 | } | |
5063 | ||
f447e4eb SE |
5064 | static void update_tfa_sched(void *ignored) |
5065 | { | |
5066 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
5067 | ||
5068 | /* | |
5069 | * check if PMC3 is used | |
5070 | * and if so force schedule out for all event types all contexts | |
5071 | */ | |
5072 | if (test_bit(3, cpuc->active_mask)) | |
61e76d53 | 5073 | perf_pmu_resched(x86_get_pmu(smp_processor_id())); |
f447e4eb SE |
5074 | } |
5075 | ||
5076 | static ssize_t show_sysctl_tfa(struct device *cdev, | |
5077 | struct device_attribute *attr, | |
5078 | char *buf) | |
5079 | { | |
5080 | return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); | |
5081 | } | |
5082 | ||
5083 | static ssize_t set_sysctl_tfa(struct device *cdev, | |
5084 | struct device_attribute *attr, | |
5085 | const char *buf, size_t count) | |
5086 | { | |
5087 | bool val; | |
5088 | ssize_t ret; | |
5089 | ||
5090 | ret = kstrtobool(buf, &val); | |
5091 | if (ret) | |
5092 | return ret; | |
5093 | ||
5094 | /* no change */ | |
5095 | if (val == allow_tsx_force_abort) | |
5096 | return count; | |
5097 | ||
5098 | allow_tsx_force_abort = val; | |
5099 | ||
eda8a2c5 | 5100 | cpus_read_lock(); |
f447e4eb | 5101 | on_each_cpu(update_tfa_sched, NULL, 1); |
eda8a2c5 | 5102 | cpus_read_unlock(); |
f447e4eb SE |
5103 | |
5104 | return count; | |
5105 | } | |
5106 | ||
5107 | ||
6089327f KL |
5108 | static DEVICE_ATTR_RW(freeze_on_smi); |
5109 | ||
b00233b5 AK |
5110 | static ssize_t branches_show(struct device *cdev, |
5111 | struct device_attribute *attr, | |
5112 | char *buf) | |
5113 | { | |
5114 | return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); | |
5115 | } | |
5116 | ||
5117 | static DEVICE_ATTR_RO(branches); | |
5118 | ||
5119 | static struct attribute *lbr_attrs[] = { | |
5120 | &dev_attr_branches.attr, | |
5121 | NULL | |
5122 | }; | |
5123 | ||
5124 | static char pmu_name_str[30]; | |
5125 | ||
5126 | static ssize_t pmu_name_show(struct device *cdev, | |
5127 | struct device_attribute *attr, | |
5128 | char *buf) | |
5129 | { | |
5130 | return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); | |
5131 | } | |
5132 | ||
5133 | static DEVICE_ATTR_RO(pmu_name); | |
5134 | ||
b00233b5 | 5135 | static struct attribute *intel_pmu_caps_attrs[] = { |
5da382eb PZ |
5136 | &dev_attr_pmu_name.attr, |
5137 | NULL | |
b00233b5 AK |
5138 | }; |
5139 | ||
f447e4eb SE |
5140 | static DEVICE_ATTR(allow_tsx_force_abort, 0644, |
5141 | show_sysctl_tfa, | |
5142 | set_sysctl_tfa); | |
400816f6 | 5143 | |
6089327f KL |
5144 | static struct attribute *intel_pmu_attrs[] = { |
5145 | &dev_attr_freeze_on_smi.attr, | |
b7c9b392 | 5146 | &dev_attr_allow_tsx_force_abort.attr, |
6089327f KL |
5147 | NULL, |
5148 | }; | |
5149 | ||
baa0c833 JO |
5150 | static umode_t |
5151 | tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) | |
d4ae5529 | 5152 | { |
baa0c833 JO |
5153 | return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; |
5154 | } | |
d4ae5529 | 5155 | |
baa0c833 JO |
5156 | static umode_t |
5157 | pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) | |
5158 | { | |
5159 | return x86_pmu.pebs ? attr->mode : 0; | |
5160 | } | |
d4ae5529 | 5161 | |
1f157286 JO |
5162 | static umode_t |
5163 | lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) | |
5164 | { | |
5165 | return x86_pmu.lbr_nr ? attr->mode : 0; | |
5166 | } | |
5167 | ||
3ea40ac7 JO |
5168 | static umode_t |
5169 | exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) | |
5170 | { | |
5171 | return x86_pmu.version >= 2 ? attr->mode : 0; | |
5172 | } | |
5173 | ||
b7c9b392 JO |
5174 | static umode_t |
5175 | default_is_visible(struct kobject *kobj, struct attribute *attr, int i) | |
5176 | { | |
5177 | if (attr == &dev_attr_allow_tsx_force_abort.attr) | |
5178 | return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; | |
5179 | ||
5180 | return attr->mode; | |
5181 | } | |
5182 | ||
baa0c833 JO |
5183 | static struct attribute_group group_events_td = { |
5184 | .name = "events", | |
5185 | }; | |
d4ae5529 | 5186 | |
baa0c833 JO |
5187 | static struct attribute_group group_events_mem = { |
5188 | .name = "events", | |
5189 | .is_visible = pebs_is_visible, | |
5190 | }; | |
5191 | ||
5192 | static struct attribute_group group_events_tsx = { | |
5193 | .name = "events", | |
5194 | .is_visible = tsx_is_visible, | |
5195 | }; | |
5196 | ||
1f157286 JO |
5197 | static struct attribute_group group_caps_gen = { |
5198 | .name = "caps", | |
5199 | .attrs = intel_pmu_caps_attrs, | |
5200 | }; | |
5201 | ||
5202 | static struct attribute_group group_caps_lbr = { | |
5203 | .name = "caps", | |
5204 | .attrs = lbr_attrs, | |
5205 | .is_visible = lbr_is_visible, | |
5206 | }; | |
5207 | ||
3ea40ac7 JO |
5208 | static struct attribute_group group_format_extra = { |
5209 | .name = "format", | |
5210 | .is_visible = exra_is_visible, | |
5211 | }; | |
5212 | ||
b6576880 JO |
5213 | static struct attribute_group group_format_extra_skl = { |
5214 | .name = "format", | |
5215 | .is_visible = exra_is_visible, | |
5216 | }; | |
5217 | ||
6a9f4efe | 5218 | static struct attribute_group group_default = { |
b7c9b392 JO |
5219 | .attrs = intel_pmu_attrs, |
5220 | .is_visible = default_is_visible, | |
6a9f4efe JO |
5221 | }; |
5222 | ||
baa0c833 JO |
5223 | static const struct attribute_group *attr_update[] = { |
5224 | &group_events_td, | |
5225 | &group_events_mem, | |
5226 | &group_events_tsx, | |
1f157286 JO |
5227 | &group_caps_gen, |
5228 | &group_caps_lbr, | |
3ea40ac7 | 5229 | &group_format_extra, |
b6576880 | 5230 | &group_format_extra_skl, |
6a9f4efe | 5231 | &group_default, |
baa0c833 JO |
5232 | NULL, |
5233 | }; | |
5234 | ||
f83d2f91 KL |
5235 | EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); |
5236 | EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); | |
5237 | EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); | |
5238 | EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); | |
5239 | EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); | |
5240 | EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); | |
5241 | EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); | |
5242 | EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); | |
5243 | EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); | |
5244 | ||
5245 | static struct attribute *adl_hybrid_events_attrs[] = { | |
5246 | EVENT_PTR(slots_adl), | |
5247 | EVENT_PTR(td_retiring_adl), | |
5248 | EVENT_PTR(td_bad_spec_adl), | |
5249 | EVENT_PTR(td_fe_bound_adl), | |
5250 | EVENT_PTR(td_be_bound_adl), | |
5251 | EVENT_PTR(td_heavy_ops_adl), | |
5252 | EVENT_PTR(td_br_mis_adl), | |
5253 | EVENT_PTR(td_fetch_lat_adl), | |
5254 | EVENT_PTR(td_mem_bound_adl), | |
5255 | NULL, | |
5256 | }; | |
5257 | ||
5258 | /* Must be in IDX order */ | |
5259 | EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); | |
5260 | EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); | |
5261 | EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); | |
5262 | ||
5263 | static struct attribute *adl_hybrid_mem_attrs[] = { | |
5264 | EVENT_PTR(mem_ld_adl), | |
5265 | EVENT_PTR(mem_st_adl), | |
5266 | EVENT_PTR(mem_ld_aux_adl), | |
5267 | NULL, | |
5268 | }; | |
5269 | ||
5270 | EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); | |
5271 | EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); | |
5272 | EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); | |
5273 | EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); | |
5274 | EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); | |
5275 | EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); | |
5276 | EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); | |
5277 | EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); | |
5278 | ||
5279 | static struct attribute *adl_hybrid_tsx_attrs[] = { | |
5280 | EVENT_PTR(tx_start_adl), | |
5281 | EVENT_PTR(tx_abort_adl), | |
5282 | EVENT_PTR(tx_commit_adl), | |
5283 | EVENT_PTR(tx_capacity_read_adl), | |
5284 | EVENT_PTR(tx_capacity_write_adl), | |
5285 | EVENT_PTR(tx_conflict_adl), | |
5286 | EVENT_PTR(cycles_t_adl), | |
5287 | EVENT_PTR(cycles_ct_adl), | |
5288 | NULL, | |
5289 | }; | |
5290 | ||
5291 | FORMAT_ATTR_HYBRID(in_tx, hybrid_big); | |
5292 | FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); | |
5293 | FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); | |
5294 | FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); | |
5295 | FORMAT_ATTR_HYBRID(frontend, hybrid_big); | |
5296 | ||
5297 | static struct attribute *adl_hybrid_extra_attr_rtm[] = { | |
5298 | FORMAT_HYBRID_PTR(in_tx), | |
5299 | FORMAT_HYBRID_PTR(in_tx_cp), | |
5300 | FORMAT_HYBRID_PTR(offcore_rsp), | |
5301 | FORMAT_HYBRID_PTR(ldlat), | |
5302 | FORMAT_HYBRID_PTR(frontend), | |
5303 | NULL, | |
5304 | }; | |
5305 | ||
5306 | static struct attribute *adl_hybrid_extra_attr[] = { | |
5307 | FORMAT_HYBRID_PTR(offcore_rsp), | |
5308 | FORMAT_HYBRID_PTR(ldlat), | |
5309 | FORMAT_HYBRID_PTR(frontend), | |
5310 | NULL, | |
5311 | }; | |
5312 | ||
58ae30c2 KL |
5313 | static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) |
5314 | { | |
5315 | struct device *dev = kobj_to_dev(kobj); | |
5316 | struct x86_hybrid_pmu *pmu = | |
5317 | container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); | |
5318 | struct perf_pmu_events_hybrid_attr *pmu_attr = | |
5319 | container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); | |
5320 | ||
5321 | return pmu->cpu_type & pmu_attr->pmu_type; | |
5322 | } | |
5323 | ||
5324 | static umode_t hybrid_events_is_visible(struct kobject *kobj, | |
5325 | struct attribute *attr, int i) | |
5326 | { | |
5327 | return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; | |
5328 | } | |
5329 | ||
5330 | static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) | |
5331 | { | |
5332 | int cpu = cpumask_first(&pmu->supported_cpus); | |
5333 | ||
5334 | return (cpu >= nr_cpu_ids) ? -1 : cpu; | |
5335 | } | |
5336 | ||
5337 | static umode_t hybrid_tsx_is_visible(struct kobject *kobj, | |
5338 | struct attribute *attr, int i) | |
5339 | { | |
5340 | struct device *dev = kobj_to_dev(kobj); | |
5341 | struct x86_hybrid_pmu *pmu = | |
5342 | container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); | |
5343 | int cpu = hybrid_find_supported_cpu(pmu); | |
5344 | ||
5345 | return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; | |
5346 | } | |
5347 | ||
5348 | static umode_t hybrid_format_is_visible(struct kobject *kobj, | |
5349 | struct attribute *attr, int i) | |
5350 | { | |
5351 | struct device *dev = kobj_to_dev(kobj); | |
5352 | struct x86_hybrid_pmu *pmu = | |
5353 | container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); | |
5354 | struct perf_pmu_format_hybrid_attr *pmu_attr = | |
5355 | container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); | |
5356 | int cpu = hybrid_find_supported_cpu(pmu); | |
5357 | ||
5358 | return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0; | |
5359 | } | |
5360 | ||
5361 | static struct attribute_group hybrid_group_events_td = { | |
5362 | .name = "events", | |
5363 | .is_visible = hybrid_events_is_visible, | |
5364 | }; | |
5365 | ||
5366 | static struct attribute_group hybrid_group_events_mem = { | |
5367 | .name = "events", | |
5368 | .is_visible = hybrid_events_is_visible, | |
5369 | }; | |
5370 | ||
5371 | static struct attribute_group hybrid_group_events_tsx = { | |
5372 | .name = "events", | |
5373 | .is_visible = hybrid_tsx_is_visible, | |
5374 | }; | |
5375 | ||
5376 | static struct attribute_group hybrid_group_format_extra = { | |
5377 | .name = "format", | |
5378 | .is_visible = hybrid_format_is_visible, | |
5379 | }; | |
5380 | ||
5381 | static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, | |
5382 | struct device_attribute *attr, | |
5383 | char *buf) | |
5384 | { | |
5385 | struct x86_hybrid_pmu *pmu = | |
5386 | container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); | |
5387 | ||
5388 | return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); | |
5389 | } | |
5390 | ||
5391 | static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); | |
5392 | static struct attribute *intel_hybrid_cpus_attrs[] = { | |
5393 | &dev_attr_cpus.attr, | |
5394 | NULL, | |
5395 | }; | |
5396 | ||
5397 | static struct attribute_group hybrid_group_cpus = { | |
5398 | .attrs = intel_hybrid_cpus_attrs, | |
5399 | }; | |
5400 | ||
5401 | static const struct attribute_group *hybrid_attr_update[] = { | |
5402 | &hybrid_group_events_td, | |
5403 | &hybrid_group_events_mem, | |
5404 | &hybrid_group_events_tsx, | |
5405 | &group_caps_gen, | |
5406 | &group_caps_lbr, | |
5407 | &hybrid_group_format_extra, | |
5408 | &group_default, | |
5409 | &hybrid_group_cpus, | |
5410 | NULL, | |
5411 | }; | |
5412 | ||
baa0c833 | 5413 | static struct attribute *empty_attrs; |
d4ae5529 | 5414 | |
b8c4d1a8 KL |
5415 | static void intel_pmu_check_num_counters(int *num_counters, |
5416 | int *num_counters_fixed, | |
5417 | u64 *intel_ctrl, u64 fixed_mask) | |
5418 | { | |
5419 | if (*num_counters > INTEL_PMC_MAX_GENERIC) { | |
5420 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", | |
5421 | *num_counters, INTEL_PMC_MAX_GENERIC); | |
5422 | *num_counters = INTEL_PMC_MAX_GENERIC; | |
5423 | } | |
5424 | *intel_ctrl = (1ULL << *num_counters) - 1; | |
5425 | ||
5426 | if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) { | |
5427 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", | |
5428 | *num_counters_fixed, INTEL_PMC_MAX_FIXED); | |
5429 | *num_counters_fixed = INTEL_PMC_MAX_FIXED; | |
5430 | } | |
5431 | ||
5432 | *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED; | |
5433 | } | |
5434 | ||
bc14fe1b KL |
5435 | static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, |
5436 | int num_counters, | |
5437 | int num_counters_fixed, | |
5438 | u64 intel_ctrl) | |
5439 | { | |
5440 | struct event_constraint *c; | |
5441 | ||
5442 | if (!event_constraints) | |
5443 | return; | |
5444 | ||
5445 | /* | |
5446 | * event on fixed counter2 (REF_CYCLES) only works on this | |
5447 | * counter, so do not extend mask to generic counters | |
5448 | */ | |
5449 | for_each_event_constraint(c, event_constraints) { | |
5450 | /* | |
5451 | * Don't extend the topdown slots and metrics | |
5452 | * events to the generic counters. | |
5453 | */ | |
5454 | if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { | |
5455 | /* | |
5456 | * Disable topdown slots and metrics events, | |
5457 | * if slots event is not in CPUID. | |
5458 | */ | |
5459 | if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) | |
5460 | c->idxmsk64 = 0; | |
5461 | c->weight = hweight64(c->idxmsk64); | |
5462 | continue; | |
5463 | } | |
5464 | ||
5465 | if (c->cmask == FIXED_EVENT_FLAGS) { | |
5466 | /* Disabled fixed counters which are not in CPUID */ | |
5467 | c->idxmsk64 &= intel_ctrl; | |
5468 | ||
762c0289 KL |
5469 | /* |
5470 | * Don't extend the pseudo-encoding to the | |
5471 | * generic counters | |
5472 | */ | |
5473 | if (!use_fixed_pseudo_encoding(c->code)) | |
bc14fe1b KL |
5474 | c->idxmsk64 |= (1ULL << num_counters) - 1; |
5475 | } | |
5476 | c->idxmsk64 &= | |
5477 | ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed)); | |
5478 | c->weight = hweight64(c->idxmsk64); | |
5479 | } | |
5480 | } | |
5481 | ||
34d5b61f KL |
5482 | static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) |
5483 | { | |
5484 | struct extra_reg *er; | |
5485 | ||
5486 | /* | |
5487 | * Access extra MSR may cause #GP under certain circumstances. | |
5488 | * E.g. KVM doesn't support offcore event | |
5489 | * Check all extra_regs here. | |
5490 | */ | |
5491 | if (!extra_regs) | |
5492 | return; | |
5493 | ||
5494 | for (er = extra_regs; er->msr; er++) { | |
5495 | er->extra_msr_access = check_msr(er->msr, 0x11UL); | |
5496 | /* Disable LBR select mapping */ | |
5497 | if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) | |
5498 | x86_pmu.lbr_sel_map = NULL; | |
5499 | } | |
5500 | } | |
5501 | ||
d9977c43 KL |
5502 | static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) |
5503 | { | |
5504 | struct x86_hybrid_pmu *pmu; | |
5505 | int i; | |
5506 | ||
5507 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { | |
5508 | pmu = &x86_pmu.hybrid_pmu[i]; | |
5509 | ||
5510 | intel_pmu_check_num_counters(&pmu->num_counters, | |
5511 | &pmu->num_counters_fixed, | |
5512 | &pmu->intel_ctrl, | |
5513 | fixed_mask); | |
5514 | ||
5515 | if (pmu->intel_cap.perf_metrics) { | |
5516 | pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; | |
5517 | pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS; | |
5518 | } | |
5519 | ||
5520 | if (pmu->intel_cap.pebs_output_pt_available) | |
5521 | pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; | |
5522 | ||
5523 | intel_pmu_check_event_constraints(pmu->event_constraints, | |
5524 | pmu->num_counters, | |
5525 | pmu->num_counters_fixed, | |
5526 | pmu->intel_ctrl); | |
5527 | ||
5528 | intel_pmu_check_extra_regs(pmu->extra_regs); | |
5529 | } | |
5530 | } | |
5531 | ||
de0428a7 | 5532 | __init int intel_pmu_init(void) |
f22f54f4 | 5533 | { |
b6576880 | 5534 | struct attribute **extra_skl_attr = &empty_attrs; |
baa0c833 JO |
5535 | struct attribute **extra_attr = &empty_attrs; |
5536 | struct attribute **td_attr = &empty_attrs; | |
5537 | struct attribute **mem_attr = &empty_attrs; | |
5538 | struct attribute **tsx_attr = &empty_attrs; | |
f22f54f4 PZ |
5539 | union cpuid10_edx edx; |
5540 | union cpuid10_eax eax; | |
ffb871bc | 5541 | union cpuid10_ebx ebx; |
32451614 | 5542 | unsigned int fixed_mask; |
faaeff98 | 5543 | bool pmem = false; |
338b522c | 5544 | int version, i; |
b00233b5 | 5545 | char *name; |
f83d2f91 | 5546 | struct x86_hybrid_pmu *pmu; |
f22f54f4 PZ |
5547 | |
5548 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { | |
a072738e CG |
5549 | switch (boot_cpu_data.x86) { |
5550 | case 0x6: | |
5551 | return p6_pmu_init(); | |
e717bf4e VW |
5552 | case 0xb: |
5553 | return knc_pmu_init(); | |
a072738e CG |
5554 | case 0xf: |
5555 | return p4_pmu_init(); | |
5556 | } | |
f22f54f4 | 5557 | return -ENODEV; |
f22f54f4 PZ |
5558 | } |
5559 | ||
5560 | /* | |
5561 | * Check whether the Architectural PerfMon supports | |
5562 | * Branch Misses Retired hw_event or not. | |
5563 | */ | |
32451614 | 5564 | cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); |
ffb871bc | 5565 | if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) |
f22f54f4 PZ |
5566 | return -ENODEV; |
5567 | ||
5568 | version = eax.split.version_id; | |
5569 | if (version < 2) | |
5570 | x86_pmu = core_pmu; | |
5571 | else | |
5572 | x86_pmu = intel_pmu; | |
5573 | ||
5574 | x86_pmu.version = version; | |
948b1bb8 RR |
5575 | x86_pmu.num_counters = eax.split.num_counters; |
5576 | x86_pmu.cntval_bits = eax.split.bit_width; | |
5577 | x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; | |
f22f54f4 | 5578 | |
c1d6f42f PZ |
5579 | x86_pmu.events_maskl = ebx.full; |
5580 | x86_pmu.events_mask_len = eax.split.mask_length; | |
5581 | ||
70ab7003 AK |
5582 | x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); |
5583 | ||
f22f54f4 PZ |
5584 | /* |
5585 | * Quirk: v2 perfmon does not report fixed-purpose events, so | |
f92b7604 | 5586 | * assume at least 3 events, when not running in a hypervisor: |
f22f54f4 | 5587 | */ |
32451614 | 5588 | if (version > 1 && version < 5) { |
f92b7604 IP |
5589 | int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); |
5590 | ||
5591 | x86_pmu.num_counters_fixed = | |
5592 | max((int)edx.split.num_counters_fixed, assume); | |
32451614 KL |
5593 | |
5594 | fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; | |
5595 | } else if (version >= 5) | |
5596 | x86_pmu.num_counters_fixed = fls(fixed_mask); | |
f22f54f4 | 5597 | |
c9b08884 | 5598 | if (boot_cpu_has(X86_FEATURE_PDCM)) { |
8db909a7 PZ |
5599 | u64 capabilities; |
5600 | ||
5601 | rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); | |
5602 | x86_pmu.intel_cap.capabilities = capabilities; | |
5603 | } | |
5604 | ||
c301b1d8 | 5605 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { |
9f354a72 | 5606 | x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; |
c301b1d8 KL |
5607 | x86_pmu.lbr_read = intel_pmu_lbr_read_32; |
5608 | } | |
9f354a72 | 5609 | |
47125db2 KL |
5610 | if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) |
5611 | intel_pmu_arch_lbr_init(); | |
5612 | ||
ca037701 PZ |
5613 | intel_ds_init(); |
5614 | ||
c1d6f42f PZ |
5615 | x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ |
5616 | ||
cadbaa03 SE |
5617 | if (version >= 5) { |
5618 | x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; | |
5619 | if (x86_pmu.intel_cap.anythread_deprecated) | |
5620 | pr_cont(" AnyThread deprecated, "); | |
5621 | } | |
5622 | ||
f22f54f4 PZ |
5623 | /* |
5624 | * Install the hw-cache-events table: | |
5625 | */ | |
5626 | switch (boot_cpu_data.x86_model) { | |
ef5f9f47 | 5627 | case INTEL_FAM6_CORE_YONAH: |
f22f54f4 | 5628 | pr_cont("Core events, "); |
b00233b5 | 5629 | name = "core"; |
f22f54f4 PZ |
5630 | break; |
5631 | ||
ef5f9f47 | 5632 | case INTEL_FAM6_CORE2_MEROM: |
c1d6f42f | 5633 | x86_add_quirk(intel_clovertown_quirk); |
df561f66 | 5634 | fallthrough; |
2b0fc374 | 5635 | |
ef5f9f47 DH |
5636 | case INTEL_FAM6_CORE2_MEROM_L: |
5637 | case INTEL_FAM6_CORE2_PENRYN: | |
5638 | case INTEL_FAM6_CORE2_DUNNINGTON: | |
f22f54f4 PZ |
5639 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
5640 | sizeof(hw_cache_event_ids)); | |
5641 | ||
caff2bef PZ |
5642 | intel_pmu_lbr_init_core(); |
5643 | ||
f22f54f4 | 5644 | x86_pmu.event_constraints = intel_core2_event_constraints; |
17e31629 | 5645 | x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; |
f22f54f4 | 5646 | pr_cont("Core2 events, "); |
b00233b5 | 5647 | name = "core2"; |
f22f54f4 PZ |
5648 | break; |
5649 | ||
ef5f9f47 DH |
5650 | case INTEL_FAM6_NEHALEM: |
5651 | case INTEL_FAM6_NEHALEM_EP: | |
5652 | case INTEL_FAM6_NEHALEM_EX: | |
f22f54f4 PZ |
5653 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, |
5654 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
5655 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
5656 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 5657 | |
caff2bef PZ |
5658 | intel_pmu_lbr_init_nhm(); |
5659 | ||
f22f54f4 | 5660 | x86_pmu.event_constraints = intel_nehalem_event_constraints; |
17e31629 | 5661 | x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; |
11164cd4 | 5662 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
a7e3ed1e | 5663 | x86_pmu.extra_regs = intel_nehalem_extra_regs; |
44d3bbb6 | 5664 | x86_pmu.limit_period = nhm_limit_period; |
ec75a716 | 5665 | |
d4ae5529 | 5666 | mem_attr = nhm_mem_events_attrs; |
f20093ee | 5667 | |
91fc4cc0 | 5668 | /* UOPS_ISSUED.STALLED_CYCLES */ |
f9b4eeb8 PZ |
5669 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
5670 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
91fc4cc0 | 5671 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
5672 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
5673 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
94403f88 | 5674 | |
e17dc653 | 5675 | intel_pmu_pebs_data_source_nhm(); |
c1d6f42f | 5676 | x86_add_quirk(intel_nehalem_quirk); |
95298355 | 5677 | x86_pmu.pebs_no_tlb = 1; |
a5df70c3 | 5678 | extra_attr = nhm_format_attr; |
ec75a716 | 5679 | |
11164cd4 | 5680 | pr_cont("Nehalem events, "); |
b00233b5 | 5681 | name = "nehalem"; |
f22f54f4 | 5682 | break; |
caff2bef | 5683 | |
f2c4db1b PZ |
5684 | case INTEL_FAM6_ATOM_BONNELL: |
5685 | case INTEL_FAM6_ATOM_BONNELL_MID: | |
5686 | case INTEL_FAM6_ATOM_SALTWELL: | |
5687 | case INTEL_FAM6_ATOM_SALTWELL_MID: | |
5688 | case INTEL_FAM6_ATOM_SALTWELL_TABLET: | |
f22f54f4 PZ |
5689 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, |
5690 | sizeof(hw_cache_event_ids)); | |
5691 | ||
caff2bef PZ |
5692 | intel_pmu_lbr_init_atom(); |
5693 | ||
f22f54f4 | 5694 | x86_pmu.event_constraints = intel_gen_event_constraints; |
17e31629 | 5695 | x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; |
673d188b | 5696 | x86_pmu.pebs_aliases = intel_pebs_aliases_core2; |
f22f54f4 | 5697 | pr_cont("Atom events, "); |
b00233b5 | 5698 | name = "bonnell"; |
f22f54f4 PZ |
5699 | break; |
5700 | ||
f2c4db1b | 5701 | case INTEL_FAM6_ATOM_SILVERMONT: |
5ebb34ed | 5702 | case INTEL_FAM6_ATOM_SILVERMONT_D: |
f2c4db1b | 5703 | case INTEL_FAM6_ATOM_SILVERMONT_MID: |
ef5f9f47 | 5704 | case INTEL_FAM6_ATOM_AIRMONT: |
f2c4db1b | 5705 | case INTEL_FAM6_ATOM_AIRMONT_MID: |
1fa64180 YZ |
5706 | memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, |
5707 | sizeof(hw_cache_event_ids)); | |
5708 | memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, | |
5709 | sizeof(hw_cache_extra_regs)); | |
5710 | ||
f21d5adc | 5711 | intel_pmu_lbr_init_slm(); |
1fa64180 YZ |
5712 | |
5713 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
5714 | x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; | |
5715 | x86_pmu.extra_regs = intel_slm_extra_regs; | |
9a5e3fb5 | 5716 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
baa0c833 | 5717 | td_attr = slm_events_attrs; |
a5df70c3 | 5718 | extra_attr = slm_format_attr; |
1fa64180 | 5719 | pr_cont("Silvermont events, "); |
b00233b5 | 5720 | name = "silvermont"; |
1fa64180 YZ |
5721 | break; |
5722 | ||
ef5f9f47 | 5723 | case INTEL_FAM6_ATOM_GOLDMONT: |
5ebb34ed | 5724 | case INTEL_FAM6_ATOM_GOLDMONT_D: |
8b92c3a7 KL |
5725 | memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, |
5726 | sizeof(hw_cache_event_ids)); | |
5727 | memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, | |
5728 | sizeof(hw_cache_extra_regs)); | |
5729 | ||
5730 | intel_pmu_lbr_init_skl(); | |
5731 | ||
5732 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
5733 | x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; | |
5734 | x86_pmu.extra_regs = intel_glm_extra_regs; | |
5735 | /* | |
5736 | * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS | |
5737 | * for precise cycles. | |
5738 | * :pp is identical to :ppp | |
5739 | */ | |
5740 | x86_pmu.pebs_aliases = NULL; | |
5741 | x86_pmu.pebs_prec_dist = true; | |
ccbebba4 | 5742 | x86_pmu.lbr_pt_coexist = true; |
8b92c3a7 | 5743 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
baa0c833 | 5744 | td_attr = glm_events_attrs; |
a5df70c3 | 5745 | extra_attr = slm_format_attr; |
8b92c3a7 | 5746 | pr_cont("Goldmont events, "); |
b00233b5 | 5747 | name = "goldmont"; |
8b92c3a7 KL |
5748 | break; |
5749 | ||
f2c4db1b | 5750 | case INTEL_FAM6_ATOM_GOLDMONT_PLUS: |
dd0b06b5 KL |
5751 | memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, |
5752 | sizeof(hw_cache_event_ids)); | |
5753 | memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, | |
5754 | sizeof(hw_cache_extra_regs)); | |
5755 | ||
5756 | intel_pmu_lbr_init_skl(); | |
5757 | ||
5758 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
dd0b06b5 KL |
5759 | x86_pmu.extra_regs = intel_glm_extra_regs; |
5760 | /* | |
5761 | * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS | |
5762 | * for precise cycles. | |
5763 | */ | |
5764 | x86_pmu.pebs_aliases = NULL; | |
5765 | x86_pmu.pebs_prec_dist = true; | |
5766 | x86_pmu.lbr_pt_coexist = true; | |
5767 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
a38b0ba1 | 5768 | x86_pmu.flags |= PMU_FL_PEBS_ALL; |
dd0b06b5 | 5769 | x86_pmu.get_event_constraints = glp_get_event_constraints; |
baa0c833 | 5770 | td_attr = glm_events_attrs; |
dd0b06b5 KL |
5771 | /* Goldmont Plus has 4-wide pipeline */ |
5772 | event_attr_td_total_slots_scale_glm.event_str = "4"; | |
a5df70c3 | 5773 | extra_attr = slm_format_attr; |
dd0b06b5 | 5774 | pr_cont("Goldmont plus events, "); |
b00233b5 | 5775 | name = "goldmont_plus"; |
dd0b06b5 KL |
5776 | break; |
5777 | ||
5ebb34ed | 5778 | case INTEL_FAM6_ATOM_TREMONT_D: |
eda23b38 | 5779 | case INTEL_FAM6_ATOM_TREMONT: |
dbfd6388 | 5780 | case INTEL_FAM6_ATOM_TREMONT_L: |
6daeb873 KL |
5781 | x86_pmu.late_ack = true; |
5782 | memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, | |
5783 | sizeof(hw_cache_event_ids)); | |
5784 | memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, | |
5785 | sizeof(hw_cache_extra_regs)); | |
5786 | hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; | |
5787 | ||
5788 | intel_pmu_lbr_init_skl(); | |
5789 | ||
5790 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
5791 | x86_pmu.extra_regs = intel_tnt_extra_regs; | |
5792 | /* | |
5793 | * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS | |
5794 | * for precise cycles. | |
5795 | */ | |
5796 | x86_pmu.pebs_aliases = NULL; | |
5797 | x86_pmu.pebs_prec_dist = true; | |
5798 | x86_pmu.lbr_pt_coexist = true; | |
5799 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
5800 | x86_pmu.get_event_constraints = tnt_get_event_constraints; | |
c2208046 | 5801 | td_attr = tnt_events_attrs; |
6daeb873 KL |
5802 | extra_attr = slm_format_attr; |
5803 | pr_cont("Tremont events, "); | |
5804 | name = "Tremont"; | |
5805 | break; | |
5806 | ||
ef5f9f47 DH |
5807 | case INTEL_FAM6_WESTMERE: |
5808 | case INTEL_FAM6_WESTMERE_EP: | |
5809 | case INTEL_FAM6_WESTMERE_EX: | |
f22f54f4 PZ |
5810 | memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, |
5811 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
5812 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
5813 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 5814 | |
caff2bef PZ |
5815 | intel_pmu_lbr_init_nhm(); |
5816 | ||
f22f54f4 | 5817 | x86_pmu.event_constraints = intel_westmere_event_constraints; |
40b91cd1 | 5818 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
17e31629 | 5819 | x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; |
a7e3ed1e | 5820 | x86_pmu.extra_regs = intel_westmere_extra_regs; |
9a5e3fb5 | 5821 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
30112039 | 5822 | |
d4ae5529 | 5823 | mem_attr = nhm_mem_events_attrs; |
f20093ee | 5824 | |
30112039 | 5825 | /* UOPS_ISSUED.STALLED_CYCLES */ |
f9b4eeb8 PZ |
5826 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
5827 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
30112039 | 5828 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
5829 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
5830 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
30112039 | 5831 | |
e17dc653 | 5832 | intel_pmu_pebs_data_source_nhm(); |
a5df70c3 | 5833 | extra_attr = nhm_format_attr; |
f22f54f4 | 5834 | pr_cont("Westmere events, "); |
b00233b5 | 5835 | name = "westmere"; |
f22f54f4 | 5836 | break; |
b622d644 | 5837 | |
ef5f9f47 DH |
5838 | case INTEL_FAM6_SANDYBRIDGE: |
5839 | case INTEL_FAM6_SANDYBRIDGE_X: | |
47a8863d | 5840 | x86_add_quirk(intel_sandybridge_quirk); |
93fcf72c | 5841 | x86_add_quirk(intel_ht_bug); |
b06b3d49 LM |
5842 | memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, |
5843 | sizeof(hw_cache_event_ids)); | |
74e6543f YZ |
5844 | memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, |
5845 | sizeof(hw_cache_extra_regs)); | |
b06b3d49 | 5846 | |
c5cc2cd9 | 5847 | intel_pmu_lbr_init_snb(); |
b06b3d49 LM |
5848 | |
5849 | x86_pmu.event_constraints = intel_snb_event_constraints; | |
de0428a7 | 5850 | x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; |
0780c927 | 5851 | x86_pmu.pebs_aliases = intel_pebs_aliases_snb; |
ef5f9f47 | 5852 | if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) |
f1923820 SE |
5853 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
5854 | else | |
5855 | x86_pmu.extra_regs = intel_snb_extra_regs; | |
93fcf72c MD |
5856 | |
5857 | ||
ee89cbc2 | 5858 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
5859 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
5860 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
e04d1b23 | 5861 | |
baa0c833 | 5862 | td_attr = snb_events_attrs; |
d4ae5529 | 5863 | mem_attr = snb_mem_events_attrs; |
f20093ee | 5864 | |
e04d1b23 | 5865 | /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ |
f9b4eeb8 PZ |
5866 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
5867 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 5868 | /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ |
f9b4eeb8 PZ |
5869 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
5870 | X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 5871 | |
a5df70c3 AK |
5872 | extra_attr = nhm_format_attr; |
5873 | ||
b06b3d49 | 5874 | pr_cont("SandyBridge events, "); |
b00233b5 | 5875 | name = "sandybridge"; |
b06b3d49 | 5876 | break; |
0f7c29ce | 5877 | |
ef5f9f47 DH |
5878 | case INTEL_FAM6_IVYBRIDGE: |
5879 | case INTEL_FAM6_IVYBRIDGE_X: | |
93fcf72c | 5880 | x86_add_quirk(intel_ht_bug); |
20a36e39 SE |
5881 | memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, |
5882 | sizeof(hw_cache_event_ids)); | |
1996388e VW |
5883 | /* dTLB-load-misses on IVB is different than SNB */ |
5884 | hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ | |
5885 | ||
20a36e39 SE |
5886 | memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, |
5887 | sizeof(hw_cache_extra_regs)); | |
5888 | ||
5889 | intel_pmu_lbr_init_snb(); | |
5890 | ||
69943182 | 5891 | x86_pmu.event_constraints = intel_ivb_event_constraints; |
20a36e39 | 5892 | x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; |
72469764 AK |
5893 | x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; |
5894 | x86_pmu.pebs_prec_dist = true; | |
ef5f9f47 | 5895 | if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) |
f1923820 SE |
5896 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
5897 | else | |
5898 | x86_pmu.extra_regs = intel_snb_extra_regs; | |
20a36e39 | 5899 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
5900 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
5901 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
20a36e39 | 5902 | |
baa0c833 | 5903 | td_attr = snb_events_attrs; |
d4ae5529 | 5904 | mem_attr = snb_mem_events_attrs; |
f20093ee | 5905 | |
20a36e39 SE |
5906 | /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ |
5907 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = | |
5908 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
5909 | ||
a5df70c3 AK |
5910 | extra_attr = nhm_format_attr; |
5911 | ||
20a36e39 | 5912 | pr_cont("IvyBridge events, "); |
b00233b5 | 5913 | name = "ivybridge"; |
20a36e39 SE |
5914 | break; |
5915 | ||
b06b3d49 | 5916 | |
c66f78a6 | 5917 | case INTEL_FAM6_HASWELL: |
ef5f9f47 | 5918 | case INTEL_FAM6_HASWELL_X: |
af239c44 | 5919 | case INTEL_FAM6_HASWELL_L: |
5e741407 | 5920 | case INTEL_FAM6_HASWELL_G: |
93fcf72c | 5921 | x86_add_quirk(intel_ht_bug); |
9b545c04 | 5922 | x86_add_quirk(intel_pebs_isolation_quirk); |
72db5596 | 5923 | x86_pmu.late_ack = true; |
0f1b5ca2 AK |
5924 | memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); |
5925 | memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
3a632cb2 | 5926 | |
e9d7f7cd | 5927 | intel_pmu_lbr_init_hsw(); |
3a632cb2 AK |
5928 | |
5929 | x86_pmu.event_constraints = intel_hsw_event_constraints; | |
3044318f | 5930 | x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; |
36bbb2f2 | 5931 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
72469764 AK |
5932 | x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; |
5933 | x86_pmu.pebs_prec_dist = true; | |
3a632cb2 | 5934 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
5935 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
5936 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
3a632cb2 AK |
5937 | |
5938 | x86_pmu.hw_config = hsw_hw_config; | |
5939 | x86_pmu.get_event_constraints = hsw_get_event_constraints; | |
b7af41a1 | 5940 | x86_pmu.lbr_double_abort = true; |
a5df70c3 AK |
5941 | extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? |
5942 | hsw_format_attr : nhm_format_attr; | |
baa0c833 | 5943 | td_attr = hsw_events_attrs; |
d4ae5529 JO |
5944 | mem_attr = hsw_mem_events_attrs; |
5945 | tsx_attr = hsw_tsx_events_attrs; | |
3a632cb2 | 5946 | pr_cont("Haswell events, "); |
b00233b5 | 5947 | name = "haswell"; |
3a632cb2 AK |
5948 | break; |
5949 | ||
c66f78a6 | 5950 | case INTEL_FAM6_BROADWELL: |
5ebb34ed | 5951 | case INTEL_FAM6_BROADWELL_D: |
5e741407 | 5952 | case INTEL_FAM6_BROADWELL_G: |
ef5f9f47 | 5953 | case INTEL_FAM6_BROADWELL_X: |
9b545c04 | 5954 | x86_add_quirk(intel_pebs_isolation_quirk); |
91f1b705 AK |
5955 | x86_pmu.late_ack = true; |
5956 | memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
5957 | memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
5958 | ||
5959 | /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ | |
5960 | hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | | |
5961 | BDW_L3_MISS|HSW_SNOOP_DRAM; | |
5962 | hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| | |
5963 | HSW_SNOOP_DRAM; | |
5964 | hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| | |
5965 | BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; | |
5966 | hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| | |
5967 | BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; | |
5968 | ||
78d504bc | 5969 | intel_pmu_lbr_init_hsw(); |
91f1b705 AK |
5970 | |
5971 | x86_pmu.event_constraints = intel_bdw_event_constraints; | |
b3e62463 | 5972 | x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; |
91f1b705 | 5973 | x86_pmu.extra_regs = intel_snbep_extra_regs; |
72469764 AK |
5974 | x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; |
5975 | x86_pmu.pebs_prec_dist = true; | |
91f1b705 | 5976 | /* all extra regs are per-cpu when HT is on */ |
9a5e3fb5 SE |
5977 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; |
5978 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
91f1b705 AK |
5979 | |
5980 | x86_pmu.hw_config = hsw_hw_config; | |
5981 | x86_pmu.get_event_constraints = hsw_get_event_constraints; | |
294fe0f5 | 5982 | x86_pmu.limit_period = bdw_limit_period; |
a5df70c3 AK |
5983 | extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? |
5984 | hsw_format_attr : nhm_format_attr; | |
baa0c833 | 5985 | td_attr = hsw_events_attrs; |
d4ae5529 JO |
5986 | mem_attr = hsw_mem_events_attrs; |
5987 | tsx_attr = hsw_tsx_events_attrs; | |
91f1b705 | 5988 | pr_cont("Broadwell events, "); |
b00233b5 | 5989 | name = "broadwell"; |
91f1b705 AK |
5990 | break; |
5991 | ||
ef5f9f47 | 5992 | case INTEL_FAM6_XEON_PHI_KNL: |
608284bf | 5993 | case INTEL_FAM6_XEON_PHI_KNM: |
1e7b9390 HC |
5994 | memcpy(hw_cache_event_ids, |
5995 | slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
5996 | memcpy(hw_cache_extra_regs, | |
5997 | knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
5998 | intel_pmu_lbr_init_knl(); | |
5999 | ||
6000 | x86_pmu.event_constraints = intel_slm_event_constraints; | |
6001 | x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; | |
6002 | x86_pmu.extra_regs = intel_knl_extra_regs; | |
6003 | ||
6004 | /* all extra regs are per-cpu when HT is on */ | |
6005 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
6006 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
a5df70c3 | 6007 | extra_attr = slm_format_attr; |
608284bf | 6008 | pr_cont("Knights Landing/Mill events, "); |
b00233b5 | 6009 | name = "knights-landing"; |
1e7b9390 HC |
6010 | break; |
6011 | ||
faaeff98 KL |
6012 | case INTEL_FAM6_SKYLAKE_X: |
6013 | pmem = true; | |
df561f66 | 6014 | fallthrough; |
af239c44 | 6015 | case INTEL_FAM6_SKYLAKE_L: |
c66f78a6 | 6016 | case INTEL_FAM6_SKYLAKE: |
af239c44 | 6017 | case INTEL_FAM6_KABYLAKE_L: |
c66f78a6 | 6018 | case INTEL_FAM6_KABYLAKE: |
9066288b KL |
6019 | case INTEL_FAM6_COMETLAKE_L: |
6020 | case INTEL_FAM6_COMETLAKE: | |
9b545c04 | 6021 | x86_add_quirk(intel_pebs_isolation_quirk); |
9a92e16f AK |
6022 | x86_pmu.late_ack = true; |
6023 | memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
6024 | memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
6025 | intel_pmu_lbr_init_skl(); | |
6026 | ||
a39fcae7 AK |
6027 | /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ |
6028 | event_attr_td_recovery_bubbles.event_str_noht = | |
6029 | "event=0xd,umask=0x1,cmask=1"; | |
6030 | event_attr_td_recovery_bubbles.event_str_ht = | |
6031 | "event=0xd,umask=0x1,cmask=1,any=1"; | |
6032 | ||
9a92e16f AK |
6033 | x86_pmu.event_constraints = intel_skl_event_constraints; |
6034 | x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; | |
6035 | x86_pmu.extra_regs = intel_skl_extra_regs; | |
72469764 AK |
6036 | x86_pmu.pebs_aliases = intel_pebs_aliases_skl; |
6037 | x86_pmu.pebs_prec_dist = true; | |
9a92e16f AK |
6038 | /* all extra regs are per-cpu when HT is on */ |
6039 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
6040 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
6041 | ||
6042 | x86_pmu.hw_config = hsw_hw_config; | |
6043 | x86_pmu.get_event_constraints = hsw_get_event_constraints; | |
a5df70c3 AK |
6044 | extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? |
6045 | hsw_format_attr : nhm_format_attr; | |
b6576880 | 6046 | extra_skl_attr = skl_format_attr; |
baa0c833 | 6047 | td_attr = hsw_events_attrs; |
d4ae5529 JO |
6048 | mem_attr = hsw_mem_events_attrs; |
6049 | tsx_attr = hsw_tsx_events_attrs; | |
faaeff98 | 6050 | intel_pmu_pebs_data_source_skl(pmem); |
400816f6 | 6051 | |
ad3c2e17 PG |
6052 | /* |
6053 | * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. | |
6054 | * TSX force abort hooks are not required on these systems. Only deploy | |
6055 | * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. | |
6056 | */ | |
6057 | if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && | |
6058 | !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { | |
400816f6 PZI |
6059 | x86_pmu.flags |= PMU_FL_TFA; |
6060 | x86_pmu.get_event_constraints = tfa_get_event_constraints; | |
6061 | x86_pmu.enable_all = intel_tfa_pmu_enable_all; | |
6062 | x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; | |
400816f6 PZI |
6063 | } |
6064 | ||
9a92e16f | 6065 | pr_cont("Skylake events, "); |
b00233b5 | 6066 | name = "skylake"; |
9a92e16f AK |
6067 | break; |
6068 | ||
faaeff98 | 6069 | case INTEL_FAM6_ICELAKE_X: |
5ebb34ed | 6070 | case INTEL_FAM6_ICELAKE_D: |
faaeff98 | 6071 | pmem = true; |
df561f66 | 6072 | fallthrough; |
af239c44 | 6073 | case INTEL_FAM6_ICELAKE_L: |
c66f78a6 | 6074 | case INTEL_FAM6_ICELAKE: |
23645a76 KL |
6075 | case INTEL_FAM6_TIGERLAKE_L: |
6076 | case INTEL_FAM6_TIGERLAKE: | |
b14d0db5 | 6077 | case INTEL_FAM6_ROCKETLAKE: |
60176089 KL |
6078 | x86_pmu.late_ack = true; |
6079 | memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
6080 | memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
6081 | hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; | |
6082 | intel_pmu_lbr_init_skl(); | |
6083 | ||
6084 | x86_pmu.event_constraints = intel_icl_event_constraints; | |
6085 | x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; | |
6086 | x86_pmu.extra_regs = intel_icl_extra_regs; | |
6087 | x86_pmu.pebs_aliases = NULL; | |
6088 | x86_pmu.pebs_prec_dist = true; | |
6089 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
6090 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
6091 | ||
6092 | x86_pmu.hw_config = hsw_hw_config; | |
6093 | x86_pmu.get_event_constraints = icl_get_event_constraints; | |
6094 | extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? | |
6095 | hsw_format_attr : nhm_format_attr; | |
b6576880 | 6096 | extra_skl_attr = skl_format_attr; |
baa0c833 | 6097 | mem_attr = icl_events_attrs; |
59a854e2 | 6098 | td_attr = icl_td_events_attrs; |
baa0c833 | 6099 | tsx_attr = icl_tsx_events_attrs; |
46b72e1b | 6100 | x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); |
60176089 | 6101 | x86_pmu.lbr_pt_coexist = true; |
faaeff98 | 6102 | intel_pmu_pebs_data_source_skl(pmem); |
1ab5f235 | 6103 | x86_pmu.num_topdown_events = 4; |
59a854e2 KL |
6104 | x86_pmu.update_topdown_event = icl_update_topdown_event; |
6105 | x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; | |
60176089 KL |
6106 | pr_cont("Icelake events, "); |
6107 | name = "icelake"; | |
6108 | break; | |
6109 | ||
61b985e3 KL |
6110 | case INTEL_FAM6_SAPPHIRERAPIDS_X: |
6111 | pmem = true; | |
6112 | x86_pmu.late_ack = true; | |
6113 | memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); | |
6114 | memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); | |
6115 | ||
6116 | x86_pmu.event_constraints = intel_spr_event_constraints; | |
6117 | x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; | |
6118 | x86_pmu.extra_regs = intel_spr_extra_regs; | |
6119 | x86_pmu.limit_period = spr_limit_period; | |
6120 | x86_pmu.pebs_aliases = NULL; | |
6121 | x86_pmu.pebs_prec_dist = true; | |
6122 | x86_pmu.pebs_block = true; | |
6123 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
6124 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
6125 | x86_pmu.flags |= PMU_FL_PEBS_ALL; | |
6126 | x86_pmu.flags |= PMU_FL_INSTR_LATENCY; | |
6127 | x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; | |
6128 | ||
6129 | x86_pmu.hw_config = hsw_hw_config; | |
6130 | x86_pmu.get_event_constraints = spr_get_event_constraints; | |
6131 | extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? | |
6132 | hsw_format_attr : nhm_format_attr; | |
6133 | extra_skl_attr = skl_format_attr; | |
6134 | mem_attr = spr_events_attrs; | |
6135 | td_attr = spr_td_events_attrs; | |
6136 | tsx_attr = spr_tsx_events_attrs; | |
6137 | x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); | |
6138 | x86_pmu.lbr_pt_coexist = true; | |
6139 | intel_pmu_pebs_data_source_skl(pmem); | |
6140 | x86_pmu.num_topdown_events = 8; | |
6141 | x86_pmu.update_topdown_event = icl_update_topdown_event; | |
6142 | x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; | |
6143 | pr_cont("Sapphire Rapids events, "); | |
6144 | name = "sapphire_rapids"; | |
6145 | break; | |
6146 | ||
f83d2f91 KL |
6147 | case INTEL_FAM6_ALDERLAKE: |
6148 | case INTEL_FAM6_ALDERLAKE_L: | |
6149 | /* | |
6150 | * Alder Lake has 2 types of CPU, core and atom. | |
6151 | * | |
6152 | * Initialize the common PerfMon capabilities here. | |
6153 | */ | |
6154 | x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, | |
6155 | sizeof(struct x86_hybrid_pmu), | |
6156 | GFP_KERNEL); | |
6157 | if (!x86_pmu.hybrid_pmu) | |
6158 | return -ENOMEM; | |
6159 | static_branch_enable(&perf_is_hybrid); | |
6160 | x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; | |
6161 | ||
f83d2f91 KL |
6162 | x86_pmu.pebs_aliases = NULL; |
6163 | x86_pmu.pebs_prec_dist = true; | |
6164 | x86_pmu.pebs_block = true; | |
6165 | x86_pmu.flags |= PMU_FL_HAS_RSP_1; | |
6166 | x86_pmu.flags |= PMU_FL_NO_HT_SHARING; | |
6167 | x86_pmu.flags |= PMU_FL_PEBS_ALL; | |
6168 | x86_pmu.flags |= PMU_FL_INSTR_LATENCY; | |
6169 | x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; | |
6170 | x86_pmu.lbr_pt_coexist = true; | |
6171 | intel_pmu_pebs_data_source_skl(false); | |
6172 | x86_pmu.num_topdown_events = 8; | |
6173 | x86_pmu.update_topdown_event = adl_update_topdown_event; | |
6174 | x86_pmu.set_topdown_event_period = adl_set_topdown_event_period; | |
6175 | ||
6176 | x86_pmu.filter_match = intel_pmu_filter_match; | |
6177 | x86_pmu.get_event_constraints = adl_get_event_constraints; | |
6178 | x86_pmu.hw_config = adl_hw_config; | |
6179 | x86_pmu.limit_period = spr_limit_period; | |
6180 | x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; | |
6181 | /* | |
6182 | * The rtm_abort_event is used to check whether to enable GPRs | |
6183 | * for the RTM abort event. Atom doesn't have the RTM abort | |
6184 | * event. There is no harmful to set it in the common | |
6185 | * x86_pmu.rtm_abort_event. | |
6186 | */ | |
6187 | x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); | |
6188 | ||
6189 | td_attr = adl_hybrid_events_attrs; | |
6190 | mem_attr = adl_hybrid_mem_attrs; | |
6191 | tsx_attr = adl_hybrid_tsx_attrs; | |
6192 | extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? | |
6193 | adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; | |
6194 | ||
6195 | /* Initialize big core specific PerfMon capabilities.*/ | |
6196 | pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; | |
6197 | pmu->name = "cpu_core"; | |
6198 | pmu->cpu_type = hybrid_big; | |
acade637 | 6199 | pmu->late_ack = true; |
ee72a94e KL |
6200 | if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { |
6201 | pmu->num_counters = x86_pmu.num_counters + 2; | |
6202 | pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; | |
6203 | } else { | |
6204 | pmu->num_counters = x86_pmu.num_counters; | |
6205 | pmu->num_counters_fixed = x86_pmu.num_counters_fixed; | |
6206 | } | |
6c64f560 KL |
6207 | |
6208 | /* | |
6209 | * Quirk: For some Alder Lake machine, when all E-cores are disabled in | |
6210 | * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, | |
6211 | * the X86_FEATURE_HYBRID_CPU is still set. The above codes will | |
6212 | * mistakenly add extra counters for P-cores. Correct the number of | |
6213 | * counters here. | |
6214 | */ | |
6215 | if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) { | |
6216 | pmu->num_counters = x86_pmu.num_counters; | |
6217 | pmu->num_counters_fixed = x86_pmu.num_counters_fixed; | |
6218 | } | |
6219 | ||
f83d2f91 KL |
6220 | pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters); |
6221 | pmu->unconstrained = (struct event_constraint) | |
6222 | __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, | |
6223 | 0, pmu->num_counters, 0, 0); | |
6224 | pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; | |
6225 | pmu->intel_cap.perf_metrics = 1; | |
6226 | pmu->intel_cap.pebs_output_pt_available = 0; | |
6227 | ||
6228 | memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); | |
6229 | memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); | |
6230 | pmu->event_constraints = intel_spr_event_constraints; | |
6231 | pmu->pebs_constraints = intel_spr_pebs_event_constraints; | |
6232 | pmu->extra_regs = intel_spr_extra_regs; | |
6233 | ||
6234 | /* Initialize Atom core specific PerfMon capabilities.*/ | |
6235 | pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; | |
6236 | pmu->name = "cpu_atom"; | |
6237 | pmu->cpu_type = hybrid_small; | |
acade637 | 6238 | pmu->mid_ack = true; |
f83d2f91 KL |
6239 | pmu->num_counters = x86_pmu.num_counters; |
6240 | pmu->num_counters_fixed = x86_pmu.num_counters_fixed; | |
6241 | pmu->max_pebs_events = x86_pmu.max_pebs_events; | |
6242 | pmu->unconstrained = (struct event_constraint) | |
6243 | __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1, | |
6244 | 0, pmu->num_counters, 0, 0); | |
6245 | pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; | |
6246 | pmu->intel_cap.perf_metrics = 0; | |
6247 | pmu->intel_cap.pebs_output_pt_available = 1; | |
6248 | ||
6249 | memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids)); | |
6250 | memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs)); | |
6251 | pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; | |
6252 | pmu->event_constraints = intel_slm_event_constraints; | |
6253 | pmu->pebs_constraints = intel_grt_pebs_event_constraints; | |
6254 | pmu->extra_regs = intel_grt_extra_regs; | |
6255 | pr_cont("Alderlake Hybrid events, "); | |
6256 | name = "alderlake_hybrid"; | |
6257 | break; | |
6258 | ||
f22f54f4 | 6259 | default: |
0af3ac1f AK |
6260 | switch (x86_pmu.version) { |
6261 | case 1: | |
6262 | x86_pmu.event_constraints = intel_v1_event_constraints; | |
6263 | pr_cont("generic architected perfmon v1, "); | |
b00233b5 | 6264 | name = "generic_arch_v1"; |
0af3ac1f AK |
6265 | break; |
6266 | default: | |
6267 | /* | |
6268 | * default constraints for v2 and up | |
6269 | */ | |
6270 | x86_pmu.event_constraints = intel_gen_event_constraints; | |
6271 | pr_cont("generic architected perfmon, "); | |
b00233b5 | 6272 | name = "generic_arch_v2+"; |
0af3ac1f AK |
6273 | break; |
6274 | } | |
f22f54f4 | 6275 | } |
ffb871bc | 6276 | |
0e96f31e | 6277 | snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); |
b00233b5 | 6278 | |
58ae30c2 KL |
6279 | if (!is_hybrid()) { |
6280 | group_events_td.attrs = td_attr; | |
6281 | group_events_mem.attrs = mem_attr; | |
6282 | group_events_tsx.attrs = tsx_attr; | |
6283 | group_format_extra.attrs = extra_attr; | |
6284 | group_format_extra_skl.attrs = extra_skl_attr; | |
a5df70c3 | 6285 | |
58ae30c2 KL |
6286 | x86_pmu.attr_update = attr_update; |
6287 | } else { | |
6288 | hybrid_group_events_td.attrs = td_attr; | |
6289 | hybrid_group_events_mem.attrs = mem_attr; | |
6290 | hybrid_group_events_tsx.attrs = tsx_attr; | |
6291 | hybrid_group_format_extra.attrs = extra_attr; | |
a1eac7ac | 6292 | |
58ae30c2 | 6293 | x86_pmu.attr_update = hybrid_attr_update; |
a1eac7ac RR |
6294 | } |
6295 | ||
b8c4d1a8 KL |
6296 | intel_pmu_check_num_counters(&x86_pmu.num_counters, |
6297 | &x86_pmu.num_counters_fixed, | |
6298 | &x86_pmu.intel_ctrl, | |
6299 | (u64)fixed_mask); | |
a1eac7ac | 6300 | |
cadbaa03 SE |
6301 | /* AnyThread may be deprecated on arch perfmon v5 or later */ |
6302 | if (x86_pmu.intel_cap.anythread_deprecated) | |
6303 | x86_pmu.format_attrs = intel_arch_formats_attr; | |
6304 | ||
bc14fe1b KL |
6305 | intel_pmu_check_event_constraints(x86_pmu.event_constraints, |
6306 | x86_pmu.num_counters, | |
6307 | x86_pmu.num_counters_fixed, | |
6308 | x86_pmu.intel_ctrl); | |
338b522c KL |
6309 | /* |
6310 | * Access LBR MSR may cause #GP under certain circumstances. | |
6311 | * E.g. KVM doesn't support LBR MSR | |
6312 | * Check all LBT MSR here. | |
6313 | * Disable LBR access if any LBR MSRs can not be accessed. | |
6314 | */ | |
3317c26a | 6315 | if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) |
338b522c KL |
6316 | x86_pmu.lbr_nr = 0; |
6317 | for (i = 0; i < x86_pmu.lbr_nr; i++) { | |
6318 | if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && | |
6319 | check_msr(x86_pmu.lbr_to + i, 0xffffUL))) | |
6320 | x86_pmu.lbr_nr = 0; | |
6321 | } | |
6322 | ||
1f157286 | 6323 | if (x86_pmu.lbr_nr) |
f09509b9 | 6324 | pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); |
b00233b5 | 6325 | |
34d5b61f | 6326 | intel_pmu_check_extra_regs(x86_pmu.extra_regs); |
338b522c | 6327 | |
069e0c3c AK |
6328 | /* Support full width counters using alternative MSR range */ |
6329 | if (x86_pmu.intel_cap.full_width_write) { | |
7f612a7f | 6330 | x86_pmu.max_period = x86_pmu.cntval_mask >> 1; |
069e0c3c AK |
6331 | x86_pmu.perfctr = MSR_IA32_PMC0; |
6332 | pr_cont("full-width counters, "); | |
6333 | } | |
6334 | ||
d0946a88 | 6335 | if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) |
59a854e2 KL |
6336 | x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; |
6337 | ||
d9977c43 KL |
6338 | if (is_hybrid()) |
6339 | intel_pmu_check_hybrid_pmus((u64)fixed_mask); | |
6340 | ||
f22f54f4 PZ |
6341 | return 0; |
6342 | } | |
b37609c3 SE |
6343 | |
6344 | /* | |
6345 | * HT bug: phase 2 init | |
6346 | * Called once we have valid topology information to check | |
6347 | * whether or not HT is enabled | |
6348 | * If HT is off, then we disable the workaround | |
6349 | */ | |
6350 | static __init int fixup_ht_bug(void) | |
6351 | { | |
030ba6cd | 6352 | int c; |
b37609c3 SE |
6353 | /* |
6354 | * problem not present on this CPU model, nothing to do | |
6355 | */ | |
6356 | if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) | |
6357 | return 0; | |
6358 | ||
030ba6cd | 6359 | if (topology_max_smt_threads() > 1) { |
b37609c3 SE |
6360 | pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); |
6361 | return 0; | |
6362 | } | |
6363 | ||
2406e3b1 PZ |
6364 | cpus_read_lock(); |
6365 | ||
6366 | hardlockup_detector_perf_stop(); | |
b37609c3 SE |
6367 | |
6368 | x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); | |
6369 | ||
b37609c3 | 6370 | x86_pmu.start_scheduling = NULL; |
0c41e756 | 6371 | x86_pmu.commit_scheduling = NULL; |
b37609c3 SE |
6372 | x86_pmu.stop_scheduling = NULL; |
6373 | ||
2406e3b1 | 6374 | hardlockup_detector_perf_restart(); |
b37609c3 | 6375 | |
1ba143a5 | 6376 | for_each_online_cpu(c) |
d01b1f96 | 6377 | free_excl_cntrs(&per_cpu(cpu_hw_events, c)); |
b37609c3 | 6378 | |
1ba143a5 | 6379 | cpus_read_unlock(); |
b37609c3 SE |
6380 | pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); |
6381 | return 0; | |
6382 | } | |
6383 | subsys_initcall(fixup_ht_bug) |