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Commit | Line | Data |
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de0428a7 KW |
1 | #include <linux/bitops.h> |
2 | #include <linux/types.h> | |
3 | #include <linux/slab.h> | |
ca037701 | 4 | |
569dedbb | 5 | #include <asm/cpu_entry_area.h> |
de0428a7 | 6 | #include <asm/perf_event.h> |
9e273276 | 7 | #include <asm/tlbflush.h> |
3e702ff6 | 8 | #include <asm/insn.h> |
de0428a7 | 9 | |
27f6d22b | 10 | #include "../perf_event.h" |
ca037701 | 11 | |
4b9996f9 TG |
12 | /* Waste a full page so it can be mapped into the cpu_entry_area */ |
13 | DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); | |
14 | ||
ca037701 PZ |
15 | /* The size of a BTS record in bytes: */ |
16 | #define BTS_RECORD_SIZE 24 | |
17 | ||
9536c8d2 | 18 | #define PEBS_FIXUP_SIZE PAGE_SIZE |
ca037701 PZ |
19 | |
20 | /* | |
21 | * pebs_record_32 for p4 and core not supported | |
22 | ||
23 | struct pebs_record_32 { | |
24 | u32 flags, ip; | |
25 | u32 ax, bc, cx, dx; | |
26 | u32 si, di, bp, sp; | |
27 | }; | |
28 | ||
29 | */ | |
30 | ||
f20093ee SE |
31 | union intel_x86_pebs_dse { |
32 | u64 val; | |
33 | struct { | |
34 | unsigned int ld_dse:4; | |
35 | unsigned int ld_stlb_miss:1; | |
36 | unsigned int ld_locked:1; | |
37 | unsigned int ld_reserved:26; | |
38 | }; | |
39 | struct { | |
40 | unsigned int st_l1d_hit:1; | |
41 | unsigned int st_reserved1:3; | |
42 | unsigned int st_stlb_miss:1; | |
43 | unsigned int st_locked:1; | |
44 | unsigned int st_reserved2:26; | |
45 | }; | |
46 | }; | |
47 | ||
48 | ||
49 | /* | |
50 | * Map PEBS Load Latency Data Source encodings to generic | |
51 | * memory data source information | |
52 | */ | |
53 | #define P(a, b) PERF_MEM_S(a, b) | |
54 | #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) | |
39ae1ca8 AK |
55 | #define LEVEL(x) P(LVLNUM, x) |
56 | #define REM P(REMOTE, REMOTE) | |
f20093ee SE |
57 | #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) |
58 | ||
e17dc653 AK |
59 | /* Version for Sandy Bridge and later */ |
60 | static u64 pebs_data_source[] = { | |
39ae1ca8 AK |
61 | P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ |
62 | OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ | |
63 | OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ | |
64 | OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ | |
65 | OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ | |
66 | OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ | |
67 | OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ | |
68 | OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ | |
69 | OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ | |
70 | OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ | |
71 | OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ | |
72 | OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ | |
73 | OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */ | |
74 | OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */ | |
75 | OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */ | |
76 | OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */ | |
f20093ee SE |
77 | }; |
78 | ||
e17dc653 AK |
79 | /* Patch up minor differences in the bits */ |
80 | void __init intel_pmu_pebs_data_source_nhm(void) | |
81 | { | |
39ae1ca8 AK |
82 | pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); |
83 | pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); | |
84 | pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); | |
85 | } | |
86 | ||
87 | void __init intel_pmu_pebs_data_source_skl(bool pmem) | |
88 | { | |
89 | u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); | |
90 | ||
91 | pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT); | |
92 | pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); | |
93 | pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); | |
94 | pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); | |
95 | pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); | |
e17dc653 AK |
96 | } |
97 | ||
9ad64c0f SE |
98 | static u64 precise_store_data(u64 status) |
99 | { | |
100 | union intel_x86_pebs_dse dse; | |
101 | u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); | |
102 | ||
103 | dse.val = status; | |
104 | ||
105 | /* | |
106 | * bit 4: TLB access | |
107 | * 1 = stored missed 2nd level TLB | |
108 | * | |
109 | * so it either hit the walker or the OS | |
110 | * otherwise hit 2nd level TLB | |
111 | */ | |
112 | if (dse.st_stlb_miss) | |
113 | val |= P(TLB, MISS); | |
114 | else | |
115 | val |= P(TLB, HIT); | |
116 | ||
117 | /* | |
118 | * bit 0: hit L1 data cache | |
119 | * if not set, then all we know is that | |
120 | * it missed L1D | |
121 | */ | |
122 | if (dse.st_l1d_hit) | |
123 | val |= P(LVL, HIT); | |
124 | else | |
125 | val |= P(LVL, MISS); | |
126 | ||
127 | /* | |
128 | * bit 5: Locked prefix | |
129 | */ | |
130 | if (dse.st_locked) | |
131 | val |= P(LOCK, LOCKED); | |
132 | ||
133 | return val; | |
134 | } | |
135 | ||
c8aab2e0 | 136 | static u64 precise_datala_hsw(struct perf_event *event, u64 status) |
f9134f36 AK |
137 | { |
138 | union perf_mem_data_src dse; | |
139 | ||
770eee1f SE |
140 | dse.val = PERF_MEM_NA; |
141 | ||
142 | if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) | |
143 | dse.mem_op = PERF_MEM_OP_STORE; | |
144 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) | |
145 | dse.mem_op = PERF_MEM_OP_LOAD; | |
722e76e6 SE |
146 | |
147 | /* | |
148 | * L1 info only valid for following events: | |
149 | * | |
150 | * MEM_UOPS_RETIRED.STLB_MISS_STORES | |
151 | * MEM_UOPS_RETIRED.LOCK_STORES | |
152 | * MEM_UOPS_RETIRED.SPLIT_STORES | |
153 | * MEM_UOPS_RETIRED.ALL_STORES | |
154 | */ | |
c8aab2e0 SE |
155 | if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { |
156 | if (status & 1) | |
157 | dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; | |
158 | else | |
159 | dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; | |
160 | } | |
f9134f36 AK |
161 | return dse.val; |
162 | } | |
163 | ||
f20093ee SE |
164 | static u64 load_latency_data(u64 status) |
165 | { | |
166 | union intel_x86_pebs_dse dse; | |
167 | u64 val; | |
f20093ee SE |
168 | |
169 | dse.val = status; | |
170 | ||
171 | /* | |
172 | * use the mapping table for bit 0-3 | |
173 | */ | |
174 | val = pebs_data_source[dse.ld_dse]; | |
175 | ||
176 | /* | |
177 | * Nehalem models do not support TLB, Lock infos | |
178 | */ | |
f473bf9c | 179 | if (x86_pmu.pebs_no_tlb) { |
f20093ee SE |
180 | val |= P(TLB, NA) | P(LOCK, NA); |
181 | return val; | |
182 | } | |
183 | /* | |
184 | * bit 4: TLB access | |
185 | * 0 = did not miss 2nd level TLB | |
186 | * 1 = missed 2nd level TLB | |
187 | */ | |
188 | if (dse.ld_stlb_miss) | |
189 | val |= P(TLB, MISS) | P(TLB, L2); | |
190 | else | |
191 | val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); | |
192 | ||
193 | /* | |
194 | * bit 5: locked prefix | |
195 | */ | |
196 | if (dse.ld_locked) | |
197 | val |= P(LOCK, LOCKED); | |
198 | ||
199 | return val; | |
200 | } | |
201 | ||
ca037701 PZ |
202 | struct pebs_record_core { |
203 | u64 flags, ip; | |
204 | u64 ax, bx, cx, dx; | |
205 | u64 si, di, bp, sp; | |
206 | u64 r8, r9, r10, r11; | |
207 | u64 r12, r13, r14, r15; | |
208 | }; | |
209 | ||
210 | struct pebs_record_nhm { | |
211 | u64 flags, ip; | |
212 | u64 ax, bx, cx, dx; | |
213 | u64 si, di, bp, sp; | |
214 | u64 r8, r9, r10, r11; | |
215 | u64 r12, r13, r14, r15; | |
216 | u64 status, dla, dse, lat; | |
217 | }; | |
218 | ||
130768b8 AK |
219 | /* |
220 | * Same as pebs_record_nhm, with two additional fields. | |
221 | */ | |
222 | struct pebs_record_hsw { | |
748e86aa AK |
223 | u64 flags, ip; |
224 | u64 ax, bx, cx, dx; | |
225 | u64 si, di, bp, sp; | |
226 | u64 r8, r9, r10, r11; | |
227 | u64 r12, r13, r14, r15; | |
228 | u64 status, dla, dse, lat; | |
d2beea4a | 229 | u64 real_ip, tsx_tuning; |
748e86aa AK |
230 | }; |
231 | ||
232 | union hsw_tsx_tuning { | |
233 | struct { | |
234 | u32 cycles_last_block : 32, | |
235 | hle_abort : 1, | |
236 | rtm_abort : 1, | |
237 | instruction_abort : 1, | |
238 | non_instruction_abort : 1, | |
239 | retry : 1, | |
240 | data_conflict : 1, | |
241 | capacity_writes : 1, | |
242 | capacity_reads : 1; | |
243 | }; | |
244 | u64 value; | |
130768b8 AK |
245 | }; |
246 | ||
a405bad5 AK |
247 | #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL |
248 | ||
2f7ebf2e AK |
249 | /* Same as HSW, plus TSC */ |
250 | ||
251 | struct pebs_record_skl { | |
252 | u64 flags, ip; | |
253 | u64 ax, bx, cx, dx; | |
254 | u64 si, di, bp, sp; | |
255 | u64 r8, r9, r10, r11; | |
256 | u64 r12, r13, r14, r15; | |
257 | u64 status, dla, dse, lat; | |
258 | u64 real_ip, tsx_tuning; | |
259 | u64 tsc; | |
260 | }; | |
261 | ||
de0428a7 | 262 | void init_debug_store_on_cpu(int cpu) |
ca037701 PZ |
263 | { |
264 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; | |
265 | ||
266 | if (!ds) | |
267 | return; | |
268 | ||
269 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, | |
270 | (u32)((u64)(unsigned long)ds), | |
271 | (u32)((u64)(unsigned long)ds >> 32)); | |
272 | } | |
273 | ||
de0428a7 | 274 | void fini_debug_store_on_cpu(int cpu) |
ca037701 PZ |
275 | { |
276 | if (!per_cpu(cpu_hw_events, cpu).ds) | |
277 | return; | |
278 | ||
279 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); | |
280 | } | |
281 | ||
9536c8d2 PZ |
282 | static DEFINE_PER_CPU(void *, insn_buffer); |
283 | ||
569dedbb | 284 | static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot) |
5ee25c87 | 285 | { |
9e273276 | 286 | unsigned long start = (unsigned long)cea; |
569dedbb HD |
287 | phys_addr_t pa; |
288 | size_t msz = 0; | |
289 | ||
290 | pa = virt_to_phys(addr); | |
9e273276 PZ |
291 | |
292 | preempt_disable(); | |
569dedbb HD |
293 | for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE) |
294 | cea_set_pte(cea, pa, prot); | |
9e273276 PZ |
295 | |
296 | /* | |
297 | * This is a cross-CPU update of the cpu_entry_area, we must shoot down | |
298 | * all TLB entries for it. | |
299 | */ | |
300 | flush_tlb_kernel_range(start, start + size); | |
301 | preempt_enable(); | |
569dedbb HD |
302 | } |
303 | ||
304 | static void ds_clear_cea(void *cea, size_t size) | |
305 | { | |
9e273276 | 306 | unsigned long start = (unsigned long)cea; |
569dedbb HD |
307 | size_t msz = 0; |
308 | ||
9e273276 | 309 | preempt_disable(); |
569dedbb HD |
310 | for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE) |
311 | cea_set_pte(cea, 0, PAGE_NONE); | |
9e273276 PZ |
312 | |
313 | flush_tlb_kernel_range(start, start + size); | |
314 | preempt_enable(); | |
569dedbb HD |
315 | } |
316 | ||
317 | static void *dsalloc_pages(size_t size, gfp_t flags, int cpu) | |
318 | { | |
319 | unsigned int order = get_order(size); | |
96681fc3 | 320 | int node = cpu_to_node(cpu); |
569dedbb HD |
321 | struct page *page; |
322 | ||
323 | page = __alloc_pages_node(node, flags | __GFP_ZERO, order); | |
324 | return page ? page_address(page) : NULL; | |
325 | } | |
326 | ||
327 | static void dsfree_pages(const void *buffer, size_t size) | |
328 | { | |
329 | if (buffer) | |
330 | free_pages((unsigned long)buffer, get_order(size)); | |
331 | } | |
332 | ||
333 | static int alloc_pebs_buffer(int cpu) | |
334 | { | |
335 | struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); | |
336 | struct debug_store *ds = hwev->ds; | |
337 | size_t bsiz = x86_pmu.pebs_buffer_size; | |
338 | int max, node = cpu_to_node(cpu); | |
339 | void *buffer, *ibuffer, *cea; | |
5ee25c87 PZ |
340 | |
341 | if (!x86_pmu.pebs) | |
342 | return 0; | |
343 | ||
569dedbb | 344 | buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu); |
5ee25c87 PZ |
345 | if (unlikely(!buffer)) |
346 | return -ENOMEM; | |
347 | ||
9536c8d2 PZ |
348 | /* |
349 | * HSW+ already provides us the eventing ip; no need to allocate this | |
350 | * buffer then. | |
351 | */ | |
352 | if (x86_pmu.intel_cap.pebs_format < 2) { | |
353 | ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); | |
354 | if (!ibuffer) { | |
569dedbb | 355 | dsfree_pages(buffer, bsiz); |
9536c8d2 PZ |
356 | return -ENOMEM; |
357 | } | |
358 | per_cpu(insn_buffer, cpu) = ibuffer; | |
359 | } | |
569dedbb HD |
360 | hwev->ds_pebs_vaddr = buffer; |
361 | /* Update the cpu entry area mapping */ | |
362 | cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; | |
363 | ds->pebs_buffer_base = (unsigned long) cea; | |
364 | ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL); | |
5ee25c87 | 365 | ds->pebs_index = ds->pebs_buffer_base; |
569dedbb HD |
366 | max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); |
367 | ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; | |
5ee25c87 PZ |
368 | return 0; |
369 | } | |
370 | ||
b39f88ac PZ |
371 | static void release_pebs_buffer(int cpu) |
372 | { | |
569dedbb HD |
373 | struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); |
374 | struct debug_store *ds = hwev->ds; | |
375 | void *cea; | |
b39f88ac PZ |
376 | |
377 | if (!ds || !x86_pmu.pebs) | |
378 | return; | |
379 | ||
9536c8d2 PZ |
380 | kfree(per_cpu(insn_buffer, cpu)); |
381 | per_cpu(insn_buffer, cpu) = NULL; | |
382 | ||
569dedbb HD |
383 | /* Clear the fixmap */ |
384 | cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; | |
385 | ds_clear_cea(cea, x86_pmu.pebs_buffer_size); | |
b39f88ac | 386 | ds->pebs_buffer_base = 0; |
569dedbb HD |
387 | dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); |
388 | hwev->ds_pebs_vaddr = NULL; | |
b39f88ac PZ |
389 | } |
390 | ||
5ee25c87 PZ |
391 | static int alloc_bts_buffer(int cpu) |
392 | { | |
569dedbb HD |
393 | struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); |
394 | struct debug_store *ds = hwev->ds; | |
395 | void *buffer, *cea; | |
396 | int max; | |
5ee25c87 PZ |
397 | |
398 | if (!x86_pmu.bts) | |
399 | return 0; | |
400 | ||
569dedbb | 401 | buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu); |
44851541 DR |
402 | if (unlikely(!buffer)) { |
403 | WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); | |
5ee25c87 | 404 | return -ENOMEM; |
44851541 | 405 | } |
569dedbb HD |
406 | hwev->ds_bts_vaddr = buffer; |
407 | /* Update the fixmap */ | |
408 | cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; | |
409 | ds->bts_buffer_base = (unsigned long) cea; | |
410 | ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL); | |
5ee25c87 | 411 | ds->bts_index = ds->bts_buffer_base; |
569dedbb HD |
412 | max = BTS_RECORD_SIZE * (BTS_BUFFER_SIZE / BTS_RECORD_SIZE); |
413 | ds->bts_absolute_maximum = ds->bts_buffer_base + max; | |
414 | ds->bts_interrupt_threshold = ds->bts_absolute_maximum - (max / 16); | |
5ee25c87 PZ |
415 | return 0; |
416 | } | |
417 | ||
b39f88ac PZ |
418 | static void release_bts_buffer(int cpu) |
419 | { | |
569dedbb HD |
420 | struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); |
421 | struct debug_store *ds = hwev->ds; | |
422 | void *cea; | |
b39f88ac PZ |
423 | |
424 | if (!ds || !x86_pmu.bts) | |
425 | return; | |
426 | ||
569dedbb HD |
427 | /* Clear the fixmap */ |
428 | cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; | |
429 | ds_clear_cea(cea, BTS_BUFFER_SIZE); | |
b39f88ac | 430 | ds->bts_buffer_base = 0; |
569dedbb HD |
431 | dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); |
432 | hwev->ds_bts_vaddr = NULL; | |
b39f88ac PZ |
433 | } |
434 | ||
65af94ba PZ |
435 | static int alloc_ds_buffer(int cpu) |
436 | { | |
569dedbb | 437 | struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; |
65af94ba | 438 | |
569dedbb | 439 | memset(ds, 0, sizeof(*ds)); |
65af94ba | 440 | per_cpu(cpu_hw_events, cpu).ds = ds; |
65af94ba PZ |
441 | return 0; |
442 | } | |
443 | ||
444 | static void release_ds_buffer(int cpu) | |
445 | { | |
65af94ba | 446 | per_cpu(cpu_hw_events, cpu).ds = NULL; |
65af94ba PZ |
447 | } |
448 | ||
de0428a7 | 449 | void release_ds_buffers(void) |
ca037701 PZ |
450 | { |
451 | int cpu; | |
452 | ||
453 | if (!x86_pmu.bts && !x86_pmu.pebs) | |
454 | return; | |
455 | ||
456 | get_online_cpus(); | |
ca037701 PZ |
457 | for_each_online_cpu(cpu) |
458 | fini_debug_store_on_cpu(cpu); | |
459 | ||
460 | for_each_possible_cpu(cpu) { | |
b39f88ac PZ |
461 | release_pebs_buffer(cpu); |
462 | release_bts_buffer(cpu); | |
65af94ba | 463 | release_ds_buffer(cpu); |
ca037701 | 464 | } |
ca037701 PZ |
465 | put_online_cpus(); |
466 | } | |
467 | ||
de0428a7 | 468 | void reserve_ds_buffers(void) |
ca037701 | 469 | { |
6809b6ea PZ |
470 | int bts_err = 0, pebs_err = 0; |
471 | int cpu; | |
472 | ||
473 | x86_pmu.bts_active = 0; | |
474 | x86_pmu.pebs_active = 0; | |
ca037701 PZ |
475 | |
476 | if (!x86_pmu.bts && !x86_pmu.pebs) | |
f80c9e30 | 477 | return; |
ca037701 | 478 | |
6809b6ea PZ |
479 | if (!x86_pmu.bts) |
480 | bts_err = 1; | |
481 | ||
482 | if (!x86_pmu.pebs) | |
483 | pebs_err = 1; | |
484 | ||
ca037701 PZ |
485 | get_online_cpus(); |
486 | ||
487 | for_each_possible_cpu(cpu) { | |
6809b6ea PZ |
488 | if (alloc_ds_buffer(cpu)) { |
489 | bts_err = 1; | |
490 | pebs_err = 1; | |
491 | } | |
ca037701 | 492 | |
6809b6ea PZ |
493 | if (!bts_err && alloc_bts_buffer(cpu)) |
494 | bts_err = 1; | |
495 | ||
496 | if (!pebs_err && alloc_pebs_buffer(cpu)) | |
497 | pebs_err = 1; | |
5ee25c87 | 498 | |
6809b6ea | 499 | if (bts_err && pebs_err) |
5ee25c87 | 500 | break; |
6809b6ea PZ |
501 | } |
502 | ||
503 | if (bts_err) { | |
504 | for_each_possible_cpu(cpu) | |
505 | release_bts_buffer(cpu); | |
506 | } | |
ca037701 | 507 | |
6809b6ea PZ |
508 | if (pebs_err) { |
509 | for_each_possible_cpu(cpu) | |
510 | release_pebs_buffer(cpu); | |
ca037701 PZ |
511 | } |
512 | ||
6809b6ea PZ |
513 | if (bts_err && pebs_err) { |
514 | for_each_possible_cpu(cpu) | |
515 | release_ds_buffer(cpu); | |
516 | } else { | |
517 | if (x86_pmu.bts && !bts_err) | |
518 | x86_pmu.bts_active = 1; | |
519 | ||
520 | if (x86_pmu.pebs && !pebs_err) | |
521 | x86_pmu.pebs_active = 1; | |
522 | ||
ca037701 PZ |
523 | for_each_online_cpu(cpu) |
524 | init_debug_store_on_cpu(cpu); | |
525 | } | |
526 | ||
527 | put_online_cpus(); | |
ca037701 PZ |
528 | } |
529 | ||
530 | /* | |
531 | * BTS | |
532 | */ | |
533 | ||
de0428a7 | 534 | struct event_constraint bts_constraint = |
15c7ad51 | 535 | EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); |
ca037701 | 536 | |
de0428a7 | 537 | void intel_pmu_enable_bts(u64 config) |
ca037701 PZ |
538 | { |
539 | unsigned long debugctlmsr; | |
540 | ||
541 | debugctlmsr = get_debugctlmsr(); | |
542 | ||
7c5ecaf7 PZ |
543 | debugctlmsr |= DEBUGCTLMSR_TR; |
544 | debugctlmsr |= DEBUGCTLMSR_BTS; | |
8062382c AS |
545 | if (config & ARCH_PERFMON_EVENTSEL_INT) |
546 | debugctlmsr |= DEBUGCTLMSR_BTINT; | |
ca037701 PZ |
547 | |
548 | if (!(config & ARCH_PERFMON_EVENTSEL_OS)) | |
7c5ecaf7 | 549 | debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; |
ca037701 PZ |
550 | |
551 | if (!(config & ARCH_PERFMON_EVENTSEL_USR)) | |
7c5ecaf7 | 552 | debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; |
ca037701 PZ |
553 | |
554 | update_debugctlmsr(debugctlmsr); | |
555 | } | |
556 | ||
de0428a7 | 557 | void intel_pmu_disable_bts(void) |
ca037701 | 558 | { |
89cbc767 | 559 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
560 | unsigned long debugctlmsr; |
561 | ||
562 | if (!cpuc->ds) | |
563 | return; | |
564 | ||
565 | debugctlmsr = get_debugctlmsr(); | |
566 | ||
567 | debugctlmsr &= | |
7c5ecaf7 PZ |
568 | ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | |
569 | DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); | |
ca037701 PZ |
570 | |
571 | update_debugctlmsr(debugctlmsr); | |
572 | } | |
573 | ||
de0428a7 | 574 | int intel_pmu_drain_bts_buffer(void) |
ca037701 | 575 | { |
89cbc767 | 576 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
577 | struct debug_store *ds = cpuc->ds; |
578 | struct bts_record { | |
579 | u64 from; | |
580 | u64 to; | |
581 | u64 flags; | |
582 | }; | |
15c7ad51 | 583 | struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
a09d31f4 | 584 | struct bts_record *at, *base, *top; |
ca037701 PZ |
585 | struct perf_output_handle handle; |
586 | struct perf_event_header header; | |
587 | struct perf_sample_data data; | |
a09d31f4 | 588 | unsigned long skip = 0; |
ca037701 PZ |
589 | struct pt_regs regs; |
590 | ||
591 | if (!event) | |
b0b2072d | 592 | return 0; |
ca037701 | 593 | |
6809b6ea | 594 | if (!x86_pmu.bts_active) |
b0b2072d | 595 | return 0; |
ca037701 | 596 | |
a09d31f4 AS |
597 | base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; |
598 | top = (struct bts_record *)(unsigned long)ds->bts_index; | |
ca037701 | 599 | |
a09d31f4 | 600 | if (top <= base) |
b0b2072d | 601 | return 0; |
ca037701 | 602 | |
0e48026a SE |
603 | memset(®s, 0, sizeof(regs)); |
604 | ||
ca037701 PZ |
605 | ds->bts_index = ds->bts_buffer_base; |
606 | ||
fd0d000b | 607 | perf_sample_data_init(&data, 0, event->hw.last_period); |
ca037701 | 608 | |
a09d31f4 AS |
609 | /* |
610 | * BTS leaks kernel addresses in branches across the cpl boundary, | |
611 | * such as traps or system calls, so unless the user is asking for | |
612 | * kernel tracing (and right now it's not possible), we'd need to | |
613 | * filter them out. But first we need to count how many of those we | |
614 | * have in the current batch. This is an extra O(n) pass, however, | |
615 | * it's much faster than the other one especially considering that | |
616 | * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the | |
617 | * alloc_bts_buffer()). | |
618 | */ | |
619 | for (at = base; at < top; at++) { | |
620 | /* | |
621 | * Note that right now *this* BTS code only works if | |
622 | * attr::exclude_kernel is set, but let's keep this extra | |
623 | * check here in case that changes. | |
624 | */ | |
625 | if (event->attr.exclude_kernel && | |
626 | (kernel_ip(at->from) || kernel_ip(at->to))) | |
627 | skip++; | |
628 | } | |
629 | ||
ca037701 PZ |
630 | /* |
631 | * Prepare a generic sample, i.e. fill in the invariant fields. | |
632 | * We will overwrite the from and to address before we output | |
633 | * the sample. | |
634 | */ | |
e8d8a90f | 635 | rcu_read_lock(); |
ca037701 PZ |
636 | perf_prepare_sample(&header, &data, event, ®s); |
637 | ||
a09d31f4 AS |
638 | if (perf_output_begin(&handle, event, header.size * |
639 | (top - base - skip))) | |
e8d8a90f | 640 | goto unlock; |
ca037701 | 641 | |
a09d31f4 AS |
642 | for (at = base; at < top; at++) { |
643 | /* Filter out any records that contain kernel addresses. */ | |
644 | if (event->attr.exclude_kernel && | |
645 | (kernel_ip(at->from) || kernel_ip(at->to))) | |
646 | continue; | |
647 | ||
ca037701 PZ |
648 | data.ip = at->from; |
649 | data.addr = at->to; | |
650 | ||
651 | perf_output_sample(&handle, &header, &data, event); | |
652 | } | |
653 | ||
654 | perf_output_end(&handle); | |
655 | ||
656 | /* There's new data available. */ | |
657 | event->hw.interrupts++; | |
658 | event->pending_kill = POLL_IN; | |
e8d8a90f PZ |
659 | unlock: |
660 | rcu_read_unlock(); | |
b0b2072d | 661 | return 1; |
ca037701 PZ |
662 | } |
663 | ||
9c964efa YZ |
664 | static inline void intel_pmu_drain_pebs_buffer(void) |
665 | { | |
666 | struct pt_regs regs; | |
667 | ||
668 | x86_pmu.drain_pebs(®s); | |
669 | } | |
670 | ||
ca037701 PZ |
671 | /* |
672 | * PEBS | |
673 | */ | |
de0428a7 | 674 | struct event_constraint intel_core2_pebs_event_constraints[] = { |
af4bdcf6 AK |
675 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ |
676 | INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ | |
677 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ | |
678 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ | |
679 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ | |
517e6341 PZ |
680 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
681 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), | |
ca037701 PZ |
682 | EVENT_CONSTRAINT_END |
683 | }; | |
684 | ||
de0428a7 | 685 | struct event_constraint intel_atom_pebs_event_constraints[] = { |
af4bdcf6 AK |
686 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ |
687 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ | |
688 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ | |
517e6341 PZ |
689 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
690 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), | |
673d188b SE |
691 | /* Allow all events as PEBS with no flags */ |
692 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), | |
17e31629 SE |
693 | EVENT_CONSTRAINT_END |
694 | }; | |
695 | ||
1fa64180 | 696 | struct event_constraint intel_slm_pebs_event_constraints[] = { |
33636732 KL |
697 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
698 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), | |
86a04461 AK |
699 | /* Allow all events as PEBS with no flags */ |
700 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), | |
1fa64180 YZ |
701 | EVENT_CONSTRAINT_END |
702 | }; | |
703 | ||
8b92c3a7 KL |
704 | struct event_constraint intel_glm_pebs_event_constraints[] = { |
705 | /* Allow all events as PEBS with no flags */ | |
706 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), | |
707 | EVENT_CONSTRAINT_END | |
708 | }; | |
709 | ||
dd0b06b5 KL |
710 | struct event_constraint intel_glp_pebs_event_constraints[] = { |
711 | /* Allow all events as PEBS with no flags */ | |
712 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
713 | EVENT_CONSTRAINT_END | |
714 | }; | |
715 | ||
de0428a7 | 716 | struct event_constraint intel_nehalem_pebs_event_constraints[] = { |
f20093ee | 717 | INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ |
af4bdcf6 AK |
718 | INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ |
719 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ | |
720 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ | |
7d5d02da | 721 | INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ |
af4bdcf6 AK |
722 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ |
723 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ | |
724 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ | |
725 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ | |
726 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ | |
727 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ | |
517e6341 PZ |
728 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
729 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), | |
17e31629 SE |
730 | EVENT_CONSTRAINT_END |
731 | }; | |
732 | ||
de0428a7 | 733 | struct event_constraint intel_westmere_pebs_event_constraints[] = { |
f20093ee | 734 | INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ |
af4bdcf6 AK |
735 | INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ |
736 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ | |
737 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ | |
7d5d02da | 738 | INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ |
af4bdcf6 AK |
739 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ |
740 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ | |
741 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ | |
742 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ | |
743 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ | |
744 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ | |
517e6341 PZ |
745 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
746 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), | |
ca037701 PZ |
747 | EVENT_CONSTRAINT_END |
748 | }; | |
749 | ||
de0428a7 | 750 | struct event_constraint intel_snb_pebs_event_constraints[] = { |
0dbc9479 | 751 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
f20093ee | 752 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
9ad64c0f | 753 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
86a04461 AK |
754 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
755 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | |
b63b4b45 MD |
756 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ |
757 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
758 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
759 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
86a04461 AK |
760 | /* Allow all events as PEBS with no flags */ |
761 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
b06b3d49 LM |
762 | EVENT_CONSTRAINT_END |
763 | }; | |
764 | ||
20a36e39 | 765 | struct event_constraint intel_ivb_pebs_event_constraints[] = { |
0dbc9479 | 766 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
f20093ee | 767 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
9ad64c0f | 768 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
86a04461 AK |
769 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
770 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | |
72469764 AK |
771 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ |
772 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), | |
b63b4b45 MD |
773 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ |
774 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
775 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ | |
776 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ | |
86a04461 AK |
777 | /* Allow all events as PEBS with no flags */ |
778 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
20a36e39 SE |
779 | EVENT_CONSTRAINT_END |
780 | }; | |
781 | ||
3044318f | 782 | struct event_constraint intel_hsw_pebs_event_constraints[] = { |
0dbc9479 | 783 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
86a04461 AK |
784 | INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ |
785 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ | |
786 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | |
72469764 AK |
787 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ |
788 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), | |
86a04461 | 789 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ |
b63b4b45 MD |
790 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ |
791 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ | |
792 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ | |
793 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
794 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ | |
795 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ | |
796 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ | |
797 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
798 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ | |
799 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ | |
9a92e16f AK |
800 | /* Allow all events as PEBS with no flags */ |
801 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
802 | EVENT_CONSTRAINT_END | |
803 | }; | |
804 | ||
b3e62463 SE |
805 | struct event_constraint intel_bdw_pebs_event_constraints[] = { |
806 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ | |
807 | INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ | |
808 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ | |
809 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), | |
810 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ | |
811 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), | |
812 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ | |
813 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ | |
814 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ | |
815 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ | |
816 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ | |
817 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ | |
818 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ | |
819 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ | |
820 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ | |
821 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ | |
822 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ | |
823 | /* Allow all events as PEBS with no flags */ | |
824 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
825 | EVENT_CONSTRAINT_END | |
826 | }; | |
827 | ||
828 | ||
9a92e16f AK |
829 | struct event_constraint intel_skl_pebs_event_constraints[] = { |
830 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ | |
72469764 AK |
831 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ |
832 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), | |
442f5c74 AK |
833 | /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */ |
834 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), | |
9a92e16f AK |
835 | INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */ |
836 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ | |
837 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ | |
838 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ | |
839 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */ | |
840 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ | |
841 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ | |
842 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ | |
843 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ | |
844 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ | |
845 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ | |
846 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */ | |
86a04461 AK |
847 | /* Allow all events as PEBS with no flags */ |
848 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), | |
3044318f AK |
849 | EVENT_CONSTRAINT_END |
850 | }; | |
851 | ||
de0428a7 | 852 | struct event_constraint *intel_pebs_constraints(struct perf_event *event) |
ca037701 PZ |
853 | { |
854 | struct event_constraint *c; | |
855 | ||
ab608344 | 856 | if (!event->attr.precise_ip) |
ca037701 PZ |
857 | return NULL; |
858 | ||
859 | if (x86_pmu.pebs_constraints) { | |
860 | for_each_event_constraint(c, x86_pmu.pebs_constraints) { | |
9fac2cf3 SE |
861 | if ((event->hw.config & c->cmask) == c->code) { |
862 | event->hw.flags |= c->flags; | |
ca037701 | 863 | return c; |
9fac2cf3 | 864 | } |
ca037701 PZ |
865 | } |
866 | } | |
867 | ||
868 | return &emptyconstraint; | |
869 | } | |
870 | ||
09e61b4f PZ |
871 | /* |
872 | * We need the sched_task callback even for per-cpu events when we use | |
873 | * the large interrupt threshold, such that we can provide PID and TID | |
874 | * to PEBS samples. | |
875 | */ | |
876 | static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc) | |
877 | { | |
878 | return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); | |
879 | } | |
880 | ||
df6c3db8 JO |
881 | void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in) |
882 | { | |
883 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
884 | ||
885 | if (!sched_in && pebs_needs_sched_cb(cpuc)) | |
886 | intel_pmu_drain_pebs_buffer(); | |
887 | } | |
888 | ||
09e61b4f PZ |
889 | static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) |
890 | { | |
891 | struct debug_store *ds = cpuc->ds; | |
892 | u64 threshold; | |
893 | ||
894 | if (cpuc->n_pebs == cpuc->n_large_pebs) { | |
895 | threshold = ds->pebs_absolute_maximum - | |
896 | x86_pmu.max_pebs_events * x86_pmu.pebs_record_size; | |
897 | } else { | |
898 | threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size; | |
899 | } | |
900 | ||
901 | ds->pebs_interrupt_threshold = threshold; | |
902 | } | |
903 | ||
904 | static void | |
905 | pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu) | |
906 | { | |
b6a32f02 JO |
907 | /* |
908 | * Make sure we get updated with the first PEBS | |
909 | * event. It will trigger also during removal, but | |
910 | * that does not hurt: | |
911 | */ | |
912 | bool update = cpuc->n_pebs == 1; | |
913 | ||
09e61b4f PZ |
914 | if (needed_cb != pebs_needs_sched_cb(cpuc)) { |
915 | if (!needed_cb) | |
916 | perf_sched_cb_inc(pmu); | |
917 | else | |
918 | perf_sched_cb_dec(pmu); | |
919 | ||
b6a32f02 | 920 | update = true; |
09e61b4f | 921 | } |
b6a32f02 JO |
922 | |
923 | if (update) | |
924 | pebs_update_threshold(cpuc); | |
09e61b4f PZ |
925 | } |
926 | ||
68f7082f | 927 | void intel_pmu_pebs_add(struct perf_event *event) |
3569c0d7 | 928 | { |
09e61b4f PZ |
929 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
930 | struct hw_perf_event *hwc = &event->hw; | |
931 | bool needed_cb = pebs_needs_sched_cb(cpuc); | |
932 | ||
933 | cpuc->n_pebs++; | |
934 | if (hwc->flags & PERF_X86_EVENT_FREERUNNING) | |
935 | cpuc->n_large_pebs++; | |
936 | ||
937 | pebs_update_state(needed_cb, cpuc, event->ctx->pmu); | |
3569c0d7 YZ |
938 | } |
939 | ||
de0428a7 | 940 | void intel_pmu_pebs_enable(struct perf_event *event) |
ca037701 | 941 | { |
89cbc767 | 942 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ef21f683 | 943 | struct hw_perf_event *hwc = &event->hw; |
851559e3 | 944 | struct debug_store *ds = cpuc->ds; |
09e61b4f | 945 | |
ca037701 PZ |
946 | hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; |
947 | ||
ad0e6cfe | 948 | cpuc->pebs_enabled |= 1ULL << hwc->idx; |
f20093ee SE |
949 | |
950 | if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) | |
951 | cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); | |
9ad64c0f SE |
952 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) |
953 | cpuc->pebs_enabled |= 1ULL << 63; | |
851559e3 | 954 | |
3569c0d7 | 955 | /* |
09e61b4f PZ |
956 | * Use auto-reload if possible to save a MSR write in the PMI. |
957 | * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD. | |
3569c0d7 | 958 | */ |
851559e3 YZ |
959 | if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { |
960 | ds->pebs_event_reset[hwc->idx] = | |
961 | (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; | |
dc853e26 JO |
962 | } else { |
963 | ds->pebs_event_reset[hwc->idx] = 0; | |
851559e3 | 964 | } |
09e61b4f PZ |
965 | } |
966 | ||
68f7082f | 967 | void intel_pmu_pebs_del(struct perf_event *event) |
09e61b4f PZ |
968 | { |
969 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
970 | struct hw_perf_event *hwc = &event->hw; | |
971 | bool needed_cb = pebs_needs_sched_cb(cpuc); | |
972 | ||
973 | cpuc->n_pebs--; | |
974 | if (hwc->flags & PERF_X86_EVENT_FREERUNNING) | |
975 | cpuc->n_large_pebs--; | |
3569c0d7 | 976 | |
09e61b4f | 977 | pebs_update_state(needed_cb, cpuc, event->ctx->pmu); |
ca037701 PZ |
978 | } |
979 | ||
de0428a7 | 980 | void intel_pmu_pebs_disable(struct perf_event *event) |
ca037701 | 981 | { |
89cbc767 | 982 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ef21f683 | 983 | struct hw_perf_event *hwc = &event->hw; |
2a853e11 | 984 | |
09e61b4f | 985 | if (cpuc->n_pebs == cpuc->n_large_pebs) |
2a853e11 | 986 | intel_pmu_drain_pebs_buffer(); |
ca037701 | 987 | |
ad0e6cfe | 988 | cpuc->pebs_enabled &= ~(1ULL << hwc->idx); |
983433b5 | 989 | |
b371b594 | 990 | if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) |
983433b5 | 991 | cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); |
b371b594 | 992 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) |
983433b5 SE |
993 | cpuc->pebs_enabled &= ~(1ULL << 63); |
994 | ||
4807e3d5 | 995 | if (cpuc->enabled) |
ad0e6cfe | 996 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); |
ca037701 PZ |
997 | |
998 | hwc->config |= ARCH_PERFMON_EVENTSEL_INT; | |
999 | } | |
1000 | ||
de0428a7 | 1001 | void intel_pmu_pebs_enable_all(void) |
ca037701 | 1002 | { |
89cbc767 | 1003 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
1004 | |
1005 | if (cpuc->pebs_enabled) | |
1006 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); | |
1007 | } | |
1008 | ||
de0428a7 | 1009 | void intel_pmu_pebs_disable_all(void) |
ca037701 | 1010 | { |
89cbc767 | 1011 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
1012 | |
1013 | if (cpuc->pebs_enabled) | |
1014 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
1015 | } | |
1016 | ||
ef21f683 PZ |
1017 | static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) |
1018 | { | |
89cbc767 | 1019 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ef21f683 PZ |
1020 | unsigned long from = cpuc->lbr_entries[0].from; |
1021 | unsigned long old_to, to = cpuc->lbr_entries[0].to; | |
1022 | unsigned long ip = regs->ip; | |
57d1c0c0 | 1023 | int is_64bit = 0; |
9536c8d2 | 1024 | void *kaddr; |
6ba48ff4 | 1025 | int size; |
ef21f683 | 1026 | |
8db909a7 PZ |
1027 | /* |
1028 | * We don't need to fixup if the PEBS assist is fault like | |
1029 | */ | |
1030 | if (!x86_pmu.intel_cap.pebs_trap) | |
1031 | return 1; | |
1032 | ||
a562b187 PZ |
1033 | /* |
1034 | * No LBR entry, no basic block, no rewinding | |
1035 | */ | |
ef21f683 PZ |
1036 | if (!cpuc->lbr_stack.nr || !from || !to) |
1037 | return 0; | |
1038 | ||
a562b187 PZ |
1039 | /* |
1040 | * Basic blocks should never cross user/kernel boundaries | |
1041 | */ | |
1042 | if (kernel_ip(ip) != kernel_ip(to)) | |
1043 | return 0; | |
1044 | ||
1045 | /* | |
1046 | * unsigned math, either ip is before the start (impossible) or | |
1047 | * the basic block is larger than 1 page (sanity) | |
1048 | */ | |
9536c8d2 | 1049 | if ((ip - to) > PEBS_FIXUP_SIZE) |
ef21f683 PZ |
1050 | return 0; |
1051 | ||
1052 | /* | |
1053 | * We sampled a branch insn, rewind using the LBR stack | |
1054 | */ | |
1055 | if (ip == to) { | |
d07bdfd3 | 1056 | set_linear_ip(regs, from); |
ef21f683 PZ |
1057 | return 1; |
1058 | } | |
1059 | ||
6ba48ff4 | 1060 | size = ip - to; |
9536c8d2 | 1061 | if (!kernel_ip(ip)) { |
6ba48ff4 | 1062 | int bytes; |
9536c8d2 PZ |
1063 | u8 *buf = this_cpu_read(insn_buffer); |
1064 | ||
6ba48ff4 | 1065 | /* 'size' must fit our buffer, see above */ |
9536c8d2 | 1066 | bytes = copy_from_user_nmi(buf, (void __user *)to, size); |
0a196848 | 1067 | if (bytes != 0) |
9536c8d2 PZ |
1068 | return 0; |
1069 | ||
1070 | kaddr = buf; | |
1071 | } else { | |
1072 | kaddr = (void *)to; | |
1073 | } | |
1074 | ||
ef21f683 PZ |
1075 | do { |
1076 | struct insn insn; | |
ef21f683 PZ |
1077 | |
1078 | old_to = to; | |
ef21f683 | 1079 | |
57d1c0c0 PZ |
1080 | #ifdef CONFIG_X86_64 |
1081 | is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32); | |
1082 | #endif | |
6ba48ff4 | 1083 | insn_init(&insn, kaddr, size, is_64bit); |
ef21f683 | 1084 | insn_get_length(&insn); |
6ba48ff4 DH |
1085 | /* |
1086 | * Make sure there was not a problem decoding the | |
1087 | * instruction and getting the length. This is | |
1088 | * doubly important because we have an infinite | |
1089 | * loop if insn.length=0. | |
1090 | */ | |
1091 | if (!insn.length) | |
1092 | break; | |
9536c8d2 | 1093 | |
ef21f683 | 1094 | to += insn.length; |
9536c8d2 | 1095 | kaddr += insn.length; |
6ba48ff4 | 1096 | size -= insn.length; |
ef21f683 PZ |
1097 | } while (to < ip); |
1098 | ||
1099 | if (to == ip) { | |
d07bdfd3 | 1100 | set_linear_ip(regs, old_to); |
ef21f683 PZ |
1101 | return 1; |
1102 | } | |
1103 | ||
a562b187 PZ |
1104 | /* |
1105 | * Even though we decoded the basic block, the instruction stream | |
1106 | * never matched the given IP, either the TO or the IP got corrupted. | |
1107 | */ | |
ef21f683 PZ |
1108 | return 0; |
1109 | } | |
1110 | ||
2f7ebf2e | 1111 | static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs) |
748e86aa AK |
1112 | { |
1113 | if (pebs->tsx_tuning) { | |
1114 | union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning }; | |
1115 | return tsx.cycles_last_block; | |
1116 | } | |
1117 | return 0; | |
1118 | } | |
1119 | ||
2f7ebf2e | 1120 | static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs) |
a405bad5 AK |
1121 | { |
1122 | u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; | |
1123 | ||
1124 | /* For RTM XABORTs also log the abort code from AX */ | |
1125 | if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) | |
1126 | txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; | |
1127 | return txn; | |
1128 | } | |
1129 | ||
43cf7631 YZ |
1130 | static void setup_pebs_sample_data(struct perf_event *event, |
1131 | struct pt_regs *iregs, void *__pebs, | |
1132 | struct perf_sample_data *data, | |
1133 | struct pt_regs *regs) | |
2b0b5c6f | 1134 | { |
c8aab2e0 SE |
1135 | #define PERF_X86_EVENT_PEBS_HSW_PREC \ |
1136 | (PERF_X86_EVENT_PEBS_ST_HSW | \ | |
1137 | PERF_X86_EVENT_PEBS_LD_HSW | \ | |
1138 | PERF_X86_EVENT_PEBS_NA_HSW) | |
2b0b5c6f | 1139 | /* |
d2beea4a PZ |
1140 | * We cast to the biggest pebs_record but are careful not to |
1141 | * unconditionally access the 'extra' entries. | |
2b0b5c6f | 1142 | */ |
89cbc767 | 1143 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2f7ebf2e | 1144 | struct pebs_record_skl *pebs = __pebs; |
f20093ee | 1145 | u64 sample_type; |
c8aab2e0 SE |
1146 | int fll, fst, dsrc; |
1147 | int fl = event->hw.flags; | |
2b0b5c6f | 1148 | |
21509084 YZ |
1149 | if (pebs == NULL) |
1150 | return; | |
1151 | ||
c8aab2e0 SE |
1152 | sample_type = event->attr.sample_type; |
1153 | dsrc = sample_type & PERF_SAMPLE_DATA_SRC; | |
1154 | ||
1155 | fll = fl & PERF_X86_EVENT_PEBS_LDLAT; | |
1156 | fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); | |
f20093ee | 1157 | |
43cf7631 | 1158 | perf_sample_data_init(data, 0, event->hw.last_period); |
2b0b5c6f | 1159 | |
43cf7631 | 1160 | data->period = event->hw.last_period; |
f20093ee SE |
1161 | |
1162 | /* | |
c8aab2e0 | 1163 | * Use latency for weight (only avail with PEBS-LL) |
f20093ee | 1164 | */ |
c8aab2e0 | 1165 | if (fll && (sample_type & PERF_SAMPLE_WEIGHT)) |
43cf7631 | 1166 | data->weight = pebs->lat; |
c8aab2e0 SE |
1167 | |
1168 | /* | |
1169 | * data.data_src encodes the data source | |
1170 | */ | |
1171 | if (dsrc) { | |
1172 | u64 val = PERF_MEM_NA; | |
1173 | if (fll) | |
1174 | val = load_latency_data(pebs->dse); | |
1175 | else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) | |
1176 | val = precise_datala_hsw(event, pebs->dse); | |
1177 | else if (fst) | |
1178 | val = precise_store_data(pebs->dse); | |
43cf7631 | 1179 | data->data_src.val = val; |
f20093ee SE |
1180 | } |
1181 | ||
2b0b5c6f | 1182 | /* |
b8000586 PZ |
1183 | * We use the interrupt regs as a base because the PEBS record does not |
1184 | * contain a full regs set, specifically it seems to lack segment | |
1185 | * descriptors, which get used by things like user_mode(). | |
2b0b5c6f | 1186 | * |
b8000586 PZ |
1187 | * In the simple case fix up only the IP for PERF_SAMPLE_IP. |
1188 | * | |
1189 | * We must however always use BP,SP from iregs for the unwinder to stay | |
1190 | * sane; the record BP,SP can point into thin air when the record is | |
1191 | * from a previous PMI context or an (I)RET happend between the record | |
1192 | * and PMI. | |
2b0b5c6f | 1193 | */ |
43cf7631 YZ |
1194 | *regs = *iregs; |
1195 | regs->flags = pebs->flags; | |
1196 | set_linear_ip(regs, pebs->ip); | |
2b0b5c6f | 1197 | |
aea48559 | 1198 | if (sample_type & PERF_SAMPLE_REGS_INTR) { |
43cf7631 YZ |
1199 | regs->ax = pebs->ax; |
1200 | regs->bx = pebs->bx; | |
1201 | regs->cx = pebs->cx; | |
1202 | regs->dx = pebs->dx; | |
1203 | regs->si = pebs->si; | |
1204 | regs->di = pebs->di; | |
43cf7631 | 1205 | |
b8000586 PZ |
1206 | /* |
1207 | * Per the above; only set BP,SP if we don't need callchains. | |
1208 | * | |
1209 | * XXX: does this make sense? | |
1210 | */ | |
1211 | if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) { | |
1212 | regs->bp = pebs->bp; | |
1213 | regs->sp = pebs->sp; | |
1214 | } | |
1215 | ||
1216 | /* | |
1217 | * Preserve PERF_EFLAGS_VM from set_linear_ip(). | |
1218 | */ | |
1219 | regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM); | |
aea48559 | 1220 | #ifndef CONFIG_X86_32 |
43cf7631 YZ |
1221 | regs->r8 = pebs->r8; |
1222 | regs->r9 = pebs->r9; | |
1223 | regs->r10 = pebs->r10; | |
1224 | regs->r11 = pebs->r11; | |
1225 | regs->r12 = pebs->r12; | |
1226 | regs->r13 = pebs->r13; | |
1227 | regs->r14 = pebs->r14; | |
1228 | regs->r15 = pebs->r15; | |
aea48559 SE |
1229 | #endif |
1230 | } | |
1231 | ||
130768b8 | 1232 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) { |
43cf7631 YZ |
1233 | regs->ip = pebs->real_ip; |
1234 | regs->flags |= PERF_EFLAGS_EXACT; | |
1235 | } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs)) | |
1236 | regs->flags |= PERF_EFLAGS_EXACT; | |
2b0b5c6f | 1237 | else |
43cf7631 | 1238 | regs->flags &= ~PERF_EFLAGS_EXACT; |
2b0b5c6f | 1239 | |
c8aab2e0 | 1240 | if ((sample_type & PERF_SAMPLE_ADDR) && |
d2beea4a | 1241 | x86_pmu.intel_cap.pebs_format >= 1) |
43cf7631 | 1242 | data->addr = pebs->dla; |
f9134f36 | 1243 | |
a405bad5 AK |
1244 | if (x86_pmu.intel_cap.pebs_format >= 2) { |
1245 | /* Only set the TSX weight when no memory weight. */ | |
c8aab2e0 | 1246 | if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) |
43cf7631 | 1247 | data->weight = intel_hsw_weight(pebs); |
a405bad5 | 1248 | |
c8aab2e0 | 1249 | if (sample_type & PERF_SAMPLE_TRANSACTION) |
43cf7631 | 1250 | data->txn = intel_hsw_transaction(pebs); |
a405bad5 | 1251 | } |
748e86aa | 1252 | |
2f7ebf2e AK |
1253 | /* |
1254 | * v3 supplies an accurate time stamp, so we use that | |
1255 | * for the time stamp. | |
1256 | * | |
1257 | * We can only do this for the default trace clock. | |
1258 | */ | |
1259 | if (x86_pmu.intel_cap.pebs_format >= 3 && | |
1260 | event->attr.use_clockid == 0) | |
1261 | data->time = native_sched_clock_from_tsc(pebs->tsc); | |
1262 | ||
60ce0fbd | 1263 | if (has_branch_stack(event)) |
43cf7631 YZ |
1264 | data->br_stack = &cpuc->lbr_stack; |
1265 | } | |
1266 | ||
21509084 YZ |
1267 | static inline void * |
1268 | get_next_pebs_record_by_bit(void *base, void *top, int bit) | |
1269 | { | |
1270 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
1271 | void *at; | |
1272 | u64 pebs_status; | |
1273 | ||
1424a09a SE |
1274 | /* |
1275 | * fmt0 does not have a status bitfield (does not use | |
1276 | * perf_record_nhm format) | |
1277 | */ | |
1278 | if (x86_pmu.intel_cap.pebs_format < 1) | |
1279 | return base; | |
1280 | ||
21509084 YZ |
1281 | if (base == NULL) |
1282 | return NULL; | |
1283 | ||
1284 | for (at = base; at < top; at += x86_pmu.pebs_record_size) { | |
1285 | struct pebs_record_nhm *p = at; | |
1286 | ||
1287 | if (test_bit(bit, (unsigned long *)&p->status)) { | |
a3d86542 PZ |
1288 | /* PEBS v3 has accurate status bits */ |
1289 | if (x86_pmu.intel_cap.pebs_format >= 3) | |
1290 | return at; | |
21509084 YZ |
1291 | |
1292 | if (p->status == (1 << bit)) | |
1293 | return at; | |
1294 | ||
1295 | /* clear non-PEBS bit and re-check */ | |
1296 | pebs_status = p->status & cpuc->pebs_enabled; | |
fd583ad1 | 1297 | pebs_status &= PEBS_COUNTER_MASK; |
21509084 YZ |
1298 | if (pebs_status == (1 << bit)) |
1299 | return at; | |
1300 | } | |
1301 | } | |
1302 | return NULL; | |
1303 | } | |
1304 | ||
43cf7631 | 1305 | static void __intel_pmu_pebs_event(struct perf_event *event, |
21509084 YZ |
1306 | struct pt_regs *iregs, |
1307 | void *base, void *top, | |
1308 | int bit, int count) | |
43cf7631 YZ |
1309 | { |
1310 | struct perf_sample_data data; | |
1311 | struct pt_regs regs; | |
21509084 | 1312 | void *at = get_next_pebs_record_by_bit(base, top, bit); |
43cf7631 | 1313 | |
21509084 YZ |
1314 | if (!intel_pmu_save_and_restart(event) && |
1315 | !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)) | |
43cf7631 YZ |
1316 | return; |
1317 | ||
a3d86542 PZ |
1318 | while (count > 1) { |
1319 | setup_pebs_sample_data(event, iregs, at, &data, ®s); | |
1320 | perf_event_output(event, &data, ®s); | |
1321 | at += x86_pmu.pebs_record_size; | |
1322 | at = get_next_pebs_record_by_bit(at, top, bit); | |
1323 | count--; | |
21509084 YZ |
1324 | } |
1325 | ||
1326 | setup_pebs_sample_data(event, iregs, at, &data, ®s); | |
60ce0fbd | 1327 | |
21509084 YZ |
1328 | /* |
1329 | * All but the last records are processed. | |
1330 | * The last one is left to be able to call the overflow handler. | |
1331 | */ | |
1332 | if (perf_event_overflow(event, &data, ®s)) { | |
a4eaf7f1 | 1333 | x86_pmu_stop(event, 0); |
21509084 YZ |
1334 | return; |
1335 | } | |
1336 | ||
2b0b5c6f PZ |
1337 | } |
1338 | ||
ca037701 PZ |
1339 | static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) |
1340 | { | |
89cbc767 | 1341 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 PZ |
1342 | struct debug_store *ds = cpuc->ds; |
1343 | struct perf_event *event = cpuc->events[0]; /* PMC0 only */ | |
1344 | struct pebs_record_core *at, *top; | |
ca037701 PZ |
1345 | int n; |
1346 | ||
6809b6ea | 1347 | if (!x86_pmu.pebs_active) |
ca037701 PZ |
1348 | return; |
1349 | ||
ca037701 PZ |
1350 | at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; |
1351 | top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; | |
1352 | ||
d80c7502 PZ |
1353 | /* |
1354 | * Whatever else happens, drain the thing | |
1355 | */ | |
1356 | ds->pebs_index = ds->pebs_buffer_base; | |
1357 | ||
1358 | if (!test_bit(0, cpuc->active_mask)) | |
8f4aebd2 | 1359 | return; |
ca037701 | 1360 | |
d80c7502 PZ |
1361 | WARN_ON_ONCE(!event); |
1362 | ||
ab608344 | 1363 | if (!event->attr.precise_ip) |
d80c7502 PZ |
1364 | return; |
1365 | ||
1424a09a | 1366 | n = top - at; |
d80c7502 PZ |
1367 | if (n <= 0) |
1368 | return; | |
ca037701 | 1369 | |
21509084 | 1370 | __intel_pmu_pebs_event(event, iregs, at, top, 0, n); |
ca037701 PZ |
1371 | } |
1372 | ||
d2beea4a | 1373 | static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) |
ca037701 | 1374 | { |
89cbc767 | 1375 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
ca037701 | 1376 | struct debug_store *ds = cpuc->ds; |
21509084 YZ |
1377 | struct perf_event *event; |
1378 | void *base, *at, *top; | |
21509084 | 1379 | short counts[MAX_PEBS_EVENTS] = {}; |
f38b0dbb | 1380 | short error[MAX_PEBS_EVENTS] = {}; |
a3d86542 | 1381 | int bit, i; |
d2beea4a PZ |
1382 | |
1383 | if (!x86_pmu.pebs_active) | |
1384 | return; | |
1385 | ||
21509084 | 1386 | base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; |
d2beea4a | 1387 | top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; |
ca037701 | 1388 | |
ca037701 PZ |
1389 | ds->pebs_index = ds->pebs_buffer_base; |
1390 | ||
21509084 | 1391 | if (unlikely(base >= top)) |
d2beea4a PZ |
1392 | return; |
1393 | ||
21509084 | 1394 | for (at = base; at < top; at += x86_pmu.pebs_record_size) { |
130768b8 | 1395 | struct pebs_record_nhm *p = at; |
75f80859 | 1396 | u64 pebs_status; |
ca037701 | 1397 | |
8ef9b845 PZ |
1398 | pebs_status = p->status & cpuc->pebs_enabled; |
1399 | pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1; | |
1400 | ||
1401 | /* PEBS v3 has more accurate status bits */ | |
a3d86542 | 1402 | if (x86_pmu.intel_cap.pebs_format >= 3) { |
8ef9b845 PZ |
1403 | for_each_set_bit(bit, (unsigned long *)&pebs_status, |
1404 | x86_pmu.max_pebs_events) | |
a3d86542 PZ |
1405 | counts[bit]++; |
1406 | ||
1407 | continue; | |
1408 | } | |
1409 | ||
01330d72 AK |
1410 | /* |
1411 | * On some CPUs the PEBS status can be zero when PEBS is | |
1412 | * racing with clearing of GLOBAL_STATUS. | |
1413 | * | |
1414 | * Normally we would drop that record, but in the | |
1415 | * case when there is only a single active PEBS event | |
1416 | * we can assume it's for that event. | |
1417 | */ | |
1418 | if (!pebs_status && cpuc->pebs_enabled && | |
1419 | !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) | |
1420 | pebs_status = cpuc->pebs_enabled; | |
1421 | ||
75f80859 | 1422 | bit = find_first_bit((unsigned long *)&pebs_status, |
21509084 | 1423 | x86_pmu.max_pebs_events); |
957ea1fd | 1424 | if (bit >= x86_pmu.max_pebs_events) |
21509084 | 1425 | continue; |
75f80859 | 1426 | |
21509084 YZ |
1427 | /* |
1428 | * The PEBS hardware does not deal well with the situation | |
1429 | * when events happen near to each other and multiple bits | |
1430 | * are set. But it should happen rarely. | |
1431 | * | |
1432 | * If these events include one PEBS and multiple non-PEBS | |
1433 | * events, it doesn't impact PEBS record. The record will | |
1434 | * be handled normally. (slow path) | |
1435 | * | |
1436 | * If these events include two or more PEBS events, the | |
1437 | * records for the events can be collapsed into a single | |
1438 | * one, and it's not possible to reconstruct all events | |
1439 | * that caused the PEBS record. It's called collision. | |
1440 | * If collision happened, the record will be dropped. | |
21509084 | 1441 | */ |
75f80859 PZ |
1442 | if (p->status != (1ULL << bit)) { |
1443 | for_each_set_bit(i, (unsigned long *)&pebs_status, | |
1444 | x86_pmu.max_pebs_events) | |
1445 | error[i]++; | |
1446 | continue; | |
ca037701 | 1447 | } |
75f80859 | 1448 | |
21509084 YZ |
1449 | counts[bit]++; |
1450 | } | |
ca037701 | 1451 | |
21509084 | 1452 | for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) { |
f38b0dbb | 1453 | if ((counts[bit] == 0) && (error[bit] == 0)) |
ca037701 | 1454 | continue; |
75f80859 | 1455 | |
21509084 | 1456 | event = cpuc->events[bit]; |
8ef9b845 PZ |
1457 | if (WARN_ON_ONCE(!event)) |
1458 | continue; | |
1459 | ||
1460 | if (WARN_ON_ONCE(!event->attr.precise_ip)) | |
1461 | continue; | |
ca037701 | 1462 | |
f38b0dbb | 1463 | /* log dropped samples number */ |
475113d9 | 1464 | if (error[bit]) { |
f38b0dbb KL |
1465 | perf_log_lost_samples(event, error[bit]); |
1466 | ||
475113d9 JO |
1467 | if (perf_event_account_interrupt(event)) |
1468 | x86_pmu_stop(event, 0); | |
1469 | } | |
1470 | ||
f38b0dbb KL |
1471 | if (counts[bit]) { |
1472 | __intel_pmu_pebs_event(event, iregs, base, | |
1473 | top, bit, counts[bit]); | |
1474 | } | |
ca037701 | 1475 | } |
ca037701 PZ |
1476 | } |
1477 | ||
1478 | /* | |
1479 | * BTS, PEBS probe and setup | |
1480 | */ | |
1481 | ||
066ce64c | 1482 | void __init intel_ds_init(void) |
ca037701 PZ |
1483 | { |
1484 | /* | |
1485 | * No support for 32bit formats | |
1486 | */ | |
1487 | if (!boot_cpu_has(X86_FEATURE_DTES64)) | |
1488 | return; | |
1489 | ||
1490 | x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); | |
1491 | x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); | |
e72daf3f | 1492 | x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; |
ca037701 | 1493 | if (x86_pmu.pebs) { |
8db909a7 PZ |
1494 | char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; |
1495 | int format = x86_pmu.intel_cap.pebs_format; | |
ca037701 PZ |
1496 | |
1497 | switch (format) { | |
1498 | case 0: | |
1b74dde7 | 1499 | pr_cont("PEBS fmt0%c, ", pebs_type); |
ca037701 | 1500 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); |
e72daf3f JO |
1501 | /* |
1502 | * Using >PAGE_SIZE buffers makes the WRMSR to | |
1503 | * PERF_GLOBAL_CTRL in intel_pmu_enable_all() | |
1504 | * mysteriously hang on Core2. | |
1505 | * | |
1506 | * As a workaround, we don't do this. | |
1507 | */ | |
1508 | x86_pmu.pebs_buffer_size = PAGE_SIZE; | |
ca037701 | 1509 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; |
ca037701 PZ |
1510 | break; |
1511 | ||
1512 | case 1: | |
1b74dde7 | 1513 | pr_cont("PEBS fmt1%c, ", pebs_type); |
ca037701 PZ |
1514 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); |
1515 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; | |
ca037701 PZ |
1516 | break; |
1517 | ||
130768b8 AK |
1518 | case 2: |
1519 | pr_cont("PEBS fmt2%c, ", pebs_type); | |
1520 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); | |
d2beea4a | 1521 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; |
130768b8 AK |
1522 | break; |
1523 | ||
2f7ebf2e AK |
1524 | case 3: |
1525 | pr_cont("PEBS fmt3%c, ", pebs_type); | |
1526 | x86_pmu.pebs_record_size = | |
1527 | sizeof(struct pebs_record_skl); | |
1528 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; | |
a7b58d21 | 1529 | x86_pmu.free_running_flags |= PERF_SAMPLE_TIME; |
2f7ebf2e AK |
1530 | break; |
1531 | ||
ca037701 | 1532 | default: |
1b74dde7 | 1533 | pr_cont("no PEBS fmt%d%c, ", format, pebs_type); |
ca037701 | 1534 | x86_pmu.pebs = 0; |
ca037701 PZ |
1535 | } |
1536 | } | |
1537 | } | |
1d9d8639 SE |
1538 | |
1539 | void perf_restore_debug_store(void) | |
1540 | { | |
2a6e06b2 LT |
1541 | struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); |
1542 | ||
1d9d8639 SE |
1543 | if (!x86_pmu.bts && !x86_pmu.pebs) |
1544 | return; | |
1545 | ||
2a6e06b2 | 1546 | wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); |
1d9d8639 | 1547 | } |