[mirror_ubuntu-artful-kernel.git] / arch / x86 / events / intel / pt.h

/*
 * Intel(R) Processor Trace PMU driver for perf
 * Copyright (c) 2013-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
 * Programming Reference:
 * http://software.intel.com/en-us/intel-isa-extensions
 */

#ifndef __INTEL_PT_H__
#define __INTEL_PT_H__

/*
 * PT MSR bit definitions
 */
#define RTIT_CTL_TRACEEN		BIT(0)
#define RTIT_CTL_CYCLEACC		BIT(1)
#define RTIT_CTL_OS			BIT(2)
#define RTIT_CTL_USR			BIT(3)
#define RTIT_CTL_PWR_EVT_EN		BIT(4)
#define RTIT_CTL_FUP_ON_PTW		BIT(5)
#define RTIT_CTL_CR3EN			BIT(7)
#define RTIT_CTL_TOPA			BIT(8)
#define RTIT_CTL_MTC_EN			BIT(9)
#define RTIT_CTL_TSC_EN			BIT(10)
#define RTIT_CTL_DISRETC		BIT(11)
#define RTIT_CTL_PTW_EN			BIT(12)
#define RTIT_CTL_BRANCH_EN		BIT(13)
#define RTIT_CTL_MTC_RANGE_OFFSET	14
#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
#define RTIT_CTL_CYC_THRESH_OFFSET	19
#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
#define RTIT_CTL_PSB_FREQ_OFFSET	24
#define RTIT_CTL_PSB_FREQ      		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
#define RTIT_CTL_ADDR0_OFFSET		32
#define RTIT_CTL_ADDR0      		(0x0full << RTIT_CTL_ADDR0_OFFSET)
#define RTIT_CTL_ADDR1_OFFSET		36
#define RTIT_CTL_ADDR1      		(0x0full << RTIT_CTL_ADDR1_OFFSET)
#define RTIT_CTL_ADDR2_OFFSET		40
#define RTIT_CTL_ADDR2      		(0x0full << RTIT_CTL_ADDR2_OFFSET)
#define RTIT_CTL_ADDR3_OFFSET		44
#define RTIT_CTL_ADDR3      		(0x0full << RTIT_CTL_ADDR3_OFFSET)
#define RTIT_STATUS_FILTEREN		BIT(0)
#define RTIT_STATUS_CONTEXTEN		BIT(1)
#define RTIT_STATUS_TRIGGEREN		BIT(2)
#define RTIT_STATUS_BUFFOVF		BIT(3)
#define RTIT_STATUS_ERROR		BIT(4)
#define RTIT_STATUS_STOPPED		BIT(5)

/*
 * Single-entry ToPA: when this close to region boundary, switch
 * buffers to avoid losing data.
 */
#define TOPA_PMI_MARGIN 512

#define TOPA_SHIFT 12

static inline unsigned int sizes(unsigned int tsz)
{
	return 1 << (tsz + TOPA_SHIFT);
};

struct topa_entry {
	u64	end	: 1;
	u64	rsvd0	: 1;
	u64	intr	: 1;
	u64	rsvd1	: 1;
	u64	stop	: 1;
	u64	rsvd2	: 1;
	u64	size	: 4;
	u64	rsvd3	: 2;
	u64	base	: 36;
	u64	rsvd4	: 16;
};

#define PT_CPUID_LEAVES		2
#define PT_CPUID_REGS_NUM	4 /* number of regsters (eax, ebx, ecx, edx) */

/* TSC to Core Crystal Clock Ratio */
#define CPUID_TSC_LEAF		0x15

enum pt_capabilities {
	PT_CAP_max_subleaf = 0,
	PT_CAP_cr3_filtering,
	PT_CAP_psb_cyc,
	PT_CAP_ip_filtering,
	PT_CAP_mtc,
	PT_CAP_ptwrite,
	PT_CAP_power_event_trace,
	PT_CAP_topa_output,
	PT_CAP_topa_multiple_entries,
	PT_CAP_single_range_output,
	PT_CAP_payloads_lip,
	PT_CAP_num_address_ranges,
	PT_CAP_mtc_periods,
	PT_CAP_cycle_thresholds,
	PT_CAP_psb_periods,
};

struct pt_pmu {
	struct pmu		pmu;
	u32			caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
	bool			vmx;
	unsigned long		max_nonturbo_ratio;
	unsigned int		tsc_art_num;
	unsigned int		tsc_art_den;
};

/**
 * struct pt_buffer - buffer configuration; one buffer per task_struct or
 *		cpu, depending on perf event configuration
 * @cpu:	cpu for per-cpu allocation
 * @tables:	list of ToPA tables in this buffer
 * @first:	shorthand for first topa table
 * @last:	shorthand for last topa table
 * @cur:	current topa table
 * @nr_pages:	buffer size in pages
 * @cur_idx:	current output region's index within @cur table
 * @output_off:	offset within the current output region
 * @data_size:	running total of the amount of data in this buffer
 * @lost:	if data was lost/truncated
 * @head:	logical write offset inside the buffer
 * @snapshot:	if this is for a snapshot/overwrite counter
 * @stop_pos:	STOP topa entry in the buffer
 * @intr_pos:	INT topa entry in the buffer
 * @data_pages:	array of pages from perf
 * @topa_index:	table of topa entries indexed by page offset
 */
struct pt_buffer {
	int			cpu;
	struct list_head	tables;
	struct topa		*first, *last, *cur;
	unsigned int		cur_idx;
	size_t			output_off;
	unsigned long		nr_pages;
	local_t			data_size;
	local64_t		head;
	bool			snapshot;
	unsigned long		stop_pos, intr_pos;
	void			**data_pages;
	struct topa_entry	*topa_index[0];
};

#define PT_FILTERS_NUM	4

/**
 * struct pt_filter - IP range filter configuration
 * @msr_a:	range start, goes to RTIT_ADDRn_A
 * @msr_b:	range end, goes to RTIT_ADDRn_B
 * @config:	4-bit field in RTIT_CTL
 */
struct pt_filter {
	unsigned long	msr_a;
	unsigned long	msr_b;
	unsigned long	config;
};

/**
 * struct pt_filters - IP range filtering context
 * @filter:	filters defined for this context
 * @nr_filters:	number of defined filters in the @filter array
 */
struct pt_filters {
	struct pt_filter	filter[PT_FILTERS_NUM];
	unsigned int		nr_filters;
};

/**
 * struct pt - per-cpu pt context
 * @handle:	perf output handle
 * @filters:		last configured filters
 * @handle_nmi:	do handle PT PMI on this cpu, there's an active event
 * @vmx_on:	1 if VMX is ON on this cpu
 */
struct pt {
	struct perf_output_handle handle;
	struct pt_filters	filters;
	int			handle_nmi;
	int			vmx_on;
};

#endif /* __INTEL_PT_H__ */
Commit	Line	Data
52ca9ced AS	1	/*
	2	* Intel(R) Processor Trace PMU driver for perf
	3	* Copyright (c) 2013-2014, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* Intel PT is specified in the Intel Architecture Instruction Set Extensions
	15	* Programming Reference:
	16	* http://software.intel.com/en-us/intel-isa-extensions
	17	*/
	18
	19	#ifndef __INTEL_PT_H__
	20	#define __INTEL_PT_H__
	21
0dd28e2c AS	22	/*
	23	* PT MSR bit definitions
	24	*/
	25	#define RTIT_CTL_TRACEEN BIT(0)
	26	#define RTIT_CTL_CYCLEACC BIT(1)
	27	#define RTIT_CTL_OS BIT(2)
	28	#define RTIT_CTL_USR BIT(3)
8ee83b2a AS	29	#define RTIT_CTL_PWR_EVT_EN BIT(4)
8ee83b2a AS	30	#define RTIT_CTL_FUP_ON_PTW BIT(5)
0dd28e2c AS	31	#define RTIT_CTL_CR3EN BIT(7)
	32	#define RTIT_CTL_TOPA BIT(8)
	33	#define RTIT_CTL_MTC_EN BIT(9)
	34	#define RTIT_CTL_TSC_EN BIT(10)
	35	#define RTIT_CTL_DISRETC BIT(11)
8ee83b2a	36	#define RTIT_CTL_PTW_EN BIT(12)
0dd28e2c AS	37	#define RTIT_CTL_BRANCH_EN BIT(13)
	38	#define RTIT_CTL_MTC_RANGE_OFFSET 14
	39	#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
	40	#define RTIT_CTL_CYC_THRESH_OFFSET 19
	41	#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
	42	#define RTIT_CTL_PSB_FREQ_OFFSET 24
	43	#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
f127fa09 AS	44	#define RTIT_CTL_ADDR0_OFFSET 32
	45	#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
	46	#define RTIT_CTL_ADDR1_OFFSET 36
	47	#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
	48	#define RTIT_CTL_ADDR2_OFFSET 40
	49	#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
	50	#define RTIT_CTL_ADDR3_OFFSET 44
	51	#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
	52	#define RTIT_STATUS_FILTEREN BIT(0)
0dd28e2c AS	53	#define RTIT_STATUS_CONTEXTEN BIT(1)
0dd28e2c AS	54	#define RTIT_STATUS_TRIGGEREN BIT(2)
f127fa09	55	#define RTIT_STATUS_BUFFOVF BIT(3)
0dd28e2c AS	56	#define RTIT_STATUS_ERROR BIT(4)
	57	#define RTIT_STATUS_STOPPED BIT(5)
	58
52ca9ced AS	59	/*
	60	* Single-entry ToPA: when this close to region boundary, switch
	61	* buffers to avoid losing data.
	62	*/
	63	#define TOPA_PMI_MARGIN 512
	64
709bc871	65	#define TOPA_SHIFT 12
52ca9ced	66
709bc871	67	static inline unsigned int sizes(unsigned int tsz)
52ca9ced	68	{
709bc871	69	return 1 << (tsz + TOPA_SHIFT);
52ca9ced AS	70	};
	71
	72	struct topa_entry {
	73	u64 end : 1;
	74	u64 rsvd0 : 1;
	75	u64 intr : 1;
	76	u64 rsvd1 : 1;
	77	u64 stop : 1;
	78	u64 rsvd2 : 1;
	79	u64 size : 4;
	80	u64 rsvd3 : 2;
	81	u64 base : 36;
	82	u64 rsvd4 : 16;
	83	};
	84
709bc871 TI	85	#define PT_CPUID_LEAVES 2
709bc871 TI	86	#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
52ca9ced	87
65c7e6f1 AS	88	/* TSC to Core Crystal Clock Ratio */
	89	#define CPUID_TSC_LEAF 0x15
	90
52ca9ced AS	91	enum pt_capabilities {
	92	PT_CAP_max_subleaf = 0,
	93	PT_CAP_cr3_filtering,
b1bf72d6	94	PT_CAP_psb_cyc,
f127fa09	95	PT_CAP_ip_filtering,
b1bf72d6	96	PT_CAP_mtc,
8ee83b2a AS	97	PT_CAP_ptwrite,
8ee83b2a AS	98	PT_CAP_power_event_trace,
52ca9ced AS	99	PT_CAP_topa_output,
52ca9ced AS	100	PT_CAP_topa_multiple_entries,
b1bf72d6	101	PT_CAP_single_range_output,
52ca9ced	102	PT_CAP_payloads_lip,
f127fa09	103	PT_CAP_num_address_ranges,
b1bf72d6 AS	104	PT_CAP_mtc_periods,
	105	PT_CAP_cycle_thresholds,
	106	PT_CAP_psb_periods,
52ca9ced AS	107	};
	108
	109	struct pt_pmu {
	110	struct pmu pmu;
709bc871	111	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
1c5ac21a	112	bool vmx;
65c7e6f1 AS	113	unsigned long max_nonturbo_ratio;
	114	unsigned int tsc_art_num;
	115	unsigned int tsc_art_den;
52ca9ced AS	116	};
	117
	118	/**
	119	* struct pt_buffer - buffer configuration; one buffer per task_struct or
	120	* cpu, depending on perf event configuration
	121	* @cpu: cpu for per-cpu allocation
	122	* @tables: list of ToPA tables in this buffer
	123	* @first: shorthand for first topa table
	124	* @last: shorthand for last topa table
	125	* @cur: current topa table
	126	* @nr_pages: buffer size in pages
	127	* @cur_idx: current output region's index within @cur table
	128	* @output_off: offset within the current output region
	129	* @data_size: running total of the amount of data in this buffer
	130	* @lost: if data was lost/truncated
	131	* @head: logical write offset inside the buffer
	132	* @snapshot: if this is for a snapshot/overwrite counter
	133	* @stop_pos: STOP topa entry in the buffer
	134	* @intr_pos: INT topa entry in the buffer
	135	* @data_pages: array of pages from perf
	136	* @topa_index: table of topa entries indexed by page offset
	137	*/
	138	struct pt_buffer {
	139	int cpu;
	140	struct list_head tables;
	141	struct topa first, last, *cur;
	142	unsigned int cur_idx;
	143	size_t output_off;
	144	unsigned long nr_pages;
	145	local_t data_size;
52ca9ced AS	146	local64_t head;
	147	bool snapshot;
	148	unsigned long stop_pos, intr_pos;
	149	void **data_pages;
	150	struct topa_entry *topa_index[0];
	151	};
	152
eadf48ca AS	153	#define PT_FILTERS_NUM 4
	154
	155	/**
	156	* struct pt_filter - IP range filter configuration
	157	* @msr_a: range start, goes to RTIT_ADDRn_A
	158	* @msr_b: range end, goes to RTIT_ADDRn_B
	159	* @config: 4-bit field in RTIT_CTL
	160	*/
	161	struct pt_filter {
	162	unsigned long msr_a;
	163	unsigned long msr_b;
	164	unsigned long config;
	165	};
	166
	167	/**
	168	* struct pt_filters - IP range filtering context
	169	* @filter: filters defined for this context
	170	* @nr_filters: number of defined filters in the @filter array
	171	*/
	172	struct pt_filters {
	173	struct pt_filter filter[PT_FILTERS_NUM];
	174	unsigned int nr_filters;
	175	};
	176
52ca9ced AS	177	/**
	178	* struct pt - per-cpu pt context
	179	* @handle: perf output handle
eadf48ca	180	* @filters: last configured filters
52ca9ced	181	* @handle_nmi: do handle PT PMI on this cpu, there's an active event
1c5ac21a	182	* @vmx_on: 1 if VMX is ON on this cpu
52ca9ced AS	183	*/
	184	struct pt {
	185	struct perf_output_handle handle;
eadf48ca	186	struct pt_filters filters;
52ca9ced	187	int handle_nmi;
1c5ac21a	188	int vmx_on;
52ca9ced AS	189	};
	190
	191	#endif /* __INTEL_PT_H__ */