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4788e5b4 SE |
1 | /* |
2 | * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters | |
3 | * Copyright (C) 2013 Google, Inc., Stephane Eranian | |
4 | * | |
5 | * Intel RAPL interface is specified in the IA-32 Manual Vol3b | |
6 | * section 14.7.1 (September 2013) | |
7 | * | |
8 | * RAPL provides more controls than just reporting energy consumption | |
9 | * however here we only expose the 3 energy consumption free running | |
10 | * counters (pp0, pkg, dram). | |
11 | * | |
12 | * Each of those counters increments in a power unit defined by the | |
13 | * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules | |
14 | * but it can vary. | |
15 | * | |
16 | * Counter to rapl events mappings: | |
17 | * | |
18 | * pp0 counter: consumption of all physical cores (power plane 0) | |
19 | * event: rapl_energy_cores | |
20 | * perf code: 0x1 | |
21 | * | |
22 | * pkg counter: consumption of the whole processor package | |
23 | * event: rapl_energy_pkg | |
24 | * perf code: 0x2 | |
25 | * | |
26 | * dram counter: consumption of the dram domain (servers only) | |
27 | * event: rapl_energy_dram | |
28 | * perf code: 0x3 | |
29 | * | |
f228c5b8 SE |
30 | * dram counter: consumption of the builtin-gpu domain (client only) |
31 | * event: rapl_energy_gpu | |
32 | * perf code: 0x4 | |
33 | * | |
4788e5b4 SE |
34 | * We manage those counters as free running (read-only). They may be |
35 | * use simultaneously by other tools, such as turbostat. | |
36 | * | |
37 | * The events only support system-wide mode counting. There is no | |
38 | * sampling support because it does not make sense and is not | |
39 | * supported by the RAPL hardware. | |
40 | * | |
41 | * Because we want to avoid floating-point operations in the kernel, | |
42 | * the events are all reported in fixed point arithmetic (32.32). | |
43 | * Tools must adjust the counts to convert them to Watts using | |
44 | * the duration of the measurement. Tools may use a function such as | |
45 | * ldexp(raw_count, -32); | |
46 | */ | |
47 | #include <linux/module.h> | |
48 | #include <linux/slab.h> | |
49 | #include <linux/perf_event.h> | |
50 | #include <asm/cpu_device_id.h> | |
27f6d22b | 51 | #include "../perf_event.h" |
4788e5b4 SE |
52 | |
53 | /* | |
54 | * RAPL energy status counters | |
55 | */ | |
56 | #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */ | |
57 | #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */ | |
58 | #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */ | |
59 | #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */ | |
60 | #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */ | |
61 | #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */ | |
e69af465 | 62 | #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */ |
f228c5b8 | 63 | #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */ |
4788e5b4 | 64 | |
64552396 | 65 | #define NR_RAPL_DOMAINS 0x4 |
da008ee7 | 66 | static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = { |
64552396 JP |
67 | "pp0-core", |
68 | "package", | |
69 | "dram", | |
70 | "pp1-gpu", | |
71 | }; | |
72 | ||
4788e5b4 SE |
73 | /* Clients have PP0, PKG */ |
74 | #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
f228c5b8 SE |
75 | 1<<RAPL_IDX_PKG_NRG_STAT|\ |
76 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
4788e5b4 SE |
77 | |
78 | /* Servers have PP0, PKG, RAM */ | |
79 | #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
80 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
81 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
82 | ||
e69af465 VW |
83 | /* Servers have PP0, PKG, RAM, PP1 */ |
84 | #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
85 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
86 | 1<<RAPL_IDX_RAM_NRG_STAT|\ | |
87 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
88 | ||
3a2a7797 DC |
89 | /* Knights Landing has PKG, RAM */ |
90 | #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\ | |
91 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
92 | ||
4788e5b4 SE |
93 | /* |
94 | * event code: LSB 8 bits, passed in attr->config | |
95 | * any other bit is reserved | |
96 | */ | |
97 | #define RAPL_EVENT_MASK 0xFFULL | |
98 | ||
99 | #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \ | |
100 | static ssize_t __rapl_##_var##_show(struct kobject *kobj, \ | |
101 | struct kobj_attribute *attr, \ | |
102 | char *page) \ | |
103 | { \ | |
104 | BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ | |
105 | return sprintf(page, _format "\n"); \ | |
106 | } \ | |
107 | static struct kobj_attribute format_attr_##_var = \ | |
108 | __ATTR(_name, 0444, __rapl_##_var##_show, NULL) | |
109 | ||
4788e5b4 SE |
110 | #define RAPL_CNTR_WIDTH 32 /* 32-bit rapl counters */ |
111 | ||
d3bcd64b HR |
112 | #define RAPL_EVENT_ATTR_STR(_name, v, str) \ |
113 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
114 | .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ | |
115 | .id = 0, \ | |
116 | .event_str = str, \ | |
433678bd SE |
117 | }; |
118 | ||
4788e5b4 SE |
119 | struct rapl_pmu { |
120 | spinlock_t lock; | |
4788e5b4 SE |
121 | int n_active; /* number of active events */ |
122 | struct list_head active_list; | |
123 | struct pmu *pmu; /* pointer to rapl_pmu_class */ | |
65661f96 SE |
124 | ktime_t timer_interval; /* in ktime_t unit */ |
125 | struct hrtimer hrtimer; | |
4788e5b4 SE |
126 | }; |
127 | ||
64552396 | 128 | static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; /* 1/2^hw_unit Joule */ |
4788e5b4 SE |
129 | static struct pmu rapl_pmu_class; |
130 | static cpumask_t rapl_cpu_mask; | |
131 | static int rapl_cntr_mask; | |
132 | ||
133 | static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu); | |
134 | static DEFINE_PER_CPU(struct rapl_pmu *, rapl_pmu_to_free); | |
135 | ||
64552396 | 136 | static struct x86_pmu_quirk *rapl_quirks; |
4788e5b4 SE |
137 | static inline u64 rapl_read_counter(struct perf_event *event) |
138 | { | |
139 | u64 raw; | |
140 | rdmsrl(event->hw.event_base, raw); | |
141 | return raw; | |
142 | } | |
143 | ||
64552396 JP |
144 | #define rapl_add_quirk(func_) \ |
145 | do { \ | |
146 | static struct x86_pmu_quirk __quirk __initdata = { \ | |
147 | .func = func_, \ | |
148 | }; \ | |
149 | __quirk.next = rapl_quirks; \ | |
150 | rapl_quirks = &__quirk; \ | |
151 | } while (0) | |
152 | ||
153 | static inline u64 rapl_scale(u64 v, int cfg) | |
4788e5b4 | 154 | { |
64552396 JP |
155 | if (cfg > NR_RAPL_DOMAINS) { |
156 | pr_warn("invalid domain %d, failed to scale data\n", cfg); | |
157 | return v; | |
158 | } | |
4788e5b4 SE |
159 | /* |
160 | * scale delta to smallest unit (1/2^32) | |
161 | * users must then scale back: count * 1/(1e9*2^32) to get Joules | |
162 | * or use ldexp(count, -32). | |
163 | * Watts = Joules/Time delta | |
164 | */ | |
64552396 | 165 | return v << (32 - rapl_hw_unit[cfg - 1]); |
4788e5b4 SE |
166 | } |
167 | ||
168 | static u64 rapl_event_update(struct perf_event *event) | |
169 | { | |
170 | struct hw_perf_event *hwc = &event->hw; | |
171 | u64 prev_raw_count, new_raw_count; | |
172 | s64 delta, sdelta; | |
173 | int shift = RAPL_CNTR_WIDTH; | |
174 | ||
175 | again: | |
176 | prev_raw_count = local64_read(&hwc->prev_count); | |
177 | rdmsrl(event->hw.event_base, new_raw_count); | |
178 | ||
179 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
180 | new_raw_count) != prev_raw_count) { | |
181 | cpu_relax(); | |
182 | goto again; | |
183 | } | |
184 | ||
185 | /* | |
186 | * Now we have the new raw value and have updated the prev | |
187 | * timestamp already. We can now calculate the elapsed delta | |
188 | * (event-)time and add that to the generic event. | |
189 | * | |
190 | * Careful, not all hw sign-extends above the physical width | |
191 | * of the count. | |
192 | */ | |
193 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
194 | delta >>= shift; | |
195 | ||
64552396 | 196 | sdelta = rapl_scale(delta, event->hw.config); |
4788e5b4 SE |
197 | |
198 | local64_add(sdelta, &event->count); | |
199 | ||
200 | return new_raw_count; | |
201 | } | |
202 | ||
65661f96 SE |
203 | static void rapl_start_hrtimer(struct rapl_pmu *pmu) |
204 | { | |
514c2304 TG |
205 | hrtimer_start(&pmu->hrtimer, pmu->timer_interval, |
206 | HRTIMER_MODE_REL_PINNED); | |
65661f96 SE |
207 | } |
208 | ||
209 | static void rapl_stop_hrtimer(struct rapl_pmu *pmu) | |
210 | { | |
211 | hrtimer_cancel(&pmu->hrtimer); | |
212 | } | |
213 | ||
214 | static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) | |
215 | { | |
89cbc767 | 216 | struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu); |
65661f96 SE |
217 | struct perf_event *event; |
218 | unsigned long flags; | |
219 | ||
220 | if (!pmu->n_active) | |
221 | return HRTIMER_NORESTART; | |
222 | ||
223 | spin_lock_irqsave(&pmu->lock, flags); | |
224 | ||
225 | list_for_each_entry(event, &pmu->active_list, active_entry) { | |
226 | rapl_event_update(event); | |
227 | } | |
228 | ||
229 | spin_unlock_irqrestore(&pmu->lock, flags); | |
230 | ||
231 | hrtimer_forward_now(hrtimer, pmu->timer_interval); | |
232 | ||
233 | return HRTIMER_RESTART; | |
234 | } | |
235 | ||
236 | static void rapl_hrtimer_init(struct rapl_pmu *pmu) | |
237 | { | |
238 | struct hrtimer *hr = &pmu->hrtimer; | |
239 | ||
240 | hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
241 | hr->function = rapl_hrtimer_handle; | |
242 | } | |
243 | ||
4788e5b4 SE |
244 | static void __rapl_pmu_event_start(struct rapl_pmu *pmu, |
245 | struct perf_event *event) | |
246 | { | |
247 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) | |
248 | return; | |
249 | ||
250 | event->hw.state = 0; | |
251 | ||
252 | list_add_tail(&event->active_entry, &pmu->active_list); | |
253 | ||
254 | local64_set(&event->hw.prev_count, rapl_read_counter(event)); | |
255 | ||
256 | pmu->n_active++; | |
65661f96 SE |
257 | if (pmu->n_active == 1) |
258 | rapl_start_hrtimer(pmu); | |
4788e5b4 SE |
259 | } |
260 | ||
261 | static void rapl_pmu_event_start(struct perf_event *event, int mode) | |
262 | { | |
89cbc767 | 263 | struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu); |
4788e5b4 SE |
264 | unsigned long flags; |
265 | ||
266 | spin_lock_irqsave(&pmu->lock, flags); | |
267 | __rapl_pmu_event_start(pmu, event); | |
268 | spin_unlock_irqrestore(&pmu->lock, flags); | |
269 | } | |
270 | ||
271 | static void rapl_pmu_event_stop(struct perf_event *event, int mode) | |
272 | { | |
89cbc767 | 273 | struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu); |
4788e5b4 SE |
274 | struct hw_perf_event *hwc = &event->hw; |
275 | unsigned long flags; | |
276 | ||
277 | spin_lock_irqsave(&pmu->lock, flags); | |
278 | ||
279 | /* mark event as deactivated and stopped */ | |
280 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
281 | WARN_ON_ONCE(pmu->n_active <= 0); | |
282 | pmu->n_active--; | |
65661f96 SE |
283 | if (pmu->n_active == 0) |
284 | rapl_stop_hrtimer(pmu); | |
4788e5b4 SE |
285 | |
286 | list_del(&event->active_entry); | |
287 | ||
288 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
289 | hwc->state |= PERF_HES_STOPPED; | |
290 | } | |
291 | ||
292 | /* check if update of sw counter is necessary */ | |
293 | if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | |
294 | /* | |
295 | * Drain the remaining delta count out of a event | |
296 | * that we are disabling: | |
297 | */ | |
298 | rapl_event_update(event); | |
299 | hwc->state |= PERF_HES_UPTODATE; | |
300 | } | |
301 | ||
302 | spin_unlock_irqrestore(&pmu->lock, flags); | |
303 | } | |
304 | ||
305 | static int rapl_pmu_event_add(struct perf_event *event, int mode) | |
306 | { | |
89cbc767 | 307 | struct rapl_pmu *pmu = __this_cpu_read(rapl_pmu); |
4788e5b4 SE |
308 | struct hw_perf_event *hwc = &event->hw; |
309 | unsigned long flags; | |
310 | ||
311 | spin_lock_irqsave(&pmu->lock, flags); | |
312 | ||
313 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
314 | ||
315 | if (mode & PERF_EF_START) | |
316 | __rapl_pmu_event_start(pmu, event); | |
317 | ||
318 | spin_unlock_irqrestore(&pmu->lock, flags); | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | static void rapl_pmu_event_del(struct perf_event *event, int flags) | |
324 | { | |
325 | rapl_pmu_event_stop(event, PERF_EF_UPDATE); | |
326 | } | |
327 | ||
328 | static int rapl_pmu_event_init(struct perf_event *event) | |
329 | { | |
330 | u64 cfg = event->attr.config & RAPL_EVENT_MASK; | |
331 | int bit, msr, ret = 0; | |
332 | ||
333 | /* only look at RAPL events */ | |
334 | if (event->attr.type != rapl_pmu_class.type) | |
335 | return -ENOENT; | |
336 | ||
337 | /* check only supported bits are set */ | |
338 | if (event->attr.config & ~RAPL_EVENT_MASK) | |
339 | return -EINVAL; | |
340 | ||
341 | /* | |
342 | * check event is known (determines counter) | |
343 | */ | |
344 | switch (cfg) { | |
345 | case INTEL_RAPL_PP0: | |
346 | bit = RAPL_IDX_PP0_NRG_STAT; | |
347 | msr = MSR_PP0_ENERGY_STATUS; | |
348 | break; | |
349 | case INTEL_RAPL_PKG: | |
350 | bit = RAPL_IDX_PKG_NRG_STAT; | |
351 | msr = MSR_PKG_ENERGY_STATUS; | |
352 | break; | |
353 | case INTEL_RAPL_RAM: | |
354 | bit = RAPL_IDX_RAM_NRG_STAT; | |
355 | msr = MSR_DRAM_ENERGY_STATUS; | |
356 | break; | |
f228c5b8 SE |
357 | case INTEL_RAPL_PP1: |
358 | bit = RAPL_IDX_PP1_NRG_STAT; | |
359 | msr = MSR_PP1_ENERGY_STATUS; | |
360 | break; | |
4788e5b4 SE |
361 | default: |
362 | return -EINVAL; | |
363 | } | |
364 | /* check event supported */ | |
365 | if (!(rapl_cntr_mask & (1 << bit))) | |
366 | return -EINVAL; | |
367 | ||
368 | /* unsupported modes and filters */ | |
369 | if (event->attr.exclude_user || | |
370 | event->attr.exclude_kernel || | |
371 | event->attr.exclude_hv || | |
372 | event->attr.exclude_idle || | |
373 | event->attr.exclude_host || | |
374 | event->attr.exclude_guest || | |
375 | event->attr.sample_period) /* no sampling */ | |
376 | return -EINVAL; | |
377 | ||
378 | /* must be done before validate_group */ | |
379 | event->hw.event_base = msr; | |
380 | event->hw.config = cfg; | |
381 | event->hw.idx = bit; | |
382 | ||
383 | return ret; | |
384 | } | |
385 | ||
386 | static void rapl_pmu_event_read(struct perf_event *event) | |
387 | { | |
388 | rapl_event_update(event); | |
389 | } | |
390 | ||
391 | static ssize_t rapl_get_attr_cpumask(struct device *dev, | |
392 | struct device_attribute *attr, char *buf) | |
393 | { | |
5aaba363 | 394 | return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask); |
4788e5b4 SE |
395 | } |
396 | ||
397 | static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL); | |
398 | ||
399 | static struct attribute *rapl_pmu_attrs[] = { | |
400 | &dev_attr_cpumask.attr, | |
401 | NULL, | |
402 | }; | |
403 | ||
404 | static struct attribute_group rapl_pmu_attr_group = { | |
405 | .attrs = rapl_pmu_attrs, | |
406 | }; | |
407 | ||
433678bd SE |
408 | RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); |
409 | RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); | |
410 | RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); | |
411 | RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04"); | |
4788e5b4 | 412 | |
433678bd SE |
413 | RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); |
414 | RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); | |
415 | RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); | |
416 | RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); | |
4788e5b4 SE |
417 | |
418 | /* | |
419 | * we compute in 0.23 nJ increments regardless of MSR | |
420 | */ | |
433678bd SE |
421 | RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); |
422 | RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); | |
423 | RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); | |
424 | RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); | |
4788e5b4 SE |
425 | |
426 | static struct attribute *rapl_events_srv_attr[] = { | |
427 | EVENT_PTR(rapl_cores), | |
428 | EVENT_PTR(rapl_pkg), | |
429 | EVENT_PTR(rapl_ram), | |
430 | ||
431 | EVENT_PTR(rapl_cores_unit), | |
432 | EVENT_PTR(rapl_pkg_unit), | |
433 | EVENT_PTR(rapl_ram_unit), | |
434 | ||
435 | EVENT_PTR(rapl_cores_scale), | |
436 | EVENT_PTR(rapl_pkg_scale), | |
437 | EVENT_PTR(rapl_ram_scale), | |
438 | NULL, | |
439 | }; | |
440 | ||
441 | static struct attribute *rapl_events_cln_attr[] = { | |
442 | EVENT_PTR(rapl_cores), | |
443 | EVENT_PTR(rapl_pkg), | |
f228c5b8 | 444 | EVENT_PTR(rapl_gpu), |
4788e5b4 SE |
445 | |
446 | EVENT_PTR(rapl_cores_unit), | |
447 | EVENT_PTR(rapl_pkg_unit), | |
f228c5b8 | 448 | EVENT_PTR(rapl_gpu_unit), |
4788e5b4 SE |
449 | |
450 | EVENT_PTR(rapl_cores_scale), | |
451 | EVENT_PTR(rapl_pkg_scale), | |
f228c5b8 | 452 | EVENT_PTR(rapl_gpu_scale), |
4788e5b4 SE |
453 | NULL, |
454 | }; | |
455 | ||
e69af465 VW |
456 | static struct attribute *rapl_events_hsw_attr[] = { |
457 | EVENT_PTR(rapl_cores), | |
458 | EVENT_PTR(rapl_pkg), | |
459 | EVENT_PTR(rapl_gpu), | |
460 | EVENT_PTR(rapl_ram), | |
461 | ||
462 | EVENT_PTR(rapl_cores_unit), | |
463 | EVENT_PTR(rapl_pkg_unit), | |
464 | EVENT_PTR(rapl_gpu_unit), | |
465 | EVENT_PTR(rapl_ram_unit), | |
466 | ||
467 | EVENT_PTR(rapl_cores_scale), | |
468 | EVENT_PTR(rapl_pkg_scale), | |
469 | EVENT_PTR(rapl_gpu_scale), | |
470 | EVENT_PTR(rapl_ram_scale), | |
471 | NULL, | |
472 | }; | |
473 | ||
3a2a7797 DC |
474 | static struct attribute *rapl_events_knl_attr[] = { |
475 | EVENT_PTR(rapl_pkg), | |
476 | EVENT_PTR(rapl_ram), | |
477 | ||
478 | EVENT_PTR(rapl_pkg_unit), | |
479 | EVENT_PTR(rapl_ram_unit), | |
480 | ||
481 | EVENT_PTR(rapl_pkg_scale), | |
482 | EVENT_PTR(rapl_ram_scale), | |
483 | NULL, | |
484 | }; | |
485 | ||
4788e5b4 SE |
486 | static struct attribute_group rapl_pmu_events_group = { |
487 | .name = "events", | |
488 | .attrs = NULL, /* patched at runtime */ | |
489 | }; | |
490 | ||
491 | DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7"); | |
492 | static struct attribute *rapl_formats_attr[] = { | |
493 | &format_attr_event.attr, | |
494 | NULL, | |
495 | }; | |
496 | ||
497 | static struct attribute_group rapl_pmu_format_group = { | |
498 | .name = "format", | |
499 | .attrs = rapl_formats_attr, | |
500 | }; | |
501 | ||
502 | const struct attribute_group *rapl_attr_groups[] = { | |
503 | &rapl_pmu_attr_group, | |
504 | &rapl_pmu_format_group, | |
505 | &rapl_pmu_events_group, | |
506 | NULL, | |
507 | }; | |
508 | ||
509 | static struct pmu rapl_pmu_class = { | |
510 | .attr_groups = rapl_attr_groups, | |
511 | .task_ctx_nr = perf_invalid_context, /* system-wide only */ | |
512 | .event_init = rapl_pmu_event_init, | |
513 | .add = rapl_pmu_event_add, /* must have */ | |
514 | .del = rapl_pmu_event_del, /* must have */ | |
515 | .start = rapl_pmu_event_start, | |
516 | .stop = rapl_pmu_event_stop, | |
517 | .read = rapl_pmu_event_read, | |
518 | }; | |
519 | ||
520 | static void rapl_cpu_exit(int cpu) | |
521 | { | |
522 | struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu); | |
523 | int i, phys_id = topology_physical_package_id(cpu); | |
524 | int target = -1; | |
525 | ||
526 | /* find a new cpu on same package */ | |
527 | for_each_online_cpu(i) { | |
528 | if (i == cpu) | |
529 | continue; | |
530 | if (phys_id == topology_physical_package_id(i)) { | |
531 | target = i; | |
532 | break; | |
533 | } | |
534 | } | |
535 | /* | |
536 | * clear cpu from cpumask | |
537 | * if was set in cpumask and still some cpu on package, | |
538 | * then move to new cpu | |
539 | */ | |
540 | if (cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask) && target >= 0) | |
541 | cpumask_set_cpu(target, &rapl_cpu_mask); | |
542 | ||
543 | WARN_ON(cpumask_empty(&rapl_cpu_mask)); | |
544 | /* | |
545 | * migrate events and context to new cpu | |
546 | */ | |
547 | if (target >= 0) | |
548 | perf_pmu_migrate_context(pmu->pmu, cpu, target); | |
65661f96 SE |
549 | |
550 | /* cancel overflow polling timer for CPU */ | |
551 | rapl_stop_hrtimer(pmu); | |
4788e5b4 SE |
552 | } |
553 | ||
554 | static void rapl_cpu_init(int cpu) | |
555 | { | |
556 | int i, phys_id = topology_physical_package_id(cpu); | |
557 | ||
558 | /* check if phys_is is already covered */ | |
559 | for_each_cpu(i, &rapl_cpu_mask) { | |
560 | if (phys_id == topology_physical_package_id(i)) | |
561 | return; | |
562 | } | |
563 | /* was not found, so add it */ | |
564 | cpumask_set_cpu(cpu, &rapl_cpu_mask); | |
565 | } | |
566 | ||
64552396 JP |
567 | static __init void rapl_hsw_server_quirk(void) |
568 | { | |
569 | /* | |
570 | * DRAM domain on HSW server has fixed energy unit which can be | |
571 | * different than the unit from power unit MSR. | |
572 | * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2 | |
573 | * of 2. Datasheet, September 2014, Reference Number: 330784-001 " | |
574 | */ | |
575 | rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16; | |
576 | } | |
577 | ||
4788e5b4 SE |
578 | static int rapl_cpu_prepare(int cpu) |
579 | { | |
580 | struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu); | |
581 | int phys_id = topology_physical_package_id(cpu); | |
65661f96 | 582 | u64 ms; |
4788e5b4 SE |
583 | |
584 | if (pmu) | |
585 | return 0; | |
586 | ||
587 | if (phys_id < 0) | |
588 | return -1; | |
589 | ||
590 | pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu)); | |
591 | if (!pmu) | |
592 | return -1; | |
4788e5b4 SE |
593 | spin_lock_init(&pmu->lock); |
594 | ||
595 | INIT_LIST_HEAD(&pmu->active_list); | |
596 | ||
4788e5b4 SE |
597 | pmu->pmu = &rapl_pmu_class; |
598 | ||
65661f96 SE |
599 | /* |
600 | * use reference of 200W for scaling the timeout | |
601 | * to avoid missing counter overflows. | |
602 | * 200W = 200 Joules/sec | |
603 | * divide interval by 2 to avoid lockstep (2 * 100) | |
604 | * if hw unit is 32, then we use 2 ms 1/200/2 | |
605 | */ | |
64552396 JP |
606 | if (rapl_hw_unit[0] < 32) |
607 | ms = (1000 / (2 * 100)) * (1ULL << (32 - rapl_hw_unit[0] - 1)); | |
65661f96 SE |
608 | else |
609 | ms = 2; | |
610 | ||
611 | pmu->timer_interval = ms_to_ktime(ms); | |
612 | ||
613 | rapl_hrtimer_init(pmu); | |
614 | ||
4788e5b4 SE |
615 | /* set RAPL pmu for this cpu for now */ |
616 | per_cpu(rapl_pmu, cpu) = pmu; | |
617 | per_cpu(rapl_pmu_to_free, cpu) = NULL; | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
622 | static void rapl_cpu_kfree(int cpu) | |
623 | { | |
624 | struct rapl_pmu *pmu = per_cpu(rapl_pmu_to_free, cpu); | |
625 | ||
626 | kfree(pmu); | |
627 | ||
628 | per_cpu(rapl_pmu_to_free, cpu) = NULL; | |
629 | } | |
630 | ||
631 | static int rapl_cpu_dying(int cpu) | |
632 | { | |
633 | struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu); | |
634 | ||
635 | if (!pmu) | |
636 | return 0; | |
637 | ||
638 | per_cpu(rapl_pmu, cpu) = NULL; | |
639 | ||
640 | per_cpu(rapl_pmu_to_free, cpu) = pmu; | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
645 | static int rapl_cpu_notifier(struct notifier_block *self, | |
646 | unsigned long action, void *hcpu) | |
647 | { | |
648 | unsigned int cpu = (long)hcpu; | |
649 | ||
650 | switch (action & ~CPU_TASKS_FROZEN) { | |
651 | case CPU_UP_PREPARE: | |
652 | rapl_cpu_prepare(cpu); | |
653 | break; | |
654 | case CPU_STARTING: | |
655 | rapl_cpu_init(cpu); | |
656 | break; | |
657 | case CPU_UP_CANCELED: | |
658 | case CPU_DYING: | |
659 | rapl_cpu_dying(cpu); | |
660 | break; | |
661 | case CPU_ONLINE: | |
662 | case CPU_DEAD: | |
663 | rapl_cpu_kfree(cpu); | |
664 | break; | |
665 | case CPU_DOWN_PREPARE: | |
666 | rapl_cpu_exit(cpu); | |
667 | break; | |
668 | default: | |
669 | break; | |
670 | } | |
671 | ||
672 | return NOTIFY_OK; | |
673 | } | |
674 | ||
64552396 JP |
675 | static int rapl_check_hw_unit(void) |
676 | { | |
677 | u64 msr_rapl_power_unit_bits; | |
678 | int i; | |
679 | ||
680 | /* protect rdmsrl() to handle virtualization */ | |
681 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits)) | |
682 | return -1; | |
683 | for (i = 0; i < NR_RAPL_DOMAINS; i++) | |
684 | rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL; | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
4788e5b4 SE |
689 | static const struct x86_cpu_id rapl_cpu_match[] = { |
690 | [0] = { .vendor = X86_VENDOR_INTEL, .family = 6 }, | |
691 | [1] = {}, | |
692 | }; | |
693 | ||
694 | static int __init rapl_pmu_init(void) | |
695 | { | |
696 | struct rapl_pmu *pmu; | |
697 | int cpu, ret; | |
64552396 JP |
698 | struct x86_pmu_quirk *quirk; |
699 | int i; | |
4788e5b4 SE |
700 | |
701 | /* | |
702 | * check for Intel processor family 6 | |
703 | */ | |
704 | if (!x86_match_cpu(rapl_cpu_match)) | |
705 | return 0; | |
706 | ||
707 | /* check supported CPU */ | |
708 | switch (boot_cpu_data.x86_model) { | |
709 | case 42: /* Sandy Bridge */ | |
710 | case 58: /* Ivy Bridge */ | |
4788e5b4 SE |
711 | rapl_cntr_mask = RAPL_IDX_CLN; |
712 | rapl_pmu_events_group.attrs = rapl_events_cln_attr; | |
713 | break; | |
64552396 JP |
714 | case 63: /* Haswell-Server */ |
715 | rapl_add_quirk(rapl_hsw_server_quirk); | |
716 | rapl_cntr_mask = RAPL_IDX_SRV; | |
717 | rapl_pmu_events_group.attrs = rapl_events_srv_attr; | |
718 | break; | |
e69af465 VW |
719 | case 60: /* Haswell */ |
720 | case 69: /* Haswell-Celeron */ | |
44b11fee | 721 | case 61: /* Broadwell */ |
e69af465 VW |
722 | rapl_cntr_mask = RAPL_IDX_HSW; |
723 | rapl_pmu_events_group.attrs = rapl_events_hsw_attr; | |
724 | break; | |
4788e5b4 SE |
725 | case 45: /* Sandy Bridge-EP */ |
726 | case 62: /* IvyTown */ | |
727 | rapl_cntr_mask = RAPL_IDX_SRV; | |
728 | rapl_pmu_events_group.attrs = rapl_events_srv_attr; | |
729 | break; | |
3a2a7797 DC |
730 | case 87: /* Knights Landing */ |
731 | rapl_add_quirk(rapl_hsw_server_quirk); | |
732 | rapl_cntr_mask = RAPL_IDX_KNL; | |
733 | rapl_pmu_events_group.attrs = rapl_events_knl_attr; | |
4d120c53 | 734 | break; |
4788e5b4 SE |
735 | default: |
736 | /* unsupported */ | |
737 | return 0; | |
738 | } | |
64552396 JP |
739 | ret = rapl_check_hw_unit(); |
740 | if (ret) | |
741 | return ret; | |
fd537e56 | 742 | |
64552396 JP |
743 | /* run cpu model quirks */ |
744 | for (quirk = rapl_quirks; quirk; quirk = quirk->next) | |
745 | quirk->func(); | |
fd537e56 | 746 | cpu_notifier_register_begin(); |
4788e5b4 SE |
747 | |
748 | for_each_online_cpu(cpu) { | |
24223657 VS |
749 | ret = rapl_cpu_prepare(cpu); |
750 | if (ret) | |
751 | goto out; | |
4788e5b4 SE |
752 | rapl_cpu_init(cpu); |
753 | } | |
754 | ||
fd537e56 | 755 | __perf_cpu_notifier(rapl_cpu_notifier); |
4788e5b4 SE |
756 | |
757 | ret = perf_pmu_register(&rapl_pmu_class, "power", -1); | |
758 | if (WARN_ON(ret)) { | |
759 | pr_info("RAPL PMU detected, registration failed (%d), RAPL PMU disabled\n", ret); | |
fd537e56 | 760 | cpu_notifier_register_done(); |
4788e5b4 SE |
761 | return -1; |
762 | } | |
763 | ||
89cbc767 | 764 | pmu = __this_cpu_read(rapl_pmu); |
4788e5b4 | 765 | |
64552396 | 766 | pr_info("RAPL PMU detected," |
4788e5b4 | 767 | " API unit is 2^-32 Joules," |
65661f96 SE |
768 | " %d fixed counters" |
769 | " %llu ms ovfl timer\n", | |
65661f96 SE |
770 | hweight32(rapl_cntr_mask), |
771 | ktime_to_ms(pmu->timer_interval)); | |
64552396 JP |
772 | for (i = 0; i < NR_RAPL_DOMAINS; i++) { |
773 | if (rapl_cntr_mask & (1 << i)) { | |
774 | pr_info("hw unit of domain %s 2^-%d Joules\n", | |
775 | rapl_domain_names[i], rapl_hw_unit[i]); | |
776 | } | |
777 | } | |
24223657 | 778 | out: |
fd537e56 | 779 | cpu_notifier_register_done(); |
4788e5b4 SE |
780 | |
781 | return 0; | |
782 | } | |
783 | device_initcall(rapl_pmu_init); |