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4788e5b4 SE |
1 | /* |
2 | * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters | |
3 | * Copyright (C) 2013 Google, Inc., Stephane Eranian | |
4 | * | |
5 | * Intel RAPL interface is specified in the IA-32 Manual Vol3b | |
6 | * section 14.7.1 (September 2013) | |
7 | * | |
8 | * RAPL provides more controls than just reporting energy consumption | |
9 | * however here we only expose the 3 energy consumption free running | |
10 | * counters (pp0, pkg, dram). | |
11 | * | |
12 | * Each of those counters increments in a power unit defined by the | |
13 | * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules | |
14 | * but it can vary. | |
15 | * | |
16 | * Counter to rapl events mappings: | |
17 | * | |
18 | * pp0 counter: consumption of all physical cores (power plane 0) | |
19 | * event: rapl_energy_cores | |
20 | * perf code: 0x1 | |
21 | * | |
22 | * pkg counter: consumption of the whole processor package | |
23 | * event: rapl_energy_pkg | |
24 | * perf code: 0x2 | |
25 | * | |
26 | * dram counter: consumption of the dram domain (servers only) | |
27 | * event: rapl_energy_dram | |
28 | * perf code: 0x3 | |
29 | * | |
f228c5b8 SE |
30 | * dram counter: consumption of the builtin-gpu domain (client only) |
31 | * event: rapl_energy_gpu | |
32 | * perf code: 0x4 | |
33 | * | |
4788e5b4 SE |
34 | * We manage those counters as free running (read-only). They may be |
35 | * use simultaneously by other tools, such as turbostat. | |
36 | * | |
37 | * The events only support system-wide mode counting. There is no | |
38 | * sampling support because it does not make sense and is not | |
39 | * supported by the RAPL hardware. | |
40 | * | |
41 | * Because we want to avoid floating-point operations in the kernel, | |
42 | * the events are all reported in fixed point arithmetic (32.32). | |
43 | * Tools must adjust the counts to convert them to Watts using | |
44 | * the duration of the measurement. Tools may use a function such as | |
45 | * ldexp(raw_count, -32); | |
46 | */ | |
512089d9 TG |
47 | |
48 | #define pr_fmt(fmt) "RAPL PMU: " fmt | |
49 | ||
4788e5b4 SE |
50 | #include <linux/module.h> |
51 | #include <linux/slab.h> | |
52 | #include <linux/perf_event.h> | |
53 | #include <asm/cpu_device_id.h> | |
27f6d22b | 54 | #include "../perf_event.h" |
4788e5b4 | 55 | |
4b6e2571 KL |
56 | MODULE_LICENSE("GPL"); |
57 | ||
4788e5b4 SE |
58 | /* |
59 | * RAPL energy status counters | |
60 | */ | |
61 | #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */ | |
62 | #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */ | |
63 | #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */ | |
64 | #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */ | |
65 | #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */ | |
66 | #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */ | |
e69af465 | 67 | #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */ |
f228c5b8 | 68 | #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */ |
4788e5b4 | 69 | |
64552396 | 70 | #define NR_RAPL_DOMAINS 0x4 |
da008ee7 | 71 | static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = { |
64552396 JP |
72 | "pp0-core", |
73 | "package", | |
74 | "dram", | |
75 | "pp1-gpu", | |
76 | }; | |
77 | ||
4788e5b4 SE |
78 | /* Clients have PP0, PKG */ |
79 | #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
f228c5b8 SE |
80 | 1<<RAPL_IDX_PKG_NRG_STAT|\ |
81 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
4788e5b4 SE |
82 | |
83 | /* Servers have PP0, PKG, RAM */ | |
84 | #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
85 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
86 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
87 | ||
e69af465 VW |
88 | /* Servers have PP0, PKG, RAM, PP1 */ |
89 | #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
90 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
91 | 1<<RAPL_IDX_RAM_NRG_STAT|\ | |
92 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
93 | ||
3a2a7797 DC |
94 | /* Knights Landing has PKG, RAM */ |
95 | #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\ | |
96 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
97 | ||
4788e5b4 SE |
98 | /* |
99 | * event code: LSB 8 bits, passed in attr->config | |
100 | * any other bit is reserved | |
101 | */ | |
102 | #define RAPL_EVENT_MASK 0xFFULL | |
103 | ||
104 | #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \ | |
105 | static ssize_t __rapl_##_var##_show(struct kobject *kobj, \ | |
106 | struct kobj_attribute *attr, \ | |
107 | char *page) \ | |
108 | { \ | |
109 | BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ | |
110 | return sprintf(page, _format "\n"); \ | |
111 | } \ | |
112 | static struct kobj_attribute format_attr_##_var = \ | |
113 | __ATTR(_name, 0444, __rapl_##_var##_show, NULL) | |
114 | ||
7162b8fe | 115 | #define RAPL_CNTR_WIDTH 32 |
4788e5b4 | 116 | |
d3bcd64b HR |
117 | #define RAPL_EVENT_ATTR_STR(_name, v, str) \ |
118 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
119 | .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ | |
120 | .id = 0, \ | |
121 | .event_str = str, \ | |
433678bd SE |
122 | }; |
123 | ||
4788e5b4 | 124 | struct rapl_pmu { |
a208749c | 125 | raw_spinlock_t lock; |
7162b8fe | 126 | int n_active; |
8a6d2f8f | 127 | int cpu; |
7162b8fe TG |
128 | struct list_head active_list; |
129 | struct pmu *pmu; | |
130 | ktime_t timer_interval; | |
131 | struct hrtimer hrtimer; | |
4788e5b4 SE |
132 | }; |
133 | ||
9de8d686 TG |
134 | struct rapl_pmus { |
135 | struct pmu pmu; | |
136 | unsigned int maxpkg; | |
137 | struct rapl_pmu *pmus[]; | |
138 | }; | |
139 | ||
7162b8fe TG |
140 | /* 1/2^hw_unit Joule */ |
141 | static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; | |
9de8d686 | 142 | static struct rapl_pmus *rapl_pmus; |
4788e5b4 | 143 | static cpumask_t rapl_cpu_mask; |
9de8d686 | 144 | static unsigned int rapl_cntr_mask; |
75c7003f | 145 | static u64 rapl_timer_ms; |
4788e5b4 | 146 | |
9de8d686 TG |
147 | static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) |
148 | { | |
149 | return rapl_pmus->pmus[topology_logical_package_id(cpu)]; | |
150 | } | |
4788e5b4 SE |
151 | |
152 | static inline u64 rapl_read_counter(struct perf_event *event) | |
153 | { | |
154 | u64 raw; | |
155 | rdmsrl(event->hw.event_base, raw); | |
156 | return raw; | |
157 | } | |
158 | ||
64552396 | 159 | static inline u64 rapl_scale(u64 v, int cfg) |
4788e5b4 | 160 | { |
64552396 | 161 | if (cfg > NR_RAPL_DOMAINS) { |
512089d9 | 162 | pr_warn("Invalid domain %d, failed to scale data\n", cfg); |
64552396 JP |
163 | return v; |
164 | } | |
4788e5b4 SE |
165 | /* |
166 | * scale delta to smallest unit (1/2^32) | |
167 | * users must then scale back: count * 1/(1e9*2^32) to get Joules | |
168 | * or use ldexp(count, -32). | |
169 | * Watts = Joules/Time delta | |
170 | */ | |
64552396 | 171 | return v << (32 - rapl_hw_unit[cfg - 1]); |
4788e5b4 SE |
172 | } |
173 | ||
174 | static u64 rapl_event_update(struct perf_event *event) | |
175 | { | |
176 | struct hw_perf_event *hwc = &event->hw; | |
177 | u64 prev_raw_count, new_raw_count; | |
178 | s64 delta, sdelta; | |
179 | int shift = RAPL_CNTR_WIDTH; | |
180 | ||
181 | again: | |
182 | prev_raw_count = local64_read(&hwc->prev_count); | |
183 | rdmsrl(event->hw.event_base, new_raw_count); | |
184 | ||
185 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
186 | new_raw_count) != prev_raw_count) { | |
187 | cpu_relax(); | |
188 | goto again; | |
189 | } | |
190 | ||
191 | /* | |
192 | * Now we have the new raw value and have updated the prev | |
193 | * timestamp already. We can now calculate the elapsed delta | |
194 | * (event-)time and add that to the generic event. | |
195 | * | |
196 | * Careful, not all hw sign-extends above the physical width | |
197 | * of the count. | |
198 | */ | |
199 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
200 | delta >>= shift; | |
201 | ||
64552396 | 202 | sdelta = rapl_scale(delta, event->hw.config); |
4788e5b4 SE |
203 | |
204 | local64_add(sdelta, &event->count); | |
205 | ||
206 | return new_raw_count; | |
207 | } | |
208 | ||
65661f96 SE |
209 | static void rapl_start_hrtimer(struct rapl_pmu *pmu) |
210 | { | |
514c2304 TG |
211 | hrtimer_start(&pmu->hrtimer, pmu->timer_interval, |
212 | HRTIMER_MODE_REL_PINNED); | |
65661f96 SE |
213 | } |
214 | ||
65661f96 SE |
215 | static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) |
216 | { | |
8a6d2f8f | 217 | struct rapl_pmu *pmu = container_of(hrtimer, struct rapl_pmu, hrtimer); |
65661f96 SE |
218 | struct perf_event *event; |
219 | unsigned long flags; | |
220 | ||
221 | if (!pmu->n_active) | |
222 | return HRTIMER_NORESTART; | |
223 | ||
a208749c | 224 | raw_spin_lock_irqsave(&pmu->lock, flags); |
65661f96 | 225 | |
7162b8fe | 226 | list_for_each_entry(event, &pmu->active_list, active_entry) |
65661f96 | 227 | rapl_event_update(event); |
65661f96 | 228 | |
a208749c | 229 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
65661f96 SE |
230 | |
231 | hrtimer_forward_now(hrtimer, pmu->timer_interval); | |
232 | ||
233 | return HRTIMER_RESTART; | |
234 | } | |
235 | ||
236 | static void rapl_hrtimer_init(struct rapl_pmu *pmu) | |
237 | { | |
238 | struct hrtimer *hr = &pmu->hrtimer; | |
239 | ||
240 | hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
241 | hr->function = rapl_hrtimer_handle; | |
242 | } | |
243 | ||
4788e5b4 SE |
244 | static void __rapl_pmu_event_start(struct rapl_pmu *pmu, |
245 | struct perf_event *event) | |
246 | { | |
247 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) | |
248 | return; | |
249 | ||
250 | event->hw.state = 0; | |
251 | ||
252 | list_add_tail(&event->active_entry, &pmu->active_list); | |
253 | ||
254 | local64_set(&event->hw.prev_count, rapl_read_counter(event)); | |
255 | ||
256 | pmu->n_active++; | |
65661f96 SE |
257 | if (pmu->n_active == 1) |
258 | rapl_start_hrtimer(pmu); | |
4788e5b4 SE |
259 | } |
260 | ||
261 | static void rapl_pmu_event_start(struct perf_event *event, int mode) | |
262 | { | |
8a6d2f8f | 263 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
264 | unsigned long flags; |
265 | ||
a208749c | 266 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 | 267 | __rapl_pmu_event_start(pmu, event); |
a208749c | 268 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
269 | } |
270 | ||
271 | static void rapl_pmu_event_stop(struct perf_event *event, int mode) | |
272 | { | |
8a6d2f8f | 273 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
274 | struct hw_perf_event *hwc = &event->hw; |
275 | unsigned long flags; | |
276 | ||
a208749c | 277 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 SE |
278 | |
279 | /* mark event as deactivated and stopped */ | |
280 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
281 | WARN_ON_ONCE(pmu->n_active <= 0); | |
282 | pmu->n_active--; | |
65661f96 | 283 | if (pmu->n_active == 0) |
7162b8fe | 284 | hrtimer_cancel(&pmu->hrtimer); |
4788e5b4 SE |
285 | |
286 | list_del(&event->active_entry); | |
287 | ||
288 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
289 | hwc->state |= PERF_HES_STOPPED; | |
290 | } | |
291 | ||
292 | /* check if update of sw counter is necessary */ | |
293 | if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | |
294 | /* | |
295 | * Drain the remaining delta count out of a event | |
296 | * that we are disabling: | |
297 | */ | |
298 | rapl_event_update(event); | |
299 | hwc->state |= PERF_HES_UPTODATE; | |
300 | } | |
301 | ||
a208749c | 302 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
303 | } |
304 | ||
305 | static int rapl_pmu_event_add(struct perf_event *event, int mode) | |
306 | { | |
8a6d2f8f | 307 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
308 | struct hw_perf_event *hwc = &event->hw; |
309 | unsigned long flags; | |
310 | ||
a208749c | 311 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 SE |
312 | |
313 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
314 | ||
315 | if (mode & PERF_EF_START) | |
316 | __rapl_pmu_event_start(pmu, event); | |
317 | ||
a208749c | 318 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
319 | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static void rapl_pmu_event_del(struct perf_event *event, int flags) | |
324 | { | |
325 | rapl_pmu_event_stop(event, PERF_EF_UPDATE); | |
326 | } | |
327 | ||
328 | static int rapl_pmu_event_init(struct perf_event *event) | |
329 | { | |
330 | u64 cfg = event->attr.config & RAPL_EVENT_MASK; | |
331 | int bit, msr, ret = 0; | |
9de8d686 | 332 | struct rapl_pmu *pmu; |
4788e5b4 SE |
333 | |
334 | /* only look at RAPL events */ | |
9de8d686 | 335 | if (event->attr.type != rapl_pmus->pmu.type) |
4788e5b4 SE |
336 | return -ENOENT; |
337 | ||
338 | /* check only supported bits are set */ | |
339 | if (event->attr.config & ~RAPL_EVENT_MASK) | |
340 | return -EINVAL; | |
341 | ||
8a6d2f8f TG |
342 | if (event->cpu < 0) |
343 | return -EINVAL; | |
344 | ||
4788e5b4 SE |
345 | /* |
346 | * check event is known (determines counter) | |
347 | */ | |
348 | switch (cfg) { | |
349 | case INTEL_RAPL_PP0: | |
350 | bit = RAPL_IDX_PP0_NRG_STAT; | |
351 | msr = MSR_PP0_ENERGY_STATUS; | |
352 | break; | |
353 | case INTEL_RAPL_PKG: | |
354 | bit = RAPL_IDX_PKG_NRG_STAT; | |
355 | msr = MSR_PKG_ENERGY_STATUS; | |
356 | break; | |
357 | case INTEL_RAPL_RAM: | |
358 | bit = RAPL_IDX_RAM_NRG_STAT; | |
359 | msr = MSR_DRAM_ENERGY_STATUS; | |
360 | break; | |
f228c5b8 SE |
361 | case INTEL_RAPL_PP1: |
362 | bit = RAPL_IDX_PP1_NRG_STAT; | |
363 | msr = MSR_PP1_ENERGY_STATUS; | |
364 | break; | |
4788e5b4 SE |
365 | default: |
366 | return -EINVAL; | |
367 | } | |
368 | /* check event supported */ | |
369 | if (!(rapl_cntr_mask & (1 << bit))) | |
370 | return -EINVAL; | |
371 | ||
372 | /* unsupported modes and filters */ | |
373 | if (event->attr.exclude_user || | |
374 | event->attr.exclude_kernel || | |
375 | event->attr.exclude_hv || | |
376 | event->attr.exclude_idle || | |
377 | event->attr.exclude_host || | |
378 | event->attr.exclude_guest || | |
379 | event->attr.sample_period) /* no sampling */ | |
380 | return -EINVAL; | |
381 | ||
382 | /* must be done before validate_group */ | |
9de8d686 | 383 | pmu = cpu_to_rapl_pmu(event->cpu); |
8a6d2f8f TG |
384 | event->cpu = pmu->cpu; |
385 | event->pmu_private = pmu; | |
4788e5b4 SE |
386 | event->hw.event_base = msr; |
387 | event->hw.config = cfg; | |
388 | event->hw.idx = bit; | |
389 | ||
390 | return ret; | |
391 | } | |
392 | ||
393 | static void rapl_pmu_event_read(struct perf_event *event) | |
394 | { | |
395 | rapl_event_update(event); | |
396 | } | |
397 | ||
398 | static ssize_t rapl_get_attr_cpumask(struct device *dev, | |
399 | struct device_attribute *attr, char *buf) | |
400 | { | |
5aaba363 | 401 | return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask); |
4788e5b4 SE |
402 | } |
403 | ||
404 | static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL); | |
405 | ||
406 | static struct attribute *rapl_pmu_attrs[] = { | |
407 | &dev_attr_cpumask.attr, | |
408 | NULL, | |
409 | }; | |
410 | ||
411 | static struct attribute_group rapl_pmu_attr_group = { | |
412 | .attrs = rapl_pmu_attrs, | |
413 | }; | |
414 | ||
433678bd SE |
415 | RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); |
416 | RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); | |
417 | RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); | |
418 | RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04"); | |
4788e5b4 | 419 | |
433678bd SE |
420 | RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); |
421 | RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); | |
422 | RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); | |
423 | RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); | |
4788e5b4 SE |
424 | |
425 | /* | |
426 | * we compute in 0.23 nJ increments regardless of MSR | |
427 | */ | |
433678bd SE |
428 | RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); |
429 | RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); | |
430 | RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); | |
431 | RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); | |
4788e5b4 SE |
432 | |
433 | static struct attribute *rapl_events_srv_attr[] = { | |
434 | EVENT_PTR(rapl_cores), | |
435 | EVENT_PTR(rapl_pkg), | |
436 | EVENT_PTR(rapl_ram), | |
437 | ||
438 | EVENT_PTR(rapl_cores_unit), | |
439 | EVENT_PTR(rapl_pkg_unit), | |
440 | EVENT_PTR(rapl_ram_unit), | |
441 | ||
442 | EVENT_PTR(rapl_cores_scale), | |
443 | EVENT_PTR(rapl_pkg_scale), | |
444 | EVENT_PTR(rapl_ram_scale), | |
445 | NULL, | |
446 | }; | |
447 | ||
448 | static struct attribute *rapl_events_cln_attr[] = { | |
449 | EVENT_PTR(rapl_cores), | |
450 | EVENT_PTR(rapl_pkg), | |
f228c5b8 | 451 | EVENT_PTR(rapl_gpu), |
4788e5b4 SE |
452 | |
453 | EVENT_PTR(rapl_cores_unit), | |
454 | EVENT_PTR(rapl_pkg_unit), | |
f228c5b8 | 455 | EVENT_PTR(rapl_gpu_unit), |
4788e5b4 SE |
456 | |
457 | EVENT_PTR(rapl_cores_scale), | |
458 | EVENT_PTR(rapl_pkg_scale), | |
f228c5b8 | 459 | EVENT_PTR(rapl_gpu_scale), |
4788e5b4 SE |
460 | NULL, |
461 | }; | |
462 | ||
e69af465 VW |
463 | static struct attribute *rapl_events_hsw_attr[] = { |
464 | EVENT_PTR(rapl_cores), | |
465 | EVENT_PTR(rapl_pkg), | |
466 | EVENT_PTR(rapl_gpu), | |
467 | EVENT_PTR(rapl_ram), | |
468 | ||
469 | EVENT_PTR(rapl_cores_unit), | |
470 | EVENT_PTR(rapl_pkg_unit), | |
471 | EVENT_PTR(rapl_gpu_unit), | |
472 | EVENT_PTR(rapl_ram_unit), | |
473 | ||
474 | EVENT_PTR(rapl_cores_scale), | |
475 | EVENT_PTR(rapl_pkg_scale), | |
476 | EVENT_PTR(rapl_gpu_scale), | |
477 | EVENT_PTR(rapl_ram_scale), | |
478 | NULL, | |
479 | }; | |
480 | ||
3a2a7797 DC |
481 | static struct attribute *rapl_events_knl_attr[] = { |
482 | EVENT_PTR(rapl_pkg), | |
483 | EVENT_PTR(rapl_ram), | |
484 | ||
485 | EVENT_PTR(rapl_pkg_unit), | |
486 | EVENT_PTR(rapl_ram_unit), | |
487 | ||
488 | EVENT_PTR(rapl_pkg_scale), | |
489 | EVENT_PTR(rapl_ram_scale), | |
490 | NULL, | |
491 | }; | |
492 | ||
4788e5b4 SE |
493 | static struct attribute_group rapl_pmu_events_group = { |
494 | .name = "events", | |
495 | .attrs = NULL, /* patched at runtime */ | |
496 | }; | |
497 | ||
498 | DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7"); | |
499 | static struct attribute *rapl_formats_attr[] = { | |
500 | &format_attr_event.attr, | |
501 | NULL, | |
502 | }; | |
503 | ||
504 | static struct attribute_group rapl_pmu_format_group = { | |
505 | .name = "format", | |
506 | .attrs = rapl_formats_attr, | |
507 | }; | |
508 | ||
509 | const struct attribute_group *rapl_attr_groups[] = { | |
510 | &rapl_pmu_attr_group, | |
511 | &rapl_pmu_format_group, | |
512 | &rapl_pmu_events_group, | |
513 | NULL, | |
514 | }; | |
515 | ||
4788e5b4 SE |
516 | static void rapl_cpu_exit(int cpu) |
517 | { | |
9de8d686 TG |
518 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
519 | int target; | |
4788e5b4 | 520 | |
9de8d686 TG |
521 | /* Check if exiting cpu is used for collecting rapl events */ |
522 | if (!cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask)) | |
523 | return; | |
4788e5b4 | 524 | |
9de8d686 TG |
525 | pmu->cpu = -1; |
526 | /* Find a new cpu to collect rapl events */ | |
527 | target = cpumask_any_but(topology_core_cpumask(cpu), cpu); | |
65661f96 | 528 | |
9de8d686 TG |
529 | /* Migrate rapl events to the new target */ |
530 | if (target < nr_cpu_ids) { | |
531 | cpumask_set_cpu(target, &rapl_cpu_mask); | |
532 | pmu->cpu = target; | |
533 | perf_pmu_migrate_context(pmu->pmu, cpu, target); | |
534 | } | |
4788e5b4 SE |
535 | } |
536 | ||
537 | static void rapl_cpu_init(int cpu) | |
538 | { | |
9de8d686 TG |
539 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
540 | int target; | |
541 | ||
542 | /* | |
543 | * Check if there is an online cpu in the package which collects rapl | |
544 | * events already. | |
545 | */ | |
546 | target = cpumask_any_and(&rapl_cpu_mask, topology_core_cpumask(cpu)); | |
547 | if (target < nr_cpu_ids) | |
548 | return; | |
4788e5b4 | 549 | |
4788e5b4 | 550 | cpumask_set_cpu(cpu, &rapl_cpu_mask); |
9de8d686 | 551 | pmu->cpu = cpu; |
4788e5b4 SE |
552 | } |
553 | ||
554 | static int rapl_cpu_prepare(int cpu) | |
555 | { | |
9de8d686 | 556 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
4788e5b4 SE |
557 | |
558 | if (pmu) | |
559 | return 0; | |
560 | ||
4788e5b4 SE |
561 | pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu)); |
562 | if (!pmu) | |
9de8d686 | 563 | return -ENOMEM; |
4788e5b4 | 564 | |
9de8d686 | 565 | raw_spin_lock_init(&pmu->lock); |
4788e5b4 | 566 | INIT_LIST_HEAD(&pmu->active_list); |
9de8d686 | 567 | pmu->pmu = &rapl_pmus->pmu; |
75c7003f | 568 | pmu->timer_interval = ms_to_ktime(rapl_timer_ms); |
9de8d686 | 569 | pmu->cpu = -1; |
65661f96 | 570 | rapl_hrtimer_init(pmu); |
9de8d686 | 571 | rapl_pmus->pmus[topology_logical_package_id(cpu)] = pmu; |
4788e5b4 SE |
572 | return 0; |
573 | } | |
574 | ||
575 | static int rapl_cpu_notifier(struct notifier_block *self, | |
576 | unsigned long action, void *hcpu) | |
577 | { | |
578 | unsigned int cpu = (long)hcpu; | |
579 | ||
580 | switch (action & ~CPU_TASKS_FROZEN) { | |
581 | case CPU_UP_PREPARE: | |
582 | rapl_cpu_prepare(cpu); | |
583 | break; | |
9de8d686 TG |
584 | |
585 | case CPU_DOWN_FAILED: | |
4788e5b4 | 586 | case CPU_ONLINE: |
9de8d686 | 587 | rapl_cpu_init(cpu); |
4788e5b4 | 588 | break; |
9de8d686 | 589 | |
4788e5b4 SE |
590 | case CPU_DOWN_PREPARE: |
591 | rapl_cpu_exit(cpu); | |
592 | break; | |
4788e5b4 | 593 | } |
4788e5b4 SE |
594 | return NOTIFY_OK; |
595 | } | |
596 | ||
4b6e2571 KL |
597 | static struct notifier_block rapl_cpu_nb = { |
598 | .notifier_call = rapl_cpu_notifier, | |
599 | .priority = CPU_PRI_PERF + 1, | |
600 | }; | |
601 | ||
7a869805 | 602 | static int rapl_check_hw_unit(bool apply_quirk) |
64552396 JP |
603 | { |
604 | u64 msr_rapl_power_unit_bits; | |
605 | int i; | |
606 | ||
607 | /* protect rdmsrl() to handle virtualization */ | |
608 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits)) | |
609 | return -1; | |
610 | for (i = 0; i < NR_RAPL_DOMAINS; i++) | |
611 | rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL; | |
612 | ||
7a869805 BP |
613 | /* |
614 | * DRAM domain on HSW server and KNL has fixed energy unit which can be | |
615 | * different than the unit from power unit MSR. See | |
616 | * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2 | |
617 | * of 2. Datasheet, September 2014, Reference Number: 330784-001 " | |
618 | */ | |
619 | if (apply_quirk) | |
620 | rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16; | |
75c7003f TG |
621 | |
622 | /* | |
623 | * Calculate the timer rate: | |
624 | * Use reference of 200W for scaling the timeout to avoid counter | |
625 | * overflows. 200W = 200 Joules/sec | |
626 | * Divide interval by 2 to avoid lockstep (2 * 100) | |
627 | * if hw unit is 32, then we use 2 ms 1/200/2 | |
628 | */ | |
629 | rapl_timer_ms = 2; | |
630 | if (rapl_hw_unit[0] < 32) { | |
631 | rapl_timer_ms = (1000 / (2 * 100)); | |
632 | rapl_timer_ms *= (1ULL << (32 - rapl_hw_unit[0] - 1)); | |
633 | } | |
64552396 JP |
634 | return 0; |
635 | } | |
636 | ||
512089d9 TG |
637 | static void __init rapl_advertise(void) |
638 | { | |
639 | int i; | |
640 | ||
641 | pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\n", | |
642 | hweight32(rapl_cntr_mask), rapl_timer_ms); | |
643 | ||
644 | for (i = 0; i < NR_RAPL_DOMAINS; i++) { | |
645 | if (rapl_cntr_mask & (1 << i)) { | |
646 | pr_info("hw unit of domain %s 2^-%d Joules\n", | |
647 | rapl_domain_names[i], rapl_hw_unit[i]); | |
648 | } | |
649 | } | |
650 | } | |
651 | ||
7162b8fe TG |
652 | static int __init rapl_prepare_cpus(void) |
653 | { | |
9de8d686 | 654 | unsigned int cpu, pkg; |
7162b8fe TG |
655 | int ret; |
656 | ||
657 | for_each_online_cpu(cpu) { | |
9de8d686 TG |
658 | pkg = topology_logical_package_id(cpu); |
659 | if (rapl_pmus->pmus[pkg]) | |
660 | continue; | |
661 | ||
7162b8fe TG |
662 | ret = rapl_cpu_prepare(cpu); |
663 | if (ret) | |
664 | return ret; | |
665 | rapl_cpu_init(cpu); | |
666 | } | |
667 | return 0; | |
668 | } | |
669 | ||
4b6e2571 | 670 | static void cleanup_rapl_pmus(void) |
55f2890f | 671 | { |
9de8d686 TG |
672 | int i; |
673 | ||
674 | for (i = 0; i < rapl_pmus->maxpkg; i++) | |
675 | kfree(rapl_pmus->pmus + i); | |
676 | kfree(rapl_pmus); | |
677 | } | |
55f2890f | 678 | |
9de8d686 TG |
679 | static int __init init_rapl_pmus(void) |
680 | { | |
681 | int maxpkg = topology_max_packages(); | |
682 | size_t size; | |
683 | ||
684 | size = sizeof(*rapl_pmus) + maxpkg * sizeof(struct rapl_pmu *); | |
685 | rapl_pmus = kzalloc(size, GFP_KERNEL); | |
686 | if (!rapl_pmus) | |
687 | return -ENOMEM; | |
688 | ||
689 | rapl_pmus->maxpkg = maxpkg; | |
690 | rapl_pmus->pmu.attr_groups = rapl_attr_groups; | |
691 | rapl_pmus->pmu.task_ctx_nr = perf_invalid_context; | |
692 | rapl_pmus->pmu.event_init = rapl_pmu_event_init; | |
693 | rapl_pmus->pmu.add = rapl_pmu_event_add; | |
694 | rapl_pmus->pmu.del = rapl_pmu_event_del; | |
695 | rapl_pmus->pmu.start = rapl_pmu_event_start; | |
696 | rapl_pmus->pmu.stop = rapl_pmu_event_stop; | |
697 | rapl_pmus->pmu.read = rapl_pmu_event_read; | |
698 | return 0; | |
55f2890f TG |
699 | } |
700 | ||
4b6e2571 KL |
701 | #define X86_RAPL_MODEL_MATCH(model, init) \ |
702 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init } | |
703 | ||
704 | struct intel_rapl_init_fun { | |
705 | bool apply_quirk; | |
706 | int cntr_mask; | |
707 | struct attribute **attrs; | |
708 | }; | |
709 | ||
710 | static const struct intel_rapl_init_fun snb_rapl_init __initconst = { | |
711 | .apply_quirk = false, | |
712 | .cntr_mask = RAPL_IDX_CLN, | |
713 | .attrs = rapl_events_cln_attr, | |
714 | }; | |
715 | ||
716 | static const struct intel_rapl_init_fun hsx_rapl_init __initconst = { | |
717 | .apply_quirk = true, | |
718 | .cntr_mask = RAPL_IDX_SRV, | |
719 | .attrs = rapl_events_srv_attr, | |
720 | }; | |
721 | ||
722 | static const struct intel_rapl_init_fun hsw_rapl_init __initconst = { | |
723 | .apply_quirk = false, | |
724 | .cntr_mask = RAPL_IDX_HSW, | |
725 | .attrs = rapl_events_hsw_attr, | |
726 | }; | |
727 | ||
728 | static const struct intel_rapl_init_fun snbep_rapl_init __initconst = { | |
729 | .apply_quirk = false, | |
730 | .cntr_mask = RAPL_IDX_SRV, | |
731 | .attrs = rapl_events_srv_attr, | |
732 | }; | |
733 | ||
734 | static const struct intel_rapl_init_fun knl_rapl_init __initconst = { | |
735 | .apply_quirk = true, | |
736 | .cntr_mask = RAPL_IDX_KNL, | |
737 | .attrs = rapl_events_knl_attr, | |
738 | }; | |
739 | ||
7162b8fe | 740 | static const struct x86_cpu_id rapl_cpu_match[] __initconst = { |
4b6e2571 KL |
741 | X86_RAPL_MODEL_MATCH(42, snb_rapl_init), /* Sandy Bridge */ |
742 | X86_RAPL_MODEL_MATCH(58, snb_rapl_init), /* Ivy Bridge */ | |
743 | X86_RAPL_MODEL_MATCH(63, hsx_rapl_init), /* Haswell-Server */ | |
744 | X86_RAPL_MODEL_MATCH(79, hsx_rapl_init), /* Broadwell-Server */ | |
745 | X86_RAPL_MODEL_MATCH(60, hsw_rapl_init), /* Haswell */ | |
746 | X86_RAPL_MODEL_MATCH(69, hsw_rapl_init), /* Haswell-Celeron */ | |
65cbbd03 | 747 | X86_RAPL_MODEL_MATCH(70, hsw_rapl_init), /* Haswell GT3e */ |
4b6e2571 KL |
748 | X86_RAPL_MODEL_MATCH(61, hsw_rapl_init), /* Broadwell */ |
749 | X86_RAPL_MODEL_MATCH(71, hsw_rapl_init), /* Broadwell-H */ | |
750 | X86_RAPL_MODEL_MATCH(45, snbep_rapl_init), /* Sandy Bridge-EP */ | |
751 | X86_RAPL_MODEL_MATCH(62, snbep_rapl_init), /* IvyTown */ | |
752 | X86_RAPL_MODEL_MATCH(87, knl_rapl_init), /* Knights Landing */ | |
753 | {}, | |
4788e5b4 SE |
754 | }; |
755 | ||
4b6e2571 KL |
756 | MODULE_DEVICE_TABLE(x86cpu, rapl_cpu_match); |
757 | ||
4788e5b4 SE |
758 | static int __init rapl_pmu_init(void) |
759 | { | |
4b6e2571 KL |
760 | const struct x86_cpu_id *id; |
761 | struct intel_rapl_init_fun *rapl_init; | |
762 | bool apply_quirk; | |
7162b8fe | 763 | int ret; |
4788e5b4 | 764 | |
4b6e2571 KL |
765 | id = x86_match_cpu(rapl_cpu_match); |
766 | if (!id) | |
55f2890f | 767 | return -ENODEV; |
4788e5b4 | 768 | |
4b6e2571 KL |
769 | rapl_init = (struct intel_rapl_init_fun *)id->driver_data; |
770 | apply_quirk = rapl_init->apply_quirk; | |
771 | rapl_cntr_mask = rapl_init->cntr_mask; | |
772 | rapl_pmu_events_group.attrs = rapl_init->attrs; | |
55f2890f | 773 | |
7a869805 | 774 | ret = rapl_check_hw_unit(apply_quirk); |
64552396 JP |
775 | if (ret) |
776 | return ret; | |
fd537e56 | 777 | |
9de8d686 TG |
778 | ret = init_rapl_pmus(); |
779 | if (ret) | |
780 | return ret; | |
781 | ||
fd537e56 | 782 | cpu_notifier_register_begin(); |
4788e5b4 | 783 | |
7162b8fe TG |
784 | ret = rapl_prepare_cpus(); |
785 | if (ret) | |
786 | goto out; | |
4788e5b4 | 787 | |
9de8d686 | 788 | ret = perf_pmu_register(&rapl_pmus->pmu, "power", -1); |
512089d9 | 789 | if (ret) |
55f2890f | 790 | goto out; |
4788e5b4 | 791 | |
4b6e2571 | 792 | __register_cpu_notifier(&rapl_cpu_nb); |
75c7003f | 793 | cpu_notifier_register_done(); |
512089d9 | 794 | rapl_advertise(); |
4788e5b4 | 795 | return 0; |
55f2890f TG |
796 | |
797 | out: | |
512089d9 | 798 | pr_warn("Initialization failed (%d), disabled\n", ret); |
55f2890f TG |
799 | cleanup_rapl_pmus(); |
800 | cpu_notifier_register_done(); | |
801 | return ret; | |
4788e5b4 | 802 | } |
4b6e2571 KL |
803 | module_init(rapl_pmu_init); |
804 | ||
805 | static void __exit intel_rapl_exit(void) | |
806 | { | |
807 | cpu_notifier_register_begin(); | |
808 | __unregister_cpu_notifier(&rapl_cpu_nb); | |
809 | perf_pmu_unregister(&rapl_pmus->pmu); | |
810 | cleanup_rapl_pmus(); | |
811 | cpu_notifier_register_done(); | |
812 | } | |
813 | module_exit(intel_rapl_exit); |