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Commit | Line | Data |
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6bcb2db5 | 1 | #include "uncore.h" |
087bfbb0 YZ |
2 | |
3 | static struct intel_uncore_type *empty_uncore[] = { NULL, }; | |
514b2346 YZ |
4 | struct intel_uncore_type **uncore_msr_uncores = empty_uncore; |
5 | struct intel_uncore_type **uncore_pci_uncores = empty_uncore; | |
14371cce | 6 | |
514b2346 YZ |
7 | static bool pcidrv_registered; |
8 | struct pci_driver *uncore_pci_driver; | |
9 | /* pci bus to socket mapping */ | |
712df65c TI |
10 | DEFINE_RAW_SPINLOCK(pci2phy_map_lock); |
11 | struct list_head pci2phy_map_head = LIST_HEAD_INIT(pci2phy_map_head); | |
514b2346 | 12 | struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX]; |
899396cf | 13 | |
14371cce | 14 | static DEFINE_RAW_SPINLOCK(uncore_box_lock); |
087bfbb0 YZ |
15 | /* mask of cpus that collect uncore events */ |
16 | static cpumask_t uncore_cpu_mask; | |
17 | ||
18 | /* constraint for the fixed counter */ | |
514b2346 | 19 | static struct event_constraint uncore_constraint_fixed = |
087bfbb0 | 20 | EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL); |
514b2346 | 21 | struct event_constraint uncore_constraint_empty = |
6a67943a | 22 | EVENT_CONSTRAINT(0, 0, 0); |
087bfbb0 | 23 | |
712df65c TI |
24 | int uncore_pcibus_to_physid(struct pci_bus *bus) |
25 | { | |
26 | struct pci2phy_map *map; | |
27 | int phys_id = -1; | |
28 | ||
29 | raw_spin_lock(&pci2phy_map_lock); | |
30 | list_for_each_entry(map, &pci2phy_map_head, list) { | |
31 | if (map->segment == pci_domain_nr(bus)) { | |
32 | phys_id = map->pbus_to_physid[bus->number]; | |
33 | break; | |
34 | } | |
35 | } | |
36 | raw_spin_unlock(&pci2phy_map_lock); | |
37 | ||
38 | return phys_id; | |
39 | } | |
40 | ||
4f089678 TG |
41 | static void uncore_free_pcibus_map(void) |
42 | { | |
43 | struct pci2phy_map *map, *tmp; | |
44 | ||
45 | list_for_each_entry_safe(map, tmp, &pci2phy_map_head, list) { | |
46 | list_del(&map->list); | |
47 | kfree(map); | |
48 | } | |
49 | } | |
50 | ||
712df65c TI |
51 | struct pci2phy_map *__find_pci2phy_map(int segment) |
52 | { | |
53 | struct pci2phy_map *map, *alloc = NULL; | |
54 | int i; | |
55 | ||
56 | lockdep_assert_held(&pci2phy_map_lock); | |
57 | ||
58 | lookup: | |
59 | list_for_each_entry(map, &pci2phy_map_head, list) { | |
60 | if (map->segment == segment) | |
61 | goto end; | |
62 | } | |
63 | ||
64 | if (!alloc) { | |
65 | raw_spin_unlock(&pci2phy_map_lock); | |
66 | alloc = kmalloc(sizeof(struct pci2phy_map), GFP_KERNEL); | |
67 | raw_spin_lock(&pci2phy_map_lock); | |
68 | ||
69 | if (!alloc) | |
70 | return NULL; | |
71 | ||
72 | goto lookup; | |
73 | } | |
74 | ||
75 | map = alloc; | |
76 | alloc = NULL; | |
77 | map->segment = segment; | |
78 | for (i = 0; i < 256; i++) | |
79 | map->pbus_to_physid[i] = -1; | |
80 | list_add_tail(&map->list, &pci2phy_map_head); | |
81 | ||
82 | end: | |
83 | kfree(alloc); | |
84 | return map; | |
85 | } | |
86 | ||
514b2346 YZ |
87 | ssize_t uncore_event_show(struct kobject *kobj, |
88 | struct kobj_attribute *attr, char *buf) | |
89 | { | |
90 | struct uncore_event_desc *event = | |
91 | container_of(attr, struct uncore_event_desc, attr); | |
92 | return sprintf(buf, "%s", event->config); | |
93 | } | |
94 | ||
514b2346 | 95 | struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event) |
001e413f SE |
96 | { |
97 | return container_of(event->pmu, struct intel_uncore_pmu, pmu); | |
98 | } | |
99 | ||
514b2346 | 100 | struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu) |
001e413f SE |
101 | { |
102 | struct intel_uncore_box *box; | |
103 | ||
104 | box = *per_cpu_ptr(pmu->box, cpu); | |
105 | if (box) | |
106 | return box; | |
107 | ||
108 | raw_spin_lock(&uncore_box_lock); | |
4f971248 AK |
109 | /* Recheck in lock to handle races. */ |
110 | if (*per_cpu_ptr(pmu->box, cpu)) | |
111 | goto out; | |
001e413f SE |
112 | list_for_each_entry(box, &pmu->box_list, list) { |
113 | if (box->phys_id == topology_physical_package_id(cpu)) { | |
114 | atomic_inc(&box->refcnt); | |
115 | *per_cpu_ptr(pmu->box, cpu) = box; | |
116 | break; | |
117 | } | |
118 | } | |
4f971248 | 119 | out: |
001e413f SE |
120 | raw_spin_unlock(&uncore_box_lock); |
121 | ||
122 | return *per_cpu_ptr(pmu->box, cpu); | |
123 | } | |
124 | ||
514b2346 | 125 | struct intel_uncore_box *uncore_event_to_box(struct perf_event *event) |
001e413f SE |
126 | { |
127 | /* | |
128 | * perf core schedules event on the basis of cpu, uncore events are | |
129 | * collected by one of the cpus inside a physical package. | |
130 | */ | |
131 | return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id()); | |
132 | } | |
133 | ||
514b2346 | 134 | u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event) |
254298c7 YZ |
135 | { |
136 | u64 count; | |
137 | ||
138 | rdmsrl(event->hw.event_base, count); | |
139 | ||
140 | return count; | |
141 | } | |
142 | ||
143 | /* | |
144 | * generic get constraint function for shared match/mask registers. | |
145 | */ | |
514b2346 | 146 | struct event_constraint * |
254298c7 YZ |
147 | uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event) |
148 | { | |
149 | struct intel_uncore_extra_reg *er; | |
150 | struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; | |
151 | struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; | |
152 | unsigned long flags; | |
153 | bool ok = false; | |
154 | ||
155 | /* | |
156 | * reg->alloc can be set due to existing state, so for fake box we | |
157 | * need to ignore this, otherwise we might fail to allocate proper | |
158 | * fake state for this extra reg constraint. | |
159 | */ | |
160 | if (reg1->idx == EXTRA_REG_NONE || | |
161 | (!uncore_box_is_fake(box) && reg1->alloc)) | |
162 | return NULL; | |
163 | ||
164 | er = &box->shared_regs[reg1->idx]; | |
165 | raw_spin_lock_irqsave(&er->lock, flags); | |
166 | if (!atomic_read(&er->ref) || | |
167 | (er->config1 == reg1->config && er->config2 == reg2->config)) { | |
168 | atomic_inc(&er->ref); | |
169 | er->config1 = reg1->config; | |
170 | er->config2 = reg2->config; | |
171 | ok = true; | |
172 | } | |
173 | raw_spin_unlock_irqrestore(&er->lock, flags); | |
174 | ||
175 | if (ok) { | |
176 | if (!uncore_box_is_fake(box)) | |
177 | reg1->alloc = 1; | |
178 | return NULL; | |
179 | } | |
180 | ||
514b2346 | 181 | return &uncore_constraint_empty; |
254298c7 YZ |
182 | } |
183 | ||
514b2346 | 184 | void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event) |
254298c7 YZ |
185 | { |
186 | struct intel_uncore_extra_reg *er; | |
187 | struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; | |
188 | ||
189 | /* | |
190 | * Only put constraint if extra reg was actually allocated. Also | |
191 | * takes care of event which do not use an extra shared reg. | |
192 | * | |
193 | * Also, if this is a fake box we shouldn't touch any event state | |
194 | * (reg->alloc) and we don't care about leaving inconsistent box | |
195 | * state either since it will be thrown out. | |
196 | */ | |
197 | if (uncore_box_is_fake(box) || !reg1->alloc) | |
198 | return; | |
199 | ||
200 | er = &box->shared_regs[reg1->idx]; | |
201 | atomic_dec(&er->ref); | |
202 | reg1->alloc = 0; | |
203 | } | |
204 | ||
514b2346 | 205 | u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx) |
46bdd905 YZ |
206 | { |
207 | struct intel_uncore_extra_reg *er; | |
208 | unsigned long flags; | |
209 | u64 config; | |
210 | ||
211 | er = &box->shared_regs[idx]; | |
212 | ||
213 | raw_spin_lock_irqsave(&er->lock, flags); | |
214 | config = er->config; | |
215 | raw_spin_unlock_irqrestore(&er->lock, flags); | |
216 | ||
217 | return config; | |
218 | } | |
219 | ||
254298c7 | 220 | static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx) |
087bfbb0 YZ |
221 | { |
222 | struct hw_perf_event *hwc = &event->hw; | |
223 | ||
224 | hwc->idx = idx; | |
225 | hwc->last_tag = ++box->tags[idx]; | |
226 | ||
227 | if (hwc->idx == UNCORE_PMC_IDX_FIXED) { | |
14371cce YZ |
228 | hwc->event_base = uncore_fixed_ctr(box); |
229 | hwc->config_base = uncore_fixed_ctl(box); | |
087bfbb0 YZ |
230 | return; |
231 | } | |
232 | ||
14371cce YZ |
233 | hwc->config_base = uncore_event_ctl(box, hwc->idx); |
234 | hwc->event_base = uncore_perf_ctr(box, hwc->idx); | |
087bfbb0 YZ |
235 | } |
236 | ||
514b2346 | 237 | void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event) |
087bfbb0 YZ |
238 | { |
239 | u64 prev_count, new_count, delta; | |
240 | int shift; | |
241 | ||
242 | if (event->hw.idx >= UNCORE_PMC_IDX_FIXED) | |
243 | shift = 64 - uncore_fixed_ctr_bits(box); | |
244 | else | |
245 | shift = 64 - uncore_perf_ctr_bits(box); | |
246 | ||
247 | /* the hrtimer might modify the previous event value */ | |
248 | again: | |
249 | prev_count = local64_read(&event->hw.prev_count); | |
250 | new_count = uncore_read_counter(box, event); | |
251 | if (local64_xchg(&event->hw.prev_count, new_count) != prev_count) | |
252 | goto again; | |
253 | ||
254 | delta = (new_count << shift) - (prev_count << shift); | |
255 | delta >>= shift; | |
256 | ||
257 | local64_add(delta, &event->count); | |
258 | } | |
259 | ||
260 | /* | |
261 | * The overflow interrupt is unavailable for SandyBridge-EP, is broken | |
262 | * for SandyBridge. So we use hrtimer to periodically poll the counter | |
263 | * to avoid overflow. | |
264 | */ | |
265 | static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer) | |
266 | { | |
267 | struct intel_uncore_box *box; | |
ced2efb0 | 268 | struct perf_event *event; |
087bfbb0 YZ |
269 | unsigned long flags; |
270 | int bit; | |
271 | ||
272 | box = container_of(hrtimer, struct intel_uncore_box, hrtimer); | |
273 | if (!box->n_active || box->cpu != smp_processor_id()) | |
274 | return HRTIMER_NORESTART; | |
275 | /* | |
276 | * disable local interrupt to prevent uncore_pmu_event_start/stop | |
277 | * to interrupt the update process | |
278 | */ | |
279 | local_irq_save(flags); | |
280 | ||
ced2efb0 SE |
281 | /* |
282 | * handle boxes with an active event list as opposed to active | |
283 | * counters | |
284 | */ | |
285 | list_for_each_entry(event, &box->active_list, active_entry) { | |
286 | uncore_perf_event_update(box, event); | |
287 | } | |
288 | ||
087bfbb0 YZ |
289 | for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX) |
290 | uncore_perf_event_update(box, box->events[bit]); | |
291 | ||
292 | local_irq_restore(flags); | |
293 | ||
79859cce | 294 | hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration)); |
087bfbb0 YZ |
295 | return HRTIMER_RESTART; |
296 | } | |
297 | ||
514b2346 | 298 | void uncore_pmu_start_hrtimer(struct intel_uncore_box *box) |
087bfbb0 | 299 | { |
576b0704 TG |
300 | hrtimer_start(&box->hrtimer, ns_to_ktime(box->hrtimer_duration), |
301 | HRTIMER_MODE_REL_PINNED); | |
087bfbb0 YZ |
302 | } |
303 | ||
514b2346 | 304 | void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box) |
087bfbb0 YZ |
305 | { |
306 | hrtimer_cancel(&box->hrtimer); | |
307 | } | |
308 | ||
309 | static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box) | |
310 | { | |
311 | hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
312 | box->hrtimer.function = uncore_pmu_hrtimer; | |
313 | } | |
314 | ||
73c4427c | 315 | static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int node) |
087bfbb0 YZ |
316 | { |
317 | struct intel_uncore_box *box; | |
6a67943a | 318 | int i, size; |
087bfbb0 | 319 | |
254298c7 | 320 | size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg); |
6a67943a | 321 | |
73c4427c | 322 | box = kzalloc_node(size, GFP_KERNEL, node); |
087bfbb0 YZ |
323 | if (!box) |
324 | return NULL; | |
325 | ||
6a67943a YZ |
326 | for (i = 0; i < type->num_shared_regs; i++) |
327 | raw_spin_lock_init(&box->shared_regs[i].lock); | |
328 | ||
087bfbb0 YZ |
329 | uncore_pmu_init_hrtimer(box); |
330 | atomic_set(&box->refcnt, 1); | |
331 | box->cpu = -1; | |
332 | box->phys_id = -1; | |
333 | ||
79859cce SE |
334 | /* set default hrtimer timeout */ |
335 | box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL; | |
087bfbb0 | 336 | |
ced2efb0 | 337 | INIT_LIST_HEAD(&box->active_list); |
14371cce | 338 | |
087bfbb0 | 339 | return box; |
087bfbb0 YZ |
340 | } |
341 | ||
af91568e JO |
342 | /* |
343 | * Using uncore_pmu_event_init pmu event_init callback | |
344 | * as a detection point for uncore events. | |
345 | */ | |
346 | static int uncore_pmu_event_init(struct perf_event *event); | |
347 | ||
348 | static bool is_uncore_event(struct perf_event *event) | |
349 | { | |
350 | return event->pmu->event_init == uncore_pmu_event_init; | |
351 | } | |
352 | ||
254298c7 YZ |
353 | static int |
354 | uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp) | |
087bfbb0 YZ |
355 | { |
356 | struct perf_event *event; | |
357 | int n, max_count; | |
358 | ||
359 | max_count = box->pmu->type->num_counters; | |
360 | if (box->pmu->type->fixed_ctl) | |
361 | max_count++; | |
362 | ||
363 | if (box->n_events >= max_count) | |
364 | return -EINVAL; | |
365 | ||
366 | n = box->n_events; | |
af91568e JO |
367 | |
368 | if (is_uncore_event(leader)) { | |
369 | box->event_list[n] = leader; | |
370 | n++; | |
371 | } | |
372 | ||
087bfbb0 YZ |
373 | if (!dogrp) |
374 | return n; | |
375 | ||
376 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
af91568e JO |
377 | if (!is_uncore_event(event) || |
378 | event->state <= PERF_EVENT_STATE_OFF) | |
087bfbb0 YZ |
379 | continue; |
380 | ||
381 | if (n >= max_count) | |
382 | return -EINVAL; | |
383 | ||
384 | box->event_list[n] = event; | |
385 | n++; | |
386 | } | |
387 | return n; | |
388 | } | |
389 | ||
390 | static struct event_constraint * | |
254298c7 | 391 | uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event) |
087bfbb0 | 392 | { |
6a67943a | 393 | struct intel_uncore_type *type = box->pmu->type; |
087bfbb0 YZ |
394 | struct event_constraint *c; |
395 | ||
6a67943a YZ |
396 | if (type->ops->get_constraint) { |
397 | c = type->ops->get_constraint(box, event); | |
398 | if (c) | |
399 | return c; | |
400 | } | |
401 | ||
dbc33f70 | 402 | if (event->attr.config == UNCORE_FIXED_EVENT) |
514b2346 | 403 | return &uncore_constraint_fixed; |
087bfbb0 YZ |
404 | |
405 | if (type->constraints) { | |
406 | for_each_event_constraint(c, type->constraints) { | |
407 | if ((event->hw.config & c->cmask) == c->code) | |
408 | return c; | |
409 | } | |
410 | } | |
411 | ||
412 | return &type->unconstrainted; | |
413 | } | |
414 | ||
254298c7 | 415 | static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event) |
6a67943a YZ |
416 | { |
417 | if (box->pmu->type->ops->put_constraint) | |
418 | box->pmu->type->ops->put_constraint(box, event); | |
419 | } | |
420 | ||
254298c7 | 421 | static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n) |
087bfbb0 YZ |
422 | { |
423 | unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)]; | |
43b45780 | 424 | struct event_constraint *c; |
6a67943a | 425 | int i, wmin, wmax, ret = 0; |
087bfbb0 YZ |
426 | struct hw_perf_event *hwc; |
427 | ||
428 | bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX); | |
429 | ||
430 | for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) { | |
6a67943a | 431 | c = uncore_get_event_constraint(box, box->event_list[i]); |
b371b594 | 432 | box->event_constraint[i] = c; |
087bfbb0 YZ |
433 | wmin = min(wmin, c->weight); |
434 | wmax = max(wmax, c->weight); | |
435 | } | |
436 | ||
437 | /* fastpath, try to reuse previous register */ | |
438 | for (i = 0; i < n; i++) { | |
439 | hwc = &box->event_list[i]->hw; | |
b371b594 | 440 | c = box->event_constraint[i]; |
087bfbb0 YZ |
441 | |
442 | /* never assigned */ | |
443 | if (hwc->idx == -1) | |
444 | break; | |
445 | ||
446 | /* constraint still honored */ | |
447 | if (!test_bit(hwc->idx, c->idxmsk)) | |
448 | break; | |
449 | ||
450 | /* not already used */ | |
451 | if (test_bit(hwc->idx, used_mask)) | |
452 | break; | |
453 | ||
454 | __set_bit(hwc->idx, used_mask); | |
6a67943a YZ |
455 | if (assign) |
456 | assign[i] = hwc->idx; | |
087bfbb0 | 457 | } |
087bfbb0 | 458 | /* slow path */ |
6a67943a | 459 | if (i != n) |
b371b594 | 460 | ret = perf_assign_events(box->event_constraint, n, |
cc1790cf | 461 | wmin, wmax, n, assign); |
6a67943a YZ |
462 | |
463 | if (!assign || ret) { | |
464 | for (i = 0; i < n; i++) | |
465 | uncore_put_event_constraint(box, box->event_list[i]); | |
466 | } | |
087bfbb0 YZ |
467 | return ret ? -EINVAL : 0; |
468 | } | |
469 | ||
470 | static void uncore_pmu_event_start(struct perf_event *event, int flags) | |
471 | { | |
472 | struct intel_uncore_box *box = uncore_event_to_box(event); | |
473 | int idx = event->hw.idx; | |
474 | ||
475 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) | |
476 | return; | |
477 | ||
478 | if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX)) | |
479 | return; | |
480 | ||
481 | event->hw.state = 0; | |
482 | box->events[idx] = event; | |
483 | box->n_active++; | |
484 | __set_bit(idx, box->active_mask); | |
485 | ||
486 | local64_set(&event->hw.prev_count, uncore_read_counter(box, event)); | |
487 | uncore_enable_event(box, event); | |
488 | ||
489 | if (box->n_active == 1) { | |
490 | uncore_enable_box(box); | |
491 | uncore_pmu_start_hrtimer(box); | |
492 | } | |
493 | } | |
494 | ||
495 | static void uncore_pmu_event_stop(struct perf_event *event, int flags) | |
496 | { | |
497 | struct intel_uncore_box *box = uncore_event_to_box(event); | |
498 | struct hw_perf_event *hwc = &event->hw; | |
499 | ||
500 | if (__test_and_clear_bit(hwc->idx, box->active_mask)) { | |
501 | uncore_disable_event(box, event); | |
502 | box->n_active--; | |
503 | box->events[hwc->idx] = NULL; | |
504 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
505 | hwc->state |= PERF_HES_STOPPED; | |
506 | ||
507 | if (box->n_active == 0) { | |
508 | uncore_disable_box(box); | |
509 | uncore_pmu_cancel_hrtimer(box); | |
510 | } | |
511 | } | |
512 | ||
513 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | |
514 | /* | |
515 | * Drain the remaining delta count out of a event | |
516 | * that we are disabling: | |
517 | */ | |
518 | uncore_perf_event_update(box, event); | |
519 | hwc->state |= PERF_HES_UPTODATE; | |
520 | } | |
521 | } | |
522 | ||
523 | static int uncore_pmu_event_add(struct perf_event *event, int flags) | |
524 | { | |
525 | struct intel_uncore_box *box = uncore_event_to_box(event); | |
526 | struct hw_perf_event *hwc = &event->hw; | |
527 | int assign[UNCORE_PMC_IDX_MAX]; | |
528 | int i, n, ret; | |
529 | ||
530 | if (!box) | |
531 | return -ENODEV; | |
532 | ||
533 | ret = n = uncore_collect_events(box, event, false); | |
534 | if (ret < 0) | |
535 | return ret; | |
536 | ||
537 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
538 | if (!(flags & PERF_EF_START)) | |
539 | hwc->state |= PERF_HES_ARCH; | |
540 | ||
541 | ret = uncore_assign_events(box, assign, n); | |
542 | if (ret) | |
543 | return ret; | |
544 | ||
545 | /* save events moving to new counters */ | |
546 | for (i = 0; i < box->n_events; i++) { | |
547 | event = box->event_list[i]; | |
548 | hwc = &event->hw; | |
549 | ||
550 | if (hwc->idx == assign[i] && | |
551 | hwc->last_tag == box->tags[assign[i]]) | |
552 | continue; | |
553 | /* | |
554 | * Ensure we don't accidentally enable a stopped | |
555 | * counter simply because we rescheduled. | |
556 | */ | |
557 | if (hwc->state & PERF_HES_STOPPED) | |
558 | hwc->state |= PERF_HES_ARCH; | |
559 | ||
560 | uncore_pmu_event_stop(event, PERF_EF_UPDATE); | |
561 | } | |
562 | ||
563 | /* reprogram moved events into new counters */ | |
564 | for (i = 0; i < n; i++) { | |
565 | event = box->event_list[i]; | |
566 | hwc = &event->hw; | |
567 | ||
568 | if (hwc->idx != assign[i] || | |
569 | hwc->last_tag != box->tags[assign[i]]) | |
570 | uncore_assign_hw_event(box, event, assign[i]); | |
571 | else if (i < box->n_events) | |
572 | continue; | |
573 | ||
574 | if (hwc->state & PERF_HES_ARCH) | |
575 | continue; | |
576 | ||
577 | uncore_pmu_event_start(event, 0); | |
578 | } | |
579 | box->n_events = n; | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
584 | static void uncore_pmu_event_del(struct perf_event *event, int flags) | |
585 | { | |
586 | struct intel_uncore_box *box = uncore_event_to_box(event); | |
587 | int i; | |
588 | ||
589 | uncore_pmu_event_stop(event, PERF_EF_UPDATE); | |
590 | ||
591 | for (i = 0; i < box->n_events; i++) { | |
592 | if (event == box->event_list[i]) { | |
6a67943a YZ |
593 | uncore_put_event_constraint(box, event); |
594 | ||
087bfbb0 YZ |
595 | while (++i < box->n_events) |
596 | box->event_list[i - 1] = box->event_list[i]; | |
597 | ||
598 | --box->n_events; | |
599 | break; | |
600 | } | |
601 | } | |
602 | ||
603 | event->hw.idx = -1; | |
604 | event->hw.last_tag = ~0ULL; | |
605 | } | |
606 | ||
514b2346 | 607 | void uncore_pmu_event_read(struct perf_event *event) |
087bfbb0 YZ |
608 | { |
609 | struct intel_uncore_box *box = uncore_event_to_box(event); | |
610 | uncore_perf_event_update(box, event); | |
611 | } | |
612 | ||
613 | /* | |
614 | * validation ensures the group can be loaded onto the | |
615 | * PMU if it was the only group available. | |
616 | */ | |
617 | static int uncore_validate_group(struct intel_uncore_pmu *pmu, | |
618 | struct perf_event *event) | |
619 | { | |
620 | struct perf_event *leader = event->group_leader; | |
621 | struct intel_uncore_box *fake_box; | |
087bfbb0 YZ |
622 | int ret = -EINVAL, n; |
623 | ||
73c4427c | 624 | fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE); |
087bfbb0 YZ |
625 | if (!fake_box) |
626 | return -ENOMEM; | |
627 | ||
628 | fake_box->pmu = pmu; | |
629 | /* | |
630 | * the event is not yet connected with its | |
631 | * siblings therefore we must first collect | |
632 | * existing siblings, then add the new event | |
633 | * before we can simulate the scheduling | |
634 | */ | |
635 | n = uncore_collect_events(fake_box, leader, true); | |
636 | if (n < 0) | |
637 | goto out; | |
638 | ||
639 | fake_box->n_events = n; | |
640 | n = uncore_collect_events(fake_box, event, false); | |
641 | if (n < 0) | |
642 | goto out; | |
643 | ||
644 | fake_box->n_events = n; | |
645 | ||
6a67943a | 646 | ret = uncore_assign_events(fake_box, NULL, n); |
087bfbb0 YZ |
647 | out: |
648 | kfree(fake_box); | |
649 | return ret; | |
650 | } | |
651 | ||
46bdd905 | 652 | static int uncore_pmu_event_init(struct perf_event *event) |
087bfbb0 YZ |
653 | { |
654 | struct intel_uncore_pmu *pmu; | |
655 | struct intel_uncore_box *box; | |
656 | struct hw_perf_event *hwc = &event->hw; | |
657 | int ret; | |
658 | ||
659 | if (event->attr.type != event->pmu->type) | |
660 | return -ENOENT; | |
661 | ||
662 | pmu = uncore_event_to_pmu(event); | |
663 | /* no device found for this pmu */ | |
664 | if (pmu->func_id < 0) | |
665 | return -ENOENT; | |
666 | ||
667 | /* | |
668 | * Uncore PMU does measure at all privilege level all the time. | |
669 | * So it doesn't make sense to specify any exclude bits. | |
670 | */ | |
671 | if (event->attr.exclude_user || event->attr.exclude_kernel || | |
672 | event->attr.exclude_hv || event->attr.exclude_idle) | |
673 | return -EINVAL; | |
674 | ||
675 | /* Sampling not supported yet */ | |
676 | if (hwc->sample_period) | |
677 | return -EINVAL; | |
678 | ||
679 | /* | |
680 | * Place all uncore events for a particular physical package | |
681 | * onto a single cpu | |
682 | */ | |
683 | if (event->cpu < 0) | |
684 | return -EINVAL; | |
685 | box = uncore_pmu_to_box(pmu, event->cpu); | |
686 | if (!box || box->cpu < 0) | |
687 | return -EINVAL; | |
688 | event->cpu = box->cpu; | |
689 | ||
6a67943a YZ |
690 | event->hw.idx = -1; |
691 | event->hw.last_tag = ~0ULL; | |
692 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
ebb6cc03 | 693 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
6a67943a | 694 | |
087bfbb0 YZ |
695 | if (event->attr.config == UNCORE_FIXED_EVENT) { |
696 | /* no fixed counter */ | |
697 | if (!pmu->type->fixed_ctl) | |
698 | return -EINVAL; | |
699 | /* | |
700 | * if there is only one fixed counter, only the first pmu | |
701 | * can access the fixed counter | |
702 | */ | |
703 | if (pmu->type->single_fixed && pmu->pmu_idx > 0) | |
704 | return -EINVAL; | |
dbc33f70 SE |
705 | |
706 | /* fixed counters have event field hardcoded to zero */ | |
707 | hwc->config = 0ULL; | |
087bfbb0 YZ |
708 | } else { |
709 | hwc->config = event->attr.config & pmu->type->event_mask; | |
6a67943a YZ |
710 | if (pmu->type->ops->hw_config) { |
711 | ret = pmu->type->ops->hw_config(box, event); | |
712 | if (ret) | |
713 | return ret; | |
714 | } | |
087bfbb0 YZ |
715 | } |
716 | ||
087bfbb0 YZ |
717 | if (event->group_leader != event) |
718 | ret = uncore_validate_group(pmu, event); | |
719 | else | |
720 | ret = 0; | |
721 | ||
722 | return ret; | |
723 | } | |
724 | ||
314d9f63 YZ |
725 | static ssize_t uncore_get_attr_cpumask(struct device *dev, |
726 | struct device_attribute *attr, char *buf) | |
727 | { | |
5aaba363 | 728 | return cpumap_print_to_pagebuf(true, buf, &uncore_cpu_mask); |
314d9f63 YZ |
729 | } |
730 | ||
731 | static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL); | |
732 | ||
733 | static struct attribute *uncore_pmu_attrs[] = { | |
734 | &dev_attr_cpumask.attr, | |
735 | NULL, | |
736 | }; | |
737 | ||
738 | static struct attribute_group uncore_pmu_attr_group = { | |
739 | .attrs = uncore_pmu_attrs, | |
740 | }; | |
741 | ||
a08b6769 | 742 | static int uncore_pmu_register(struct intel_uncore_pmu *pmu) |
087bfbb0 YZ |
743 | { |
744 | int ret; | |
745 | ||
d64b25b6 SE |
746 | if (!pmu->type->pmu) { |
747 | pmu->pmu = (struct pmu) { | |
748 | .attr_groups = pmu->type->attr_groups, | |
749 | .task_ctx_nr = perf_invalid_context, | |
750 | .event_init = uncore_pmu_event_init, | |
751 | .add = uncore_pmu_event_add, | |
752 | .del = uncore_pmu_event_del, | |
753 | .start = uncore_pmu_event_start, | |
754 | .stop = uncore_pmu_event_stop, | |
755 | .read = uncore_pmu_event_read, | |
756 | }; | |
757 | } else { | |
758 | pmu->pmu = *pmu->type->pmu; | |
759 | pmu->pmu.attr_groups = pmu->type->attr_groups; | |
760 | } | |
087bfbb0 YZ |
761 | |
762 | if (pmu->type->num_boxes == 1) { | |
763 | if (strlen(pmu->type->name) > 0) | |
764 | sprintf(pmu->name, "uncore_%s", pmu->type->name); | |
765 | else | |
766 | sprintf(pmu->name, "uncore"); | |
767 | } else { | |
768 | sprintf(pmu->name, "uncore_%s_%d", pmu->type->name, | |
769 | pmu->pmu_idx); | |
770 | } | |
771 | ||
772 | ret = perf_pmu_register(&pmu->pmu, pmu->name, -1); | |
4f089678 TG |
773 | if (!ret) |
774 | pmu->registered = true; | |
087bfbb0 YZ |
775 | return ret; |
776 | } | |
777 | ||
4f089678 TG |
778 | static void uncore_pmu_unregister(struct intel_uncore_pmu *pmu) |
779 | { | |
780 | if (!pmu->registered) | |
781 | return; | |
782 | perf_pmu_unregister(&pmu->pmu); | |
783 | pmu->registered = false; | |
784 | } | |
785 | ||
087bfbb0 YZ |
786 | static void __init uncore_type_exit(struct intel_uncore_type *type) |
787 | { | |
788 | int i; | |
789 | ||
ffeda003 | 790 | if (type->pmus) { |
4f089678 TG |
791 | for (i = 0; i < type->num_boxes; i++) { |
792 | uncore_pmu_unregister(&type->pmus[i]); | |
ffeda003 | 793 | free_percpu(type->pmus[i].box); |
4f089678 | 794 | } |
ffeda003 TG |
795 | kfree(type->pmus); |
796 | type->pmus = NULL; | |
797 | } | |
314d9f63 YZ |
798 | kfree(type->events_group); |
799 | type->events_group = NULL; | |
087bfbb0 YZ |
800 | } |
801 | ||
cffa59ba | 802 | static void __init uncore_types_exit(struct intel_uncore_type **types) |
14371cce YZ |
803 | { |
804 | int i; | |
ffeda003 | 805 | |
14371cce YZ |
806 | for (i = 0; types[i]; i++) |
807 | uncore_type_exit(types[i]); | |
808 | } | |
809 | ||
087bfbb0 YZ |
810 | static int __init uncore_type_init(struct intel_uncore_type *type) |
811 | { | |
812 | struct intel_uncore_pmu *pmus; | |
1b0dac2a | 813 | struct attribute_group *attr_group; |
087bfbb0 YZ |
814 | struct attribute **attrs; |
815 | int i, j; | |
816 | ||
817 | pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL); | |
818 | if (!pmus) | |
819 | return -ENOMEM; | |
820 | ||
b7b4839d DJ |
821 | type->pmus = pmus; |
822 | ||
087bfbb0 YZ |
823 | type->unconstrainted = (struct event_constraint) |
824 | __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1, | |
9fac2cf3 | 825 | 0, type->num_counters, 0, 0); |
087bfbb0 YZ |
826 | |
827 | for (i = 0; i < type->num_boxes; i++) { | |
828 | pmus[i].func_id = -1; | |
829 | pmus[i].pmu_idx = i; | |
830 | pmus[i].type = type; | |
14371cce | 831 | INIT_LIST_HEAD(&pmus[i].box_list); |
087bfbb0 YZ |
832 | pmus[i].box = alloc_percpu(struct intel_uncore_box *); |
833 | if (!pmus[i].box) | |
ffeda003 | 834 | return -ENOMEM; |
087bfbb0 YZ |
835 | } |
836 | ||
837 | if (type->event_descs) { | |
838 | i = 0; | |
839 | while (type->event_descs[i].attr.attr.name) | |
840 | i++; | |
841 | ||
1b0dac2a JSM |
842 | attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) + |
843 | sizeof(*attr_group), GFP_KERNEL); | |
844 | if (!attr_group) | |
ffeda003 | 845 | return -ENOMEM; |
087bfbb0 | 846 | |
1b0dac2a JSM |
847 | attrs = (struct attribute **)(attr_group + 1); |
848 | attr_group->name = "events"; | |
849 | attr_group->attrs = attrs; | |
087bfbb0 YZ |
850 | |
851 | for (j = 0; j < i; j++) | |
852 | attrs[j] = &type->event_descs[j].attr.attr; | |
853 | ||
1b0dac2a | 854 | type->events_group = attr_group; |
087bfbb0 YZ |
855 | } |
856 | ||
314d9f63 | 857 | type->pmu_group = &uncore_pmu_attr_group; |
087bfbb0 | 858 | return 0; |
087bfbb0 YZ |
859 | } |
860 | ||
861 | static int __init uncore_types_init(struct intel_uncore_type **types) | |
862 | { | |
863 | int i, ret; | |
864 | ||
865 | for (i = 0; types[i]; i++) { | |
866 | ret = uncore_type_init(types[i]); | |
867 | if (ret) | |
ffeda003 | 868 | return ret; |
087bfbb0 YZ |
869 | } |
870 | return 0; | |
087bfbb0 YZ |
871 | } |
872 | ||
14371cce YZ |
873 | /* |
874 | * add a pci uncore device | |
875 | */ | |
899396cf | 876 | static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
14371cce YZ |
877 | { |
878 | struct intel_uncore_pmu *pmu; | |
879 | struct intel_uncore_box *box; | |
899396cf | 880 | struct intel_uncore_type *type; |
513d793e | 881 | bool first_box = false; |
4f089678 | 882 | int phys_id, ret; |
14371cce | 883 | |
712df65c | 884 | phys_id = uncore_pcibus_to_physid(pdev->bus); |
83f8ebd2 | 885 | if (phys_id < 0 || phys_id >= UNCORE_SOCKET_MAX) |
14371cce YZ |
886 | return -ENODEV; |
887 | ||
899396cf | 888 | if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) { |
514b2346 YZ |
889 | int idx = UNCORE_PCI_DEV_IDX(id->driver_data); |
890 | uncore_extra_pci_dev[phys_id][idx] = pdev; | |
899396cf YZ |
891 | pci_set_drvdata(pdev, NULL); |
892 | return 0; | |
893 | } | |
894 | ||
514b2346 | 895 | type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)]; |
73c4427c | 896 | box = uncore_alloc_box(type, NUMA_NO_NODE); |
14371cce YZ |
897 | if (!box) |
898 | return -ENOMEM; | |
899 | ||
900 | /* | |
901 | * for performance monitoring unit with multiple boxes, | |
902 | * each box has a different function id. | |
903 | */ | |
899396cf | 904 | pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)]; |
77af0037 HC |
905 | /* Knights Landing uses a common PCI device ID for multiple instances of |
906 | * an uncore PMU device type. There is only one entry per device type in | |
907 | * the knl_uncore_pci_ids table inspite of multiple devices present for | |
908 | * some device types. Hence PCI device idx would be 0 for all devices. | |
909 | * So increment pmu pointer to point to an unused array element. | |
910 | */ | |
911 | if (boot_cpu_data.x86_model == 87) | |
912 | while (pmu->func_id >= 0) | |
913 | pmu++; | |
899396cf YZ |
914 | if (pmu->func_id < 0) |
915 | pmu->func_id = pdev->devfn; | |
916 | else | |
917 | WARN_ON_ONCE(pmu->func_id != pdev->devfn); | |
14371cce YZ |
918 | |
919 | box->phys_id = phys_id; | |
920 | box->pci_dev = pdev; | |
921 | box->pmu = pmu; | |
15c12479 | 922 | uncore_box_init(box); |
14371cce YZ |
923 | pci_set_drvdata(pdev, box); |
924 | ||
925 | raw_spin_lock(&uncore_box_lock); | |
513d793e YZ |
926 | if (list_empty(&pmu->box_list)) |
927 | first_box = true; | |
14371cce YZ |
928 | list_add_tail(&box->list, &pmu->box_list); |
929 | raw_spin_unlock(&uncore_box_lock); | |
930 | ||
4f089678 TG |
931 | if (!first_box) |
932 | return 0; | |
933 | ||
934 | ret = uncore_pmu_register(pmu); | |
935 | if (ret) { | |
936 | pci_set_drvdata(pdev, NULL); | |
937 | raw_spin_lock(&uncore_box_lock); | |
938 | list_del(&box->list); | |
939 | raw_spin_unlock(&uncore_box_lock); | |
a46195f1 | 940 | uncore_box_exit(box); |
4f089678 TG |
941 | kfree(box); |
942 | } | |
943 | return ret; | |
14371cce YZ |
944 | } |
945 | ||
357398e9 | 946 | static void uncore_pci_remove(struct pci_dev *pdev) |
14371cce YZ |
947 | { |
948 | struct intel_uncore_box *box = pci_get_drvdata(pdev); | |
899396cf | 949 | struct intel_uncore_pmu *pmu; |
712df65c | 950 | int i, cpu, phys_id; |
513d793e | 951 | bool last_box = false; |
899396cf | 952 | |
712df65c | 953 | phys_id = uncore_pcibus_to_physid(pdev->bus); |
899396cf YZ |
954 | box = pci_get_drvdata(pdev); |
955 | if (!box) { | |
956 | for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) { | |
514b2346 YZ |
957 | if (uncore_extra_pci_dev[phys_id][i] == pdev) { |
958 | uncore_extra_pci_dev[phys_id][i] = NULL; | |
899396cf YZ |
959 | break; |
960 | } | |
961 | } | |
962 | WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX); | |
963 | return; | |
964 | } | |
14371cce | 965 | |
899396cf | 966 | pmu = box->pmu; |
14371cce YZ |
967 | if (WARN_ON_ONCE(phys_id != box->phys_id)) |
968 | return; | |
969 | ||
e850f9c3 YZ |
970 | pci_set_drvdata(pdev, NULL); |
971 | ||
14371cce YZ |
972 | raw_spin_lock(&uncore_box_lock); |
973 | list_del(&box->list); | |
513d793e YZ |
974 | if (list_empty(&pmu->box_list)) |
975 | last_box = true; | |
14371cce YZ |
976 | raw_spin_unlock(&uncore_box_lock); |
977 | ||
978 | for_each_possible_cpu(cpu) { | |
979 | if (*per_cpu_ptr(pmu->box, cpu) == box) { | |
980 | *per_cpu_ptr(pmu->box, cpu) = NULL; | |
981 | atomic_dec(&box->refcnt); | |
982 | } | |
983 | } | |
984 | ||
985 | WARN_ON_ONCE(atomic_read(&box->refcnt) != 1); | |
a46195f1 | 986 | uncore_box_exit(box); |
14371cce | 987 | kfree(box); |
513d793e YZ |
988 | |
989 | if (last_box) | |
4f089678 | 990 | uncore_pmu_unregister(pmu); |
14371cce YZ |
991 | } |
992 | ||
14371cce YZ |
993 | static int __init uncore_pci_init(void) |
994 | { | |
995 | int ret; | |
996 | ||
997 | switch (boot_cpu_data.x86_model) { | |
7c94ee2e | 998 | case 45: /* Sandy Bridge-EP */ |
8268fdfc | 999 | ret = snbep_uncore_pci_init(); |
7c94ee2e | 1000 | break; |
ddcd0973 PZ |
1001 | case 62: /* Ivy Bridge-EP */ |
1002 | ret = ivbep_uncore_pci_init(); | |
e850f9c3 | 1003 | break; |
e735b9db YZ |
1004 | case 63: /* Haswell-EP */ |
1005 | ret = hswep_uncore_pci_init(); | |
1006 | break; | |
d6980ef3 | 1007 | case 79: /* BDX-EP */ |
070e9887 KL |
1008 | case 86: /* BDX-DE */ |
1009 | ret = bdx_uncore_pci_init(); | |
1010 | break; | |
b9e1ab6d | 1011 | case 42: /* Sandy Bridge */ |
92807ffd | 1012 | ret = snb_uncore_pci_init(); |
b9e1ab6d SE |
1013 | break; |
1014 | case 58: /* Ivy Bridge */ | |
92807ffd | 1015 | ret = ivb_uncore_pci_init(); |
b9e1ab6d SE |
1016 | break; |
1017 | case 60: /* Haswell */ | |
1018 | case 69: /* Haswell Celeron */ | |
92807ffd | 1019 | ret = hsw_uncore_pci_init(); |
b9e1ab6d | 1020 | break; |
a41f3c8c SE |
1021 | case 61: /* Broadwell */ |
1022 | ret = bdw_uncore_pci_init(); | |
1023 | break; | |
77af0037 HC |
1024 | case 87: /* Knights Landing */ |
1025 | ret = knl_uncore_pci_init(); | |
1026 | break; | |
0e1eb0a1 SE |
1027 | case 94: /* SkyLake */ |
1028 | ret = skl_uncore_pci_init(); | |
1029 | break; | |
14371cce YZ |
1030 | default: |
1031 | return 0; | |
1032 | } | |
1033 | ||
92807ffd YZ |
1034 | if (ret) |
1035 | return ret; | |
1036 | ||
514b2346 | 1037 | ret = uncore_types_init(uncore_pci_uncores); |
14371cce | 1038 | if (ret) |
ffeda003 | 1039 | goto err; |
14371cce YZ |
1040 | |
1041 | uncore_pci_driver->probe = uncore_pci_probe; | |
1042 | uncore_pci_driver->remove = uncore_pci_remove; | |
1043 | ||
1044 | ret = pci_register_driver(uncore_pci_driver); | |
ffeda003 TG |
1045 | if (ret) |
1046 | goto err; | |
1047 | ||
1048 | pcidrv_registered = true; | |
1049 | return 0; | |
14371cce | 1050 | |
ffeda003 TG |
1051 | err: |
1052 | uncore_types_exit(uncore_pci_uncores); | |
1053 | uncore_pci_uncores = empty_uncore; | |
4f089678 | 1054 | uncore_free_pcibus_map(); |
14371cce YZ |
1055 | return ret; |
1056 | } | |
1057 | ||
1058 | static void __init uncore_pci_exit(void) | |
1059 | { | |
1060 | if (pcidrv_registered) { | |
1061 | pcidrv_registered = false; | |
1062 | pci_unregister_driver(uncore_pci_driver); | |
514b2346 | 1063 | uncore_types_exit(uncore_pci_uncores); |
4f089678 | 1064 | uncore_free_pcibus_map(); |
14371cce YZ |
1065 | } |
1066 | } | |
1067 | ||
22cc4ccf YZ |
1068 | /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */ |
1069 | static LIST_HEAD(boxes_to_free); | |
1070 | ||
148f9bb8 | 1071 | static void uncore_kfree_boxes(void) |
22cc4ccf YZ |
1072 | { |
1073 | struct intel_uncore_box *box; | |
1074 | ||
1075 | while (!list_empty(&boxes_to_free)) { | |
1076 | box = list_entry(boxes_to_free.next, | |
1077 | struct intel_uncore_box, list); | |
1078 | list_del(&box->list); | |
1079 | kfree(box); | |
1080 | } | |
1081 | } | |
1082 | ||
148f9bb8 | 1083 | static void uncore_cpu_dying(int cpu) |
087bfbb0 YZ |
1084 | { |
1085 | struct intel_uncore_type *type; | |
1086 | struct intel_uncore_pmu *pmu; | |
1087 | struct intel_uncore_box *box; | |
1088 | int i, j; | |
1089 | ||
514b2346 YZ |
1090 | for (i = 0; uncore_msr_uncores[i]; i++) { |
1091 | type = uncore_msr_uncores[i]; | |
087bfbb0 YZ |
1092 | for (j = 0; j < type->num_boxes; j++) { |
1093 | pmu = &type->pmus[j]; | |
1094 | box = *per_cpu_ptr(pmu->box, cpu); | |
1095 | *per_cpu_ptr(pmu->box, cpu) = NULL; | |
a46195f1 | 1096 | if (box && atomic_dec_and_test(&box->refcnt)) { |
22cc4ccf | 1097 | list_add(&box->list, &boxes_to_free); |
a46195f1 TG |
1098 | uncore_box_exit(box); |
1099 | } | |
087bfbb0 YZ |
1100 | } |
1101 | } | |
1102 | } | |
1103 | ||
148f9bb8 | 1104 | static int uncore_cpu_starting(int cpu) |
087bfbb0 YZ |
1105 | { |
1106 | struct intel_uncore_type *type; | |
1107 | struct intel_uncore_pmu *pmu; | |
1108 | struct intel_uncore_box *box, *exist; | |
1109 | int i, j, k, phys_id; | |
1110 | ||
1111 | phys_id = topology_physical_package_id(cpu); | |
1112 | ||
514b2346 YZ |
1113 | for (i = 0; uncore_msr_uncores[i]; i++) { |
1114 | type = uncore_msr_uncores[i]; | |
087bfbb0 YZ |
1115 | for (j = 0; j < type->num_boxes; j++) { |
1116 | pmu = &type->pmus[j]; | |
1117 | box = *per_cpu_ptr(pmu->box, cpu); | |
1118 | /* called by uncore_cpu_init? */ | |
15c12479 IM |
1119 | if (box && box->phys_id >= 0) { |
1120 | uncore_box_init(box); | |
087bfbb0 | 1121 | continue; |
15c12479 | 1122 | } |
087bfbb0 YZ |
1123 | |
1124 | for_each_online_cpu(k) { | |
1125 | exist = *per_cpu_ptr(pmu->box, k); | |
1126 | if (exist && exist->phys_id == phys_id) { | |
1127 | atomic_inc(&exist->refcnt); | |
1128 | *per_cpu_ptr(pmu->box, cpu) = exist; | |
22cc4ccf YZ |
1129 | if (box) { |
1130 | list_add(&box->list, | |
1131 | &boxes_to_free); | |
1132 | box = NULL; | |
1133 | } | |
087bfbb0 YZ |
1134 | break; |
1135 | } | |
1136 | } | |
1137 | ||
15c12479 | 1138 | if (box) { |
087bfbb0 | 1139 | box->phys_id = phys_id; |
15c12479 IM |
1140 | uncore_box_init(box); |
1141 | } | |
087bfbb0 YZ |
1142 | } |
1143 | } | |
1144 | return 0; | |
1145 | } | |
1146 | ||
148f9bb8 | 1147 | static int uncore_cpu_prepare(int cpu, int phys_id) |
087bfbb0 YZ |
1148 | { |
1149 | struct intel_uncore_type *type; | |
1150 | struct intel_uncore_pmu *pmu; | |
1151 | struct intel_uncore_box *box; | |
1152 | int i, j; | |
1153 | ||
514b2346 YZ |
1154 | for (i = 0; uncore_msr_uncores[i]; i++) { |
1155 | type = uncore_msr_uncores[i]; | |
087bfbb0 YZ |
1156 | for (j = 0; j < type->num_boxes; j++) { |
1157 | pmu = &type->pmus[j]; | |
1158 | if (pmu->func_id < 0) | |
1159 | pmu->func_id = j; | |
1160 | ||
73c4427c | 1161 | box = uncore_alloc_box(type, cpu_to_node(cpu)); |
087bfbb0 YZ |
1162 | if (!box) |
1163 | return -ENOMEM; | |
1164 | ||
1165 | box->pmu = pmu; | |
1166 | box->phys_id = phys_id; | |
1167 | *per_cpu_ptr(pmu->box, cpu) = box; | |
1168 | } | |
1169 | } | |
1170 | return 0; | |
1171 | } | |
1172 | ||
148f9bb8 | 1173 | static void |
254298c7 | 1174 | uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu) |
087bfbb0 YZ |
1175 | { |
1176 | struct intel_uncore_type *type; | |
1177 | struct intel_uncore_pmu *pmu; | |
1178 | struct intel_uncore_box *box; | |
1179 | int i, j; | |
1180 | ||
1181 | for (i = 0; uncores[i]; i++) { | |
1182 | type = uncores[i]; | |
1183 | for (j = 0; j < type->num_boxes; j++) { | |
1184 | pmu = &type->pmus[j]; | |
1185 | if (old_cpu < 0) | |
1186 | box = uncore_pmu_to_box(pmu, new_cpu); | |
1187 | else | |
1188 | box = uncore_pmu_to_box(pmu, old_cpu); | |
1189 | if (!box) | |
1190 | continue; | |
1191 | ||
1192 | if (old_cpu < 0) { | |
1193 | WARN_ON_ONCE(box->cpu != -1); | |
1194 | box->cpu = new_cpu; | |
1195 | continue; | |
1196 | } | |
1197 | ||
1198 | WARN_ON_ONCE(box->cpu != old_cpu); | |
1199 | if (new_cpu >= 0) { | |
1200 | uncore_pmu_cancel_hrtimer(box); | |
1201 | perf_pmu_migrate_context(&pmu->pmu, | |
1202 | old_cpu, new_cpu); | |
1203 | box->cpu = new_cpu; | |
1204 | } else { | |
1205 | box->cpu = -1; | |
1206 | } | |
1207 | } | |
1208 | } | |
1209 | } | |
1210 | ||
148f9bb8 | 1211 | static void uncore_event_exit_cpu(int cpu) |
087bfbb0 YZ |
1212 | { |
1213 | int i, phys_id, target; | |
1214 | ||
1215 | /* if exiting cpu is used for collecting uncore events */ | |
1216 | if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask)) | |
1217 | return; | |
1218 | ||
1219 | /* find a new cpu to collect uncore events */ | |
1220 | phys_id = topology_physical_package_id(cpu); | |
1221 | target = -1; | |
1222 | for_each_online_cpu(i) { | |
1223 | if (i == cpu) | |
1224 | continue; | |
1225 | if (phys_id == topology_physical_package_id(i)) { | |
1226 | target = i; | |
1227 | break; | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | /* migrate uncore events to the new cpu */ | |
1232 | if (target >= 0) | |
1233 | cpumask_set_cpu(target, &uncore_cpu_mask); | |
1234 | ||
514b2346 YZ |
1235 | uncore_change_context(uncore_msr_uncores, cpu, target); |
1236 | uncore_change_context(uncore_pci_uncores, cpu, target); | |
087bfbb0 YZ |
1237 | } |
1238 | ||
148f9bb8 | 1239 | static void uncore_event_init_cpu(int cpu) |
087bfbb0 YZ |
1240 | { |
1241 | int i, phys_id; | |
1242 | ||
1243 | phys_id = topology_physical_package_id(cpu); | |
1244 | for_each_cpu(i, &uncore_cpu_mask) { | |
1245 | if (phys_id == topology_physical_package_id(i)) | |
1246 | return; | |
1247 | } | |
1248 | ||
1249 | cpumask_set_cpu(cpu, &uncore_cpu_mask); | |
1250 | ||
514b2346 YZ |
1251 | uncore_change_context(uncore_msr_uncores, -1, cpu); |
1252 | uncore_change_context(uncore_pci_uncores, -1, cpu); | |
087bfbb0 YZ |
1253 | } |
1254 | ||
148f9bb8 PG |
1255 | static int uncore_cpu_notifier(struct notifier_block *self, |
1256 | unsigned long action, void *hcpu) | |
087bfbb0 YZ |
1257 | { |
1258 | unsigned int cpu = (long)hcpu; | |
1259 | ||
1260 | /* allocate/free data structure for uncore box */ | |
1261 | switch (action & ~CPU_TASKS_FROZEN) { | |
1262 | case CPU_UP_PREPARE: | |
4f089678 | 1263 | return notifier_from_errno(uncore_cpu_prepare(cpu, -1)); |
087bfbb0 YZ |
1264 | case CPU_STARTING: |
1265 | uncore_cpu_starting(cpu); | |
1266 | break; | |
1267 | case CPU_UP_CANCELED: | |
1268 | case CPU_DYING: | |
1269 | uncore_cpu_dying(cpu); | |
1270 | break; | |
22cc4ccf YZ |
1271 | case CPU_ONLINE: |
1272 | case CPU_DEAD: | |
1273 | uncore_kfree_boxes(); | |
1274 | break; | |
087bfbb0 YZ |
1275 | default: |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | /* select the cpu that collects uncore events */ | |
1280 | switch (action & ~CPU_TASKS_FROZEN) { | |
1281 | case CPU_DOWN_FAILED: | |
1282 | case CPU_STARTING: | |
1283 | uncore_event_init_cpu(cpu); | |
1284 | break; | |
1285 | case CPU_DOWN_PREPARE: | |
1286 | uncore_event_exit_cpu(cpu); | |
1287 | break; | |
1288 | default: | |
1289 | break; | |
1290 | } | |
1291 | ||
1292 | return NOTIFY_OK; | |
1293 | } | |
1294 | ||
148f9bb8 | 1295 | static struct notifier_block uncore_cpu_nb = { |
254298c7 | 1296 | .notifier_call = uncore_cpu_notifier, |
087bfbb0 YZ |
1297 | /* |
1298 | * to migrate uncore events, our notifier should be executed | |
1299 | * before perf core's notifier. | |
1300 | */ | |
254298c7 | 1301 | .priority = CPU_PRI_PERF + 1, |
087bfbb0 YZ |
1302 | }; |
1303 | ||
4f089678 | 1304 | static int __init type_pmu_register(struct intel_uncore_type *type) |
087bfbb0 | 1305 | { |
4f089678 TG |
1306 | int i, ret; |
1307 | ||
1308 | for (i = 0; i < type->num_boxes; i++) { | |
1309 | ret = uncore_pmu_register(&type->pmus[i]); | |
1310 | if (ret) | |
1311 | return ret; | |
1312 | } | |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | static int __init uncore_msr_pmus_register(void) | |
1317 | { | |
1318 | struct intel_uncore_type **types = uncore_msr_uncores; | |
1319 | int ret; | |
1320 | ||
1321 | while (*types) { | |
1322 | ret = type_pmu_register(*types++); | |
1323 | if (ret) | |
1324 | return ret; | |
1325 | } | |
1326 | return 0; | |
087bfbb0 YZ |
1327 | } |
1328 | ||
1329 | static int __init uncore_cpu_init(void) | |
1330 | { | |
c1e46580 | 1331 | int ret; |
087bfbb0 YZ |
1332 | |
1333 | switch (boot_cpu_data.x86_model) { | |
fcde10e9 YZ |
1334 | case 26: /* Nehalem */ |
1335 | case 30: | |
1336 | case 37: /* Westmere */ | |
1337 | case 44: | |
92807ffd | 1338 | nhm_uncore_cpu_init(); |
fcde10e9 YZ |
1339 | break; |
1340 | case 42: /* Sandy Bridge */ | |
9a6bc143 | 1341 | case 58: /* Ivy Bridge */ |
3a999587 AK |
1342 | case 60: /* Haswell */ |
1343 | case 69: /* Haswell */ | |
1344 | case 70: /* Haswell */ | |
1345 | case 61: /* Broadwell */ | |
1346 | case 71: /* Broadwell */ | |
92807ffd | 1347 | snb_uncore_cpu_init(); |
fcde10e9 | 1348 | break; |
80e217e9 | 1349 | case 45: /* Sandy Bridge-EP */ |
8268fdfc | 1350 | snbep_uncore_cpu_init(); |
7c94ee2e | 1351 | break; |
cb37af77 | 1352 | case 46: /* Nehalem-EX */ |
cb37af77 | 1353 | case 47: /* Westmere-EX aka. Xeon E7 */ |
c1e46580 | 1354 | nhmex_uncore_cpu_init(); |
254298c7 | 1355 | break; |
ddcd0973 PZ |
1356 | case 62: /* Ivy Bridge-EP */ |
1357 | ivbep_uncore_cpu_init(); | |
e850f9c3 | 1358 | break; |
e735b9db YZ |
1359 | case 63: /* Haswell-EP */ |
1360 | hswep_uncore_cpu_init(); | |
1361 | break; | |
d6980ef3 | 1362 | case 79: /* BDX-EP */ |
070e9887 KL |
1363 | case 86: /* BDX-DE */ |
1364 | bdx_uncore_cpu_init(); | |
1365 | break; | |
77af0037 HC |
1366 | case 87: /* Knights Landing */ |
1367 | knl_uncore_cpu_init(); | |
1368 | break; | |
087bfbb0 YZ |
1369 | default: |
1370 | return 0; | |
1371 | } | |
1372 | ||
514b2346 | 1373 | ret = uncore_types_init(uncore_msr_uncores); |
4f089678 TG |
1374 | if (ret) |
1375 | goto err; | |
1376 | ||
1377 | ret = uncore_msr_pmus_register(); | |
087bfbb0 | 1378 | if (ret) |
ffeda003 | 1379 | goto err; |
087bfbb0 | 1380 | return 0; |
ffeda003 TG |
1381 | err: |
1382 | uncore_types_exit(uncore_msr_uncores); | |
1383 | uncore_msr_uncores = empty_uncore; | |
1384 | return ret; | |
087bfbb0 YZ |
1385 | } |
1386 | ||
4f089678 | 1387 | static void __init uncore_cpu_setup(void *dummy) |
087bfbb0 | 1388 | { |
4f089678 | 1389 | uncore_cpu_starting(smp_processor_id()); |
087bfbb0 YZ |
1390 | } |
1391 | ||
4f089678 | 1392 | static int __init uncore_cpumask_init(void) |
411cf180 | 1393 | { |
4f089678 | 1394 | int cpu, ret = 0; |
411cf180 | 1395 | |
467a9e16 | 1396 | cpu_notifier_register_begin(); |
411cf180 SE |
1397 | |
1398 | for_each_online_cpu(cpu) { | |
1399 | int i, phys_id = topology_physical_package_id(cpu); | |
1400 | ||
1401 | for_each_cpu(i, &uncore_cpu_mask) { | |
1402 | if (phys_id == topology_physical_package_id(i)) { | |
1403 | phys_id = -1; | |
1404 | break; | |
1405 | } | |
1406 | } | |
1407 | if (phys_id < 0) | |
1408 | continue; | |
1409 | ||
4f089678 TG |
1410 | ret = uncore_cpu_prepare(cpu, phys_id); |
1411 | if (ret) | |
1412 | goto out; | |
411cf180 SE |
1413 | uncore_event_init_cpu(cpu); |
1414 | } | |
1415 | on_each_cpu(uncore_cpu_setup, NULL, 1); | |
1416 | ||
467a9e16 | 1417 | __register_cpu_notifier(&uncore_cpu_nb); |
411cf180 | 1418 | |
4f089678 | 1419 | out: |
467a9e16 | 1420 | cpu_notifier_register_done(); |
4f089678 | 1421 | return ret; |
411cf180 SE |
1422 | } |
1423 | ||
087bfbb0 YZ |
1424 | static int __init intel_uncore_init(void) |
1425 | { | |
1426 | int ret; | |
1427 | ||
1428 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
1429 | return -ENODEV; | |
1430 | ||
a05123bd YZ |
1431 | if (cpu_has_hypervisor) |
1432 | return -ENODEV; | |
1433 | ||
14371cce | 1434 | ret = uncore_pci_init(); |
087bfbb0 | 1435 | if (ret) |
4f089678 | 1436 | return ret; |
14371cce | 1437 | ret = uncore_cpu_init(); |
4f089678 TG |
1438 | if (ret) |
1439 | goto errpci; | |
1440 | ret = uncore_cpumask_init(); | |
1441 | if (ret) | |
1442 | goto errcpu; | |
087bfbb0 | 1443 | |
087bfbb0 | 1444 | return 0; |
4f089678 TG |
1445 | |
1446 | errcpu: | |
1447 | uncore_types_exit(uncore_msr_uncores); | |
1448 | errpci: | |
1449 | uncore_pci_exit(); | |
087bfbb0 YZ |
1450 | return ret; |
1451 | } | |
1452 | device_initcall(intel_uncore_init); |