[mirror_ubuntu-bionic-kernel.git] / arch / x86 / events / intel / uncore.h

#include <linux/slab.h>
#include <linux/pci.h>
#include <asm/apicdef.h>

#include <linux/perf_event.h>
#include "../perf_event.h"

#define UNCORE_PMU_NAME_LEN		32
#define UNCORE_PMU_HRTIMER_INTERVAL	(60LL * NSEC_PER_SEC)
#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)

#define UNCORE_FIXED_EVENT		0xff
#define UNCORE_PMC_IDX_MAX_GENERIC	8
#define UNCORE_PMC_IDX_FIXED		UNCORE_PMC_IDX_MAX_GENERIC
#define UNCORE_PMC_IDX_MAX		(UNCORE_PMC_IDX_FIXED + 1)

#define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx)	\
		((dev << 24) | (func << 16) | (type << 8) | idx)
#define UNCORE_PCI_DEV_DATA(type, idx)	((type << 8) | idx)
#define UNCORE_PCI_DEV_DEV(data)	((data >> 24) & 0xff)
#define UNCORE_PCI_DEV_FUNC(data)	((data >> 16) & 0xff)
#define UNCORE_PCI_DEV_TYPE(data)	((data >> 8) & 0xff)
#define UNCORE_PCI_DEV_IDX(data)	(data & 0xff)
#define UNCORE_EXTRA_PCI_DEV		0xff
#define UNCORE_EXTRA_PCI_DEV_MAX	3

#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)

struct pci_extra_dev {
	struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
};

struct intel_uncore_ops;
struct intel_uncore_pmu;
struct intel_uncore_box;
struct uncore_event_desc;

struct intel_uncore_type {
	const char *name;
	int num_counters;
	int num_boxes;
	int perf_ctr_bits;
	int fixed_ctr_bits;
	unsigned perf_ctr;
	unsigned event_ctl;
	unsigned event_mask;
	unsigned event_mask_ext;
	unsigned fixed_ctr;
	unsigned fixed_ctl;
	unsigned box_ctl;
	unsigned msr_offset;
	unsigned num_shared_regs:8;
	unsigned single_fixed:1;
	unsigned pair_ctr_ctl:1;
	unsigned *msr_offsets;
	struct event_constraint unconstrainted;
	struct event_constraint *constraints;
	struct intel_uncore_pmu *pmus;
	struct intel_uncore_ops *ops;
	struct uncore_event_desc *event_descs;
	const struct attribute_group *attr_groups[4];
	struct pmu *pmu; /* for custom pmu ops */
};

#define pmu_group attr_groups[0]
#define format_group attr_groups[1]
#define events_group attr_groups[2]

struct intel_uncore_ops {
	void (*init_box)(struct intel_uncore_box *);
	void (*exit_box)(struct intel_uncore_box *);
	void (*disable_box)(struct intel_uncore_box *);
	void (*enable_box)(struct intel_uncore_box *);
	void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
	void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
	u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
	int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
	struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
						   struct perf_event *);
	void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
};

struct intel_uncore_pmu {
	struct pmu			pmu;
	char				name[UNCORE_PMU_NAME_LEN];
	int				pmu_idx;
	int				func_id;
	bool				registered;
	atomic_t			activeboxes;
	struct intel_uncore_type	*type;
	struct intel_uncore_box		**boxes;
};

struct intel_uncore_extra_reg {
	raw_spinlock_t lock;
	u64 config, config1, config2;
	atomic_t ref;
};

struct intel_uncore_box {
	int pci_phys_id;
	int pkgid;
	int n_active;	/* number of active events */
	int n_events;
	int cpu;	/* cpu to collect events */
	unsigned long flags;
	atomic_t refcnt;
	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
	u64 tags[UNCORE_PMC_IDX_MAX];
	struct pci_dev *pci_dev;
	struct intel_uncore_pmu *pmu;
	u64 hrtimer_duration; /* hrtimer timeout for this box */
	struct hrtimer hrtimer;
	struct list_head list;
	struct list_head active_list;
	void *io_addr;
	struct intel_uncore_extra_reg shared_regs[0];
};

#define UNCORE_BOX_FLAG_INITIATED	0
#define UNCORE_BOX_FLAG_CTL_OFFS8	1 /* event config registers are 8-byte apart */

struct uncore_event_desc {
	struct kobj_attribute attr;
	const char *config;
};

struct pci2phy_map {
	struct list_head list;
	int segment;
	int pbus_to_physid[256];
};

struct pci2phy_map *__find_pci2phy_map(int segment);

ssize_t uncore_event_show(struct kobject *kobj,
			  struct kobj_attribute *attr, char *buf);

#define INTEL_UNCORE_EVENT_DESC(_name, _config)			\
{								\
	.attr	= __ATTR(_name, 0444, uncore_event_show, NULL),	\
	.config	= _config,					\
}

#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)			\
static ssize_t __uncore_##_var##_show(struct kobject *kobj,		\
				struct kobj_attribute *attr,		\
				char *page)				\
{									\
	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);			\
	return sprintf(page, _format "\n");				\
}									\
static struct kobj_attribute format_attr_##_var =			\
	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)

static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->box_ctl;
}

static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctl;
}

static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr;
}

static inline
unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
{
	if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
		return idx * 8 + box->pmu->type->event_ctl;

	return idx * 4 + box->pmu->type->event_ctl;
}

static inline
unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return idx * 8 + box->pmu->type->perf_ctr;
}

static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
{
	struct intel_uncore_pmu *pmu = box->pmu;
	return pmu->type->msr_offsets ?
		pmu->type->msr_offsets[pmu->pmu_idx] :
		pmu->type->msr_offset * pmu->pmu_idx;
}

static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->box_ctl)
		return 0;
	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->fixed_ctl)
		return 0;
	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->event_ctl +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->perf_ctr +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctl(box);
	else
		return uncore_msr_fixed_ctl(box);
}

static inline
unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctr(box);
	else
		return uncore_msr_fixed_ctr(box);
}

static inline
unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_event_ctl(box, idx);
	else
		return uncore_msr_event_ctl(box, idx);
}

static inline
unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_perf_ctr(box, idx);
	else
		return uncore_msr_perf_ctr(box, idx);
}

static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->perf_ctr_bits;
}

static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr_bits;
}

static inline int uncore_num_counters(struct intel_uncore_box *box)
{
	return box->pmu->type->num_counters;
}

static inline void uncore_disable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->disable_box)
		box->pmu->type->ops->disable_box(box);
}

static inline void uncore_enable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->enable_box)
		box->pmu->type->ops->enable_box(box);
}

static inline void uncore_disable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->disable_event(box, event);
}

static inline void uncore_enable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->enable_event(box, event);
}

static inline u64 uncore_read_counter(struct intel_uncore_box *box,
				struct perf_event *event)
{
	return box->pmu->type->ops->read_counter(box, event);
}

static inline void uncore_box_init(struct intel_uncore_box *box)
{
	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->init_box)
			box->pmu->type->ops->init_box(box);
	}
}

static inline void uncore_box_exit(struct intel_uncore_box *box)
{
	if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->exit_box)
			box->pmu->type->ops->exit_box(box);
	}
}

static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
{
	return (box->pkgid < 0);
}

static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
{
	return container_of(event->pmu, struct intel_uncore_pmu, pmu);
}

static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
{
	return event->pmu_private;
}

struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_event_read(struct perf_event *event);
void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
struct event_constraint *
uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);

extern struct intel_uncore_type **uncore_msr_uncores;
extern struct intel_uncore_type **uncore_pci_uncores;
extern struct pci_driver *uncore_pci_driver;
extern raw_spinlock_t pci2phy_map_lock;
extern struct list_head pci2phy_map_head;
extern struct pci_extra_dev *uncore_extra_pci_dev;
extern struct event_constraint uncore_constraint_empty;

/* uncore_snb.c */
int snb_uncore_pci_init(void);
int ivb_uncore_pci_init(void);
int hsw_uncore_pci_init(void);
int bdw_uncore_pci_init(void);
int skl_uncore_pci_init(void);
void snb_uncore_cpu_init(void);
void nhm_uncore_cpu_init(void);
void skl_uncore_cpu_init(void);
int snb_pci2phy_map_init(int devid);

/* uncore_snbep.c */
int snbep_uncore_pci_init(void);
void snbep_uncore_cpu_init(void);
int ivbep_uncore_pci_init(void);
void ivbep_uncore_cpu_init(void);
int hswep_uncore_pci_init(void);
void hswep_uncore_cpu_init(void);
int bdx_uncore_pci_init(void);
void bdx_uncore_cpu_init(void);
int knl_uncore_pci_init(void);
void knl_uncore_cpu_init(void);
int skx_uncore_pci_init(void);
void skx_uncore_cpu_init(void);

/* uncore_nhmex.c */
void nhmex_uncore_cpu_init(void);
Commit	Line	Data
087bfbb0	1	#include <linux/slab.h>
14371cce	2	#include <linux/pci.h>
6f6e1516 IM	3	#include <asm/apicdef.h>
6f6e1516 IM	4
087bfbb0	5	#include <linux/perf_event.h>
27f6d22b	6	#include "../perf_event.h"
087bfbb0 YZ	7
087bfbb0 YZ	8	#define UNCORE_PMU_NAME_LEN 32
7740dfc0	9	#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
ced2efb0	10	#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
087bfbb0	11
eca26c99	12	#define UNCORE_FIXED_EVENT 0xff
087bfbb0 YZ	13	#define UNCORE_PMC_IDX_MAX_GENERIC 8
	14	#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
	15	#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1)
	16
a54fa079 KL	17	#define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx) \
a54fa079 KL	18	((dev << 24) \| (func << 16) \| (type << 8) \| idx)
899396cf	19	#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) \| idx)
a54fa079 KL	20	#define UNCORE_PCI_DEV_DEV(data) ((data >> 24) & 0xff)
a54fa079 KL	21	#define UNCORE_PCI_DEV_FUNC(data) ((data >> 16) & 0xff)
899396cf YZ	22	#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
	23	#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
	24	#define UNCORE_EXTRA_PCI_DEV 0xff
5306c31c	25	#define UNCORE_EXTRA_PCI_DEV_MAX 3
899396cf	26
087bfbb0 YZ	27	#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
087bfbb0 YZ	28
cf6d445f TG	29	struct pci_extra_dev {
	30	struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
	31	};
	32
087bfbb0 YZ	33	struct intel_uncore_ops;
	34	struct intel_uncore_pmu;
	35	struct intel_uncore_box;
	36	struct uncore_event_desc;
	37
	38	struct intel_uncore_type {
	39	const char *name;
	40	int num_counters;
	41	int num_boxes;
	42	int perf_ctr_bits;
	43	int fixed_ctr_bits;
087bfbb0 YZ	44	unsigned perf_ctr;
	45	unsigned event_ctl;
	46	unsigned event_mask;
cd34cd97	47	unsigned event_mask_ext;
087bfbb0 YZ	48	unsigned fixed_ctr;
	49	unsigned fixed_ctl;
	50	unsigned box_ctl;
	51	unsigned msr_offset;
6a67943a YZ	52	unsigned num_shared_regs:8;
6a67943a YZ	53	unsigned single_fixed:1;
254298c7	54	unsigned pair_ctr_ctl:1;
cb37af77	55	unsigned *msr_offsets;
087bfbb0 YZ	56	struct event_constraint unconstrainted;
	57	struct event_constraint *constraints;
	58	struct intel_uncore_pmu *pmus;
	59	struct intel_uncore_ops *ops;
	60	struct uncore_event_desc *event_descs;
314d9f63	61	const struct attribute_group *attr_groups[4];
d64b25b6	62	struct pmu pmu; / for custom pmu ops */
087bfbb0 YZ	63	};
087bfbb0 YZ	64
314d9f63 YZ	65	#define pmu_group attr_groups[0]
	66	#define format_group attr_groups[1]
	67	#define events_group attr_groups[2]
087bfbb0 YZ	68
	69	struct intel_uncore_ops {
	70	void (init_box)(struct intel_uncore_box );
a46195f1	71	void (exit_box)(struct intel_uncore_box );
087bfbb0 YZ	72	void (disable_box)(struct intel_uncore_box );
	73	void (enable_box)(struct intel_uncore_box );
	74	void (disable_event)(struct intel_uncore_box , struct perf_event *);
	75	void (enable_event)(struct intel_uncore_box , struct perf_event *);
	76	u64 (read_counter)(struct intel_uncore_box , struct perf_event *);
6a67943a YZ	77	int (hw_config)(struct intel_uncore_box , struct perf_event *);
	78	struct event_constraint (get_constraint)(struct intel_uncore_box *,
	79	struct perf_event *);
	80	void (put_constraint)(struct intel_uncore_box , struct perf_event *);
087bfbb0 YZ	81	};
	82
	83	struct intel_uncore_pmu {
4f089678 TG	84	struct pmu pmu;
	85	char name[UNCORE_PMU_NAME_LEN];
	86	int pmu_idx;
	87	int func_id;
	88	bool registered;
cf6d445f	89	atomic_t activeboxes;
4f089678	90	struct intel_uncore_type *type;
cf6d445f	91	struct intel_uncore_box **boxes;
087bfbb0 YZ	92	};
087bfbb0 YZ	93
6a67943a YZ	94	struct intel_uncore_extra_reg {
6a67943a YZ	95	raw_spinlock_t lock;
254298c7	96	u64 config, config1, config2;
6a67943a YZ	97	atomic_t ref;
	98	};
	99
087bfbb0	100	struct intel_uncore_box {
cf6d445f TG	101	int pci_phys_id;
cf6d445f TG	102	int pkgid;
087bfbb0 YZ	103	int n_active; /* number of active events */
	104	int n_events;
	105	int cpu; /* cpu to collect events */
	106	unsigned long flags;
	107	atomic_t refcnt;
	108	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	109	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
b371b594	110	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
087bfbb0 YZ	111	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
087bfbb0 YZ	112	u64 tags[UNCORE_PMC_IDX_MAX];
14371cce	113	struct pci_dev *pci_dev;
087bfbb0	114	struct intel_uncore_pmu *pmu;
79859cce	115	u64 hrtimer_duration; /* hrtimer timeout for this box */
087bfbb0 YZ	116	struct hrtimer hrtimer;
087bfbb0 YZ	117	struct list_head list;
ced2efb0	118	struct list_head active_list;
b9e1ab6d	119	void *io_addr;
6a67943a	120	struct intel_uncore_extra_reg shared_regs[0];
087bfbb0 YZ	121	};
	122
	123	#define UNCORE_BOX_FLAG_INITIATED 0
24cf8467	124	#define UNCORE_BOX_FLAG_CTL_OFFS8 1 /* event config registers are 8-byte apart */
087bfbb0 YZ	125
	126	struct uncore_event_desc {
	127	struct kobj_attribute attr;
	128	const char *config;
	129	};
	130
712df65c TI	131	struct pci2phy_map {
	132	struct list_head list;
	133	int segment;
	134	int pbus_to_physid[256];
	135	};
	136
712df65c TI	137	struct pci2phy_map *__find_pci2phy_map(int segment);
712df65c TI	138
514b2346 YZ	139	ssize_t uncore_event_show(struct kobject *kobj,
	140	struct kobj_attribute attr, char buf);
	141
087bfbb0 YZ	142	#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
	143	{ \
	144	.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
	145	.config = _config, \
	146	}
	147
	148	#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
	149	static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
	150	struct kobj_attribute *attr, \
	151	char *page) \
	152	{ \
	153	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
	154	return sprintf(page, _format "\n"); \
	155	} \
	156	static struct kobj_attribute format_attr_##_var = \
	157	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
	158
14371cce YZ	159	static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
	160	{
	161	return box->pmu->type->box_ctl;
	162	}
	163
	164	static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
	165	{
	166	return box->pmu->type->fixed_ctl;
	167	}
	168
	169	static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
	170	{
	171	return box->pmu->type->fixed_ctr;
	172	}
	173
	174	static inline
	175	unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
	176	{
24cf8467 SE	177	if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
	178	return idx * 8 + box->pmu->type->event_ctl;
	179
14371cce YZ	180	return idx * 4 + box->pmu->type->event_ctl;
	181	}
	182
	183	static inline
	184	unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
	185	{
	186	return idx * 8 + box->pmu->type->perf_ctr;
	187	}
	188
cb37af77 YZ	189	static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
	190	{
	191	struct intel_uncore_pmu *pmu = box->pmu;
	192	return pmu->type->msr_offsets ?
	193	pmu->type->msr_offsets[pmu->pmu_idx] :
	194	pmu->type->msr_offset * pmu->pmu_idx;
	195	}
	196
	197	static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	198	{
	199	if (!box->pmu->type->box_ctl)
	200	return 0;
cb37af77	201	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	202	}
087bfbb0 YZ	203
cb37af77	204	static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	205	{
	206	if (!box->pmu->type->fixed_ctl)
	207	return 0;
cb37af77	208	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	209	}
087bfbb0 YZ	210
cb37af77	211	static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
087bfbb0	212	{
cb37af77	213	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
087bfbb0 YZ	214	}
	215
	216	static inline
	217	unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
	218	{
254298c7 YZ	219	return box->pmu->type->event_ctl +
254298c7 YZ	220	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	221	uncore_msr_box_offset(box);
087bfbb0 YZ	222	}
	223
	224	static inline
	225	unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
	226	{
254298c7 YZ	227	return box->pmu->type->perf_ctr +
254298c7 YZ	228	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	229	uncore_msr_box_offset(box);
087bfbb0 YZ	230	}
087bfbb0 YZ	231
14371cce YZ	232	static inline
	233	unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
	234	{
	235	if (box->pci_dev)
	236	return uncore_pci_fixed_ctl(box);
	237	else
	238	return uncore_msr_fixed_ctl(box);
	239	}
	240
	241	static inline
	242	unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
	243	{
	244	if (box->pci_dev)
	245	return uncore_pci_fixed_ctr(box);
	246	else
	247	return uncore_msr_fixed_ctr(box);
	248	}
	249
	250	static inline
	251	unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
	252	{
	253	if (box->pci_dev)
	254	return uncore_pci_event_ctl(box, idx);
	255	else
	256	return uncore_msr_event_ctl(box, idx);
	257	}
	258
	259	static inline
	260	unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
	261	{
	262	if (box->pci_dev)
	263	return uncore_pci_perf_ctr(box, idx);
	264	else
	265	return uncore_msr_perf_ctr(box, idx);
	266	}
	267
087bfbb0 YZ	268	static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
	269	{
	270	return box->pmu->type->perf_ctr_bits;
	271	}
	272
	273	static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
	274	{
	275	return box->pmu->type->fixed_ctr_bits;
	276	}
	277
	278	static inline int uncore_num_counters(struct intel_uncore_box *box)
	279	{
	280	return box->pmu->type->num_counters;
	281	}
	282
	283	static inline void uncore_disable_box(struct intel_uncore_box *box)
	284	{
	285	if (box->pmu->type->ops->disable_box)
	286	box->pmu->type->ops->disable_box(box);
	287	}
	288
	289	static inline void uncore_enable_box(struct intel_uncore_box *box)
	290	{
	291	if (box->pmu->type->ops->enable_box)
	292	box->pmu->type->ops->enable_box(box);
	293	}
	294
	295	static inline void uncore_disable_event(struct intel_uncore_box *box,
	296	struct perf_event *event)
	297	{
	298	box->pmu->type->ops->disable_event(box, event);
	299	}
	300
	301	static inline void uncore_enable_event(struct intel_uncore_box *box,
	302	struct perf_event *event)
	303	{
	304	box->pmu->type->ops->enable_event(box, event);
	305	}
	306
	307	static inline u64 uncore_read_counter(struct intel_uncore_box *box,
	308	struct perf_event *event)
	309	{
	310	return box->pmu->type->ops->read_counter(box, event);
	311	}
	312
15c12479 IM	313	static inline void uncore_box_init(struct intel_uncore_box *box)
	314	{
	315	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	316	if (box->pmu->type->ops->init_box)
	317	box->pmu->type->ops->init_box(box);
	318	}
	319	}
	320
a46195f1 TG	321	static inline void uncore_box_exit(struct intel_uncore_box *box)
	322	{
	323	if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	324	if (box->pmu->type->ops->exit_box)
	325	box->pmu->type->ops->exit_box(box);
	326	}
	327	}
	328
254298c7 YZ	329	static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
254298c7 YZ	330	{
cf6d445f	331	return (box->pkgid < 0);
254298c7	332	}
514b2346	333
1f2569fa TG	334	static inline struct intel_uncore_pmu uncore_event_to_pmu(struct perf_event event)
	335	{
	336	return container_of(event->pmu, struct intel_uncore_pmu, pmu);
	337	}
	338
	339	static inline struct intel_uncore_box uncore_event_to_box(struct perf_event event)
	340	{
	341	return event->pmu_private;
	342	}
	343
514b2346	344	struct intel_uncore_box uncore_pmu_to_box(struct intel_uncore_pmu pmu, int cpu);
514b2346 YZ	345	u64 uncore_msr_read_counter(struct intel_uncore_box box, struct perf_event event);
	346	void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
	347	void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
	348	void uncore_pmu_event_read(struct perf_event *event);
	349	void uncore_perf_event_update(struct intel_uncore_box box, struct perf_event event);
	350	struct event_constraint *
	351	uncore_get_constraint(struct intel_uncore_box box, struct perf_event event);
	352	void uncore_put_constraint(struct intel_uncore_box box, struct perf_event event);
	353	u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
	354
	355	extern struct intel_uncore_type **uncore_msr_uncores;
	356	extern struct intel_uncore_type **uncore_pci_uncores;
	357	extern struct pci_driver *uncore_pci_driver;
712df65c TI	358	extern raw_spinlock_t pci2phy_map_lock;
712df65c TI	359	extern struct list_head pci2phy_map_head;
cf6d445f	360	extern struct pci_extra_dev *uncore_extra_pci_dev;
514b2346	361	extern struct event_constraint uncore_constraint_empty;
92807ffd	362
940b2f2f	363	/* uncore_snb.c */
92807ffd YZ	364	int snb_uncore_pci_init(void);
	365	int ivb_uncore_pci_init(void);
	366	int hsw_uncore_pci_init(void);
a41f3c8c	367	int bdw_uncore_pci_init(void);
0e1eb0a1	368	int skl_uncore_pci_init(void);
92807ffd YZ	369	void snb_uncore_cpu_init(void);
92807ffd YZ	370	void nhm_uncore_cpu_init(void);
46866b59	371	void skl_uncore_cpu_init(void);
77af0037	372	int snb_pci2phy_map_init(int devid);
8268fdfc	373
940b2f2f	374	/* uncore_snbep.c */
8268fdfc YZ	375	int snbep_uncore_pci_init(void);
8268fdfc YZ	376	void snbep_uncore_cpu_init(void);
ddcd0973 PZ	377	int ivbep_uncore_pci_init(void);
ddcd0973 PZ	378	void ivbep_uncore_cpu_init(void);
e735b9db YZ	379	int hswep_uncore_pci_init(void);
e735b9db YZ	380	void hswep_uncore_cpu_init(void);
070e9887 KL	381	int bdx_uncore_pci_init(void);
070e9887 KL	382	void bdx_uncore_cpu_init(void);
77af0037 HC	383	int knl_uncore_pci_init(void);
77af0037 HC	384	void knl_uncore_cpu_init(void);
cd34cd97 KL	385	int skx_uncore_pci_init(void);
cd34cd97 KL	386	void skx_uncore_cpu_init(void);
c1e46580	387
940b2f2f	388	/* uncore_nhmex.c */
c1e46580	389	void nhmex_uncore_cpu_init(void);