[mirror_ubuntu-bionic-kernel.git] / arch / x86 / events / msr.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/perf_event.h>
#include <linux/nospec.h>
#include <asm/intel-family.h>

enum perf_msr_id {
	PERF_MSR_TSC			= 0,
	PERF_MSR_APERF			= 1,
	PERF_MSR_MPERF			= 2,
	PERF_MSR_PPERF			= 3,
	PERF_MSR_SMI			= 4,
	PERF_MSR_PTSC			= 5,
	PERF_MSR_IRPERF			= 6,

	PERF_MSR_EVENT_MAX,
};

static bool test_aperfmperf(int idx)
{
	return boot_cpu_has(X86_FEATURE_APERFMPERF);
}

static bool test_ptsc(int idx)
{
	return boot_cpu_has(X86_FEATURE_PTSC);
}

static bool test_irperf(int idx)
{
	return boot_cpu_has(X86_FEATURE_IRPERF);
}

static bool test_intel(int idx)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
	    boot_cpu_data.x86 != 6)
		return false;

	switch (boot_cpu_data.x86_model) {
	case INTEL_FAM6_NEHALEM:
	case INTEL_FAM6_NEHALEM_G:
	case INTEL_FAM6_NEHALEM_EP:
	case INTEL_FAM6_NEHALEM_EX:

	case INTEL_FAM6_WESTMERE:
	case INTEL_FAM6_WESTMERE_EP:
	case INTEL_FAM6_WESTMERE_EX:

	case INTEL_FAM6_SANDYBRIDGE:
	case INTEL_FAM6_SANDYBRIDGE_X:

	case INTEL_FAM6_IVYBRIDGE:
	case INTEL_FAM6_IVYBRIDGE_X:

	case INTEL_FAM6_HASWELL_CORE:
	case INTEL_FAM6_HASWELL_X:
	case INTEL_FAM6_HASWELL_ULT:
	case INTEL_FAM6_HASWELL_GT3E:

	case INTEL_FAM6_BROADWELL_CORE:
	case INTEL_FAM6_BROADWELL_XEON_D:
	case INTEL_FAM6_BROADWELL_GT3E:
	case INTEL_FAM6_BROADWELL_X:

	case INTEL_FAM6_ATOM_SILVERMONT:
	case INTEL_FAM6_ATOM_SILVERMONT_X:
	case INTEL_FAM6_ATOM_AIRMONT:

	case INTEL_FAM6_ATOM_GOLDMONT:
	case INTEL_FAM6_ATOM_GOLDMONT_X:

	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:

	case INTEL_FAM6_XEON_PHI_KNL:
	case INTEL_FAM6_XEON_PHI_KNM:
		if (idx == PERF_MSR_SMI)
			return true;
		break;

	case INTEL_FAM6_SKYLAKE_MOBILE:
	case INTEL_FAM6_SKYLAKE_DESKTOP:
	case INTEL_FAM6_SKYLAKE_X:
	case INTEL_FAM6_KABYLAKE_MOBILE:
	case INTEL_FAM6_KABYLAKE_DESKTOP:
		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
			return true;
		break;
	}

	return false;
}

struct perf_msr {
	u64	msr;
	struct	perf_pmu_events_attr *attr;
	bool	(*test)(int idx);
};

PMU_EVENT_ATTR_STRING(tsc,    evattr_tsc,    "event=0x00");
PMU_EVENT_ATTR_STRING(aperf,  evattr_aperf,  "event=0x01");
PMU_EVENT_ATTR_STRING(mperf,  evattr_mperf,  "event=0x02");
PMU_EVENT_ATTR_STRING(pperf,  evattr_pperf,  "event=0x03");
PMU_EVENT_ATTR_STRING(smi,    evattr_smi,    "event=0x04");
PMU_EVENT_ATTR_STRING(ptsc,   evattr_ptsc,   "event=0x05");
PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");

static struct perf_msr msr[] = {
	[PERF_MSR_TSC]    = { 0,		&evattr_tsc,	NULL,		 },
	[PERF_MSR_APERF]  = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
	[PERF_MSR_MPERF]  = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
	[PERF_MSR_PPERF]  = { MSR_PPERF,	&evattr_pperf,	test_intel,	 },
	[PERF_MSR_SMI]    = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },
	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF,	&evattr_irperf,	test_irperf,	 },
};

static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
	NULL,
};

static struct attribute_group events_attr_group = {
	.name = "events",
	.attrs = events_attrs,
};

PMU_FORMAT_ATTR(event, "config:0-63");
static struct attribute *format_attrs[] = {
	&format_attr_event.attr,
	NULL,
};
static struct attribute_group format_attr_group = {
	.name = "format",
	.attrs = format_attrs,
};

static const struct attribute_group *attr_groups[] = {
	&events_attr_group,
	&format_attr_group,
	NULL,
};

static int msr_event_init(struct perf_event *event)
{
	u64 cfg = event->attr.config;

	if (event->attr.type != event->pmu->type)
		return -ENOENT;

	/* unsupported modes and filters */
	if (event->attr.exclude_user   ||
	    event->attr.exclude_kernel ||
	    event->attr.exclude_hv     ||
	    event->attr.exclude_idle   ||
	    event->attr.exclude_host   ||
	    event->attr.exclude_guest  ||
	    event->attr.sample_period) /* no sampling */
		return -EINVAL;

	if (cfg >= PERF_MSR_EVENT_MAX)
		return -EINVAL;

	cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);

	if (!msr[cfg].attr)
		return -EINVAL;

	event->hw.idx = -1;
	event->hw.event_base = msr[cfg].msr;
	event->hw.config = cfg;

	return 0;
}

static inline u64 msr_read_counter(struct perf_event *event)
{
	u64 now;

	if (event->hw.event_base)
		rdmsrl(event->hw.event_base, now);
	else
		rdtscll(now);

	return now;
}
static void msr_event_update(struct perf_event *event)
{
	u64 prev, now;
	s64 delta;

	/* Careful, an NMI might modify the previous event value. */
again:
	prev = local64_read(&event->hw.prev_count);
	now = msr_read_counter(event);

	if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
		goto again;

	delta = now - prev;
	if (unlikely(event->hw.event_base == MSR_SMI_COUNT))
		delta = sign_extend64(delta, 31);

	local64_add(delta, &event->count);
}

static void msr_event_start(struct perf_event *event, int flags)
{
	u64 now;

	now = msr_read_counter(event);
	local64_set(&event->hw.prev_count, now);
}

static void msr_event_stop(struct perf_event *event, int flags)
{
	msr_event_update(event);
}

static void msr_event_del(struct perf_event *event, int flags)
{
	msr_event_stop(event, PERF_EF_UPDATE);
}

static int msr_event_add(struct perf_event *event, int flags)
{
	if (flags & PERF_EF_START)
		msr_event_start(event, flags);

	return 0;
}

static struct pmu pmu_msr = {
	.task_ctx_nr	= perf_sw_context,
	.attr_groups	= attr_groups,
	.event_init	= msr_event_init,
	.add		= msr_event_add,
	.del		= msr_event_del,
	.start		= msr_event_start,
	.stop		= msr_event_stop,
	.read		= msr_event_update,
	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
};

static int __init msr_init(void)
{
	int i, j = 0;

	if (!boot_cpu_has(X86_FEATURE_TSC)) {
		pr_cont("no MSR PMU driver.\n");
		return 0;
	}

	/* Probe the MSRs. */
	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
		u64 val;

		/*
		 * Virt sucks arse; you cannot tell if a R/O MSR is present :/
		 */
		if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
			msr[i].attr = NULL;
	}

	/* List remaining MSRs in the sysfs attrs. */
	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
		if (msr[i].attr)
			events_attrs[j++] = &msr[i].attr->attr.attr;
	}
	events_attrs[j] = NULL;

	perf_pmu_register(&pmu_msr, "msr", -1);

	return 0;
}
device_initcall(msr_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
b7b7c782	2	#include <linux/perf_event.h>
44b2a2ed	3	#include <linux/nospec.h>
353bf605	4	#include <asm/intel-family.h>
b7b7c782 AL	5
	6	enum perf_msr_id {
	7	PERF_MSR_TSC = 0,
	8	PERF_MSR_APERF = 1,
	9	PERF_MSR_MPERF = 2,
	10	PERF_MSR_PPERF = 3,
	11	PERF_MSR_SMI = 4,
8a224261	12	PERF_MSR_PTSC = 5,
aaf24884	13	PERF_MSR_IRPERF = 6,
b7b7c782 AL	14
	15	PERF_MSR_EVENT_MAX,
	16	};
	17
7e5560a5	18	static bool test_aperfmperf(int idx)
19b3340c PZ	19	{
	20	return boot_cpu_has(X86_FEATURE_APERFMPERF);
	21	}
	22
8a224261 HR	23	static bool test_ptsc(int idx)
	24	{
	25	return boot_cpu_has(X86_FEATURE_PTSC);
	26	}
	27
aaf24884 HR	28	static bool test_irperf(int idx)
	29	{
	30	return boot_cpu_has(X86_FEATURE_IRPERF);
	31	}
	32
7e5560a5	33	static bool test_intel(int idx)
19b3340c PZ	34	{
	35	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL \|\|
	36	boot_cpu_data.x86 != 6)
	37	return false;
	38
	39	switch (boot_cpu_data.x86_model) {
353bf605	40	case INTEL_FAM6_NEHALEM:
b325e04e	41	case INTEL_FAM6_NEHALEM_G:
353bf605 DH	42	case INTEL_FAM6_NEHALEM_EP:
353bf605 DH	43	case INTEL_FAM6_NEHALEM_EX:
19b3340c	44
353bf605 DH	45	case INTEL_FAM6_WESTMERE:
	46	case INTEL_FAM6_WESTMERE_EP:
	47	case INTEL_FAM6_WESTMERE_EX:
19b3340c	48
353bf605 DH	49	case INTEL_FAM6_SANDYBRIDGE:
353bf605 DH	50	case INTEL_FAM6_SANDYBRIDGE_X:
19b3340c	51
353bf605 DH	52	case INTEL_FAM6_IVYBRIDGE:
353bf605 DH	53	case INTEL_FAM6_IVYBRIDGE_X:
19b3340c	54
353bf605 DH	55	case INTEL_FAM6_HASWELL_CORE:
	56	case INTEL_FAM6_HASWELL_X:
	57	case INTEL_FAM6_HASWELL_ULT:
	58	case INTEL_FAM6_HASWELL_GT3E:
19b3340c	59
353bf605 DH	60	case INTEL_FAM6_BROADWELL_CORE:
	61	case INTEL_FAM6_BROADWELL_XEON_D:
	62	case INTEL_FAM6_BROADWELL_GT3E:
	63	case INTEL_FAM6_BROADWELL_X:
19b3340c	64
2811e5d5 PZ	65	case INTEL_FAM6_ATOM_SILVERMONT:
2811e5d5 PZ	66	case INTEL_FAM6_ATOM_SILVERMONT_X:
353bf605	67	case INTEL_FAM6_ATOM_AIRMONT:
1aaccc40 KL	68
1aaccc40 KL	69	case INTEL_FAM6_ATOM_GOLDMONT:
2811e5d5	70	case INTEL_FAM6_ATOM_GOLDMONT_X:
1aaccc40	71
2811e5d5	72	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1aaccc40 KL	73
	74	case INTEL_FAM6_XEON_PHI_KNL:
	75	case INTEL_FAM6_XEON_PHI_KNM:
19b3340c PZ	76	if (idx == PERF_MSR_SMI)
	77	return true;
	78	break;
	79
353bf605 DH	80	case INTEL_FAM6_SKYLAKE_MOBILE:
353bf605 DH	81	case INTEL_FAM6_SKYLAKE_DESKTOP:
5134596c DH	82	case INTEL_FAM6_SKYLAKE_X:
	83	case INTEL_FAM6_KABYLAKE_MOBILE:
	84	case INTEL_FAM6_KABYLAKE_DESKTOP:
19b3340c PZ	85	if (idx == PERF_MSR_SMI \|\| idx == PERF_MSR_PPERF)
	86	return true;
	87	break;
	88	}
	89
	90	return false;
	91	}
	92
b7b7c782	93	struct perf_msr {
b7b7c782	94	u64 msr;
19b3340c PZ	95	struct perf_pmu_events_attr *attr;
19b3340c PZ	96	bool (*test)(int idx);
b7b7c782 AL	97	};
b7b7c782 AL	98
aaf24884 HR	99	PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00");
	100	PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
	101	PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
	102	PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
	103	PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04");
	104	PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05");
	105	PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");
b7b7c782	106
19b3340c	107	static struct perf_msr msr[] = {
aaf24884 HR	108	[PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, },
	109	[PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, },
	110	[PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, },
	111	[PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, },
	112	[PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, },
8a224261	113	[PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, },
aaf24884	114	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, },
19b3340c PZ	115	};
19b3340c PZ	116
b7b7c782	117	static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
19b3340c	118	NULL,
b7b7c782 AL	119	};
	120
	121	static struct attribute_group events_attr_group = {
	122	.name = "events",
	123	.attrs = events_attrs,
	124	};
	125
	126	PMU_FORMAT_ATTR(event, "config:0-63");
	127	static struct attribute *format_attrs[] = {
	128	&format_attr_event.attr,
	129	NULL,
	130	};
	131	static struct attribute_group format_attr_group = {
	132	.name = "format",
	133	.attrs = format_attrs,
	134	};
	135
	136	static const struct attribute_group *attr_groups[] = {
	137	&events_attr_group,
	138	&format_attr_group,
	139	NULL,
	140	};
	141
	142	static int msr_event_init(struct perf_event *event)
	143	{
	144	u64 cfg = event->attr.config;
	145
	146	if (event->attr.type != event->pmu->type)
	147	return -ENOENT;
	148
b7b7c782 AL	149	/* unsupported modes and filters */
	150	if (event->attr.exclude_user \|\|
	151	event->attr.exclude_kernel \|\|
	152	event->attr.exclude_hv \|\|
	153	event->attr.exclude_idle \|\|
	154	event->attr.exclude_host \|\|
	155	event->attr.exclude_guest \|\|
	156	event->attr.sample_period) /* no sampling */
	157	return -EINVAL;
	158
44b2a2ed PZ	159	if (cfg >= PERF_MSR_EVENT_MAX)
	160	return -EINVAL;
	161
	162	cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
	163
19b3340c PZ	164	if (!msr[cfg].attr)
	165	return -EINVAL;
	166
b7b7c782 AL	167	event->hw.idx = -1;
	168	event->hw.event_base = msr[cfg].msr;
	169	event->hw.config = cfg;
	170
	171	return 0;
	172	}
	173
	174	static inline u64 msr_read_counter(struct perf_event *event)
	175	{
	176	u64 now;
	177
	178	if (event->hw.event_base)
	179	rdmsrl(event->hw.event_base, now);
	180	else
82819ffb	181	rdtscll(now);
b7b7c782 AL	182
	183	return now;
	184	}
	185	static void msr_event_update(struct perf_event *event)
	186	{
	187	u64 prev, now;
	188	s64 delta;
	189
	190	/* Careful, an NMI might modify the previous event value. */
	191	again:
	192	prev = local64_read(&event->hw.prev_count);
	193	now = msr_read_counter(event);
	194
	195	if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
	196	goto again;
	197
	198	delta = now - prev;
78e3c795 MK	199	if (unlikely(event->hw.event_base == MSR_SMI_COUNT))
	200	delta = sign_extend64(delta, 31);
	201
3c3116b7	202	local64_add(delta, &event->count);
b7b7c782 AL	203	}
	204
	205	static void msr_event_start(struct perf_event *event, int flags)
	206	{
	207	u64 now;
	208
	209	now = msr_read_counter(event);
	210	local64_set(&event->hw.prev_count, now);
	211	}
	212
	213	static void msr_event_stop(struct perf_event *event, int flags)
	214	{
	215	msr_event_update(event);
	216	}
	217
	218	static void msr_event_del(struct perf_event *event, int flags)
	219	{
	220	msr_event_stop(event, PERF_EF_UPDATE);
	221	}
	222
	223	static int msr_event_add(struct perf_event *event, int flags)
	224	{
	225	if (flags & PERF_EF_START)
	226	msr_event_start(event, flags);
	227
	228	return 0;
	229	}
	230
	231	static struct pmu pmu_msr = {
	232	.task_ctx_nr = perf_sw_context,
	233	.attr_groups = attr_groups,
	234	.event_init = msr_event_init,
	235	.add = msr_event_add,
	236	.del = msr_event_del,
	237	.start = msr_event_start,
	238	.stop = msr_event_stop,
	239	.read = msr_event_update,
	240	.capabilities = PERF_PMU_CAP_NO_INTERRUPT,
	241	};
	242
b7b7c782 AL	243	static int __init msr_init(void)
b7b7c782 AL	244	{
19b3340c	245	int i, j = 0;
b7b7c782	246
19b3340c PZ	247	if (!boot_cpu_has(X86_FEATURE_TSC)) {
	248	pr_cont("no MSR PMU driver.\n");
	249	return 0;
b7b7c782 AL	250	}
b7b7c782 AL	251
19b3340c PZ	252	/* Probe the MSRs. */
	253	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
	254	u64 val;
b7b7c782	255
19b3340c PZ	256	/*
	257	* Virt sucks arse; you cannot tell if a R/O MSR is present :/
	258	*/
	259	if (!msr[i].test(i) \|\| rdmsrl_safe(msr[i].msr, &val))
	260	msr[i].attr = NULL;
b7b7c782 AL	261	}
b7b7c782 AL	262
19b3340c PZ	263	/* List remaining MSRs in the sysfs attrs. */
	264	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
	265	if (msr[i].attr)
	266	events_attrs[j++] = &msr[i].attr->attr.attr;
b7b7c782	267	}
19b3340c	268	events_attrs[j] = NULL;
b7b7c782 AL	269
	270	perf_pmu_register(&pmu_msr, "msr", -1);
	271
	272	return 0;
	273	}
	274	device_initcall(msr_init);