[mirror_ubuntu-jammy-kernel.git] / arch / x86 / events / msr.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/perf_event.h>
#include <asm/intel-family.h>

enum perf_msr_id {
	PERF_MSR_TSC			= 0,
	PERF_MSR_APERF			= 1,
	PERF_MSR_MPERF			= 2,
	PERF_MSR_PPERF			= 3,
	PERF_MSR_SMI			= 4,
	PERF_MSR_PTSC			= 5,
	PERF_MSR_IRPERF			= 6,
	PERF_MSR_THERM			= 7,
	PERF_MSR_THERM_SNAP		= 8,
	PERF_MSR_THERM_UNIT		= 9,
	PERF_MSR_EVENT_MAX,
};

static bool test_aperfmperf(int idx)
{
	return boot_cpu_has(X86_FEATURE_APERFMPERF);
}

static bool test_ptsc(int idx)
{
	return boot_cpu_has(X86_FEATURE_PTSC);
}

static bool test_irperf(int idx)
{
	return boot_cpu_has(X86_FEATURE_IRPERF);
}

static bool test_therm_status(int idx)
{
	return boot_cpu_has(X86_FEATURE_DTHERM);
}


static bool test_intel(int idx)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
	    boot_cpu_data.x86 != 6)
		return false;

	switch (boot_cpu_data.x86_model) {
	case INTEL_FAM6_NEHALEM:
	case INTEL_FAM6_NEHALEM_G:
	case INTEL_FAM6_NEHALEM_EP:
	case INTEL_FAM6_NEHALEM_EX:

	case INTEL_FAM6_WESTMERE:
	case INTEL_FAM6_WESTMERE_EP:
	case INTEL_FAM6_WESTMERE_EX:

	case INTEL_FAM6_SANDYBRIDGE:
	case INTEL_FAM6_SANDYBRIDGE_X:

	case INTEL_FAM6_IVYBRIDGE:
	case INTEL_FAM6_IVYBRIDGE_X:

	case INTEL_FAM6_HASWELL_CORE:
	case INTEL_FAM6_HASWELL_X:
	case INTEL_FAM6_HASWELL_ULT:
	case INTEL_FAM6_HASWELL_GT3E:

	case INTEL_FAM6_BROADWELL_CORE:
	case INTEL_FAM6_BROADWELL_XEON_D:
	case INTEL_FAM6_BROADWELL_GT3E:
	case INTEL_FAM6_BROADWELL_X:

	case INTEL_FAM6_ATOM_SILVERMONT1:
	case INTEL_FAM6_ATOM_SILVERMONT2:
	case INTEL_FAM6_ATOM_AIRMONT:

	case INTEL_FAM6_ATOM_GOLDMONT:
	case INTEL_FAM6_ATOM_DENVERTON:

	case INTEL_FAM6_ATOM_GEMINI_LAKE:

	case INTEL_FAM6_XEON_PHI_KNL:
	case INTEL_FAM6_XEON_PHI_KNM:
		if (idx == PERF_MSR_SMI)
			return true;
		break;

	case INTEL_FAM6_SKYLAKE_MOBILE:
	case INTEL_FAM6_SKYLAKE_DESKTOP:
	case INTEL_FAM6_SKYLAKE_X:
	case INTEL_FAM6_KABYLAKE_MOBILE:
	case INTEL_FAM6_KABYLAKE_DESKTOP:
		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
			return true;
		break;
	}

	return false;
}

struct perf_msr {
	u64	msr;
	struct	perf_pmu_events_attr *attr;
	bool	(*test)(int idx);
};

PMU_EVENT_ATTR_STRING(tsc,    evattr_tsc,    "event=0x00");
PMU_EVENT_ATTR_STRING(aperf,  evattr_aperf,  "event=0x01");
PMU_EVENT_ATTR_STRING(mperf,  evattr_mperf,  "event=0x02");
PMU_EVENT_ATTR_STRING(pperf,  evattr_pperf,  "event=0x03");
PMU_EVENT_ATTR_STRING(smi,    evattr_smi,    "event=0x04");
PMU_EVENT_ATTR_STRING(ptsc,   evattr_ptsc,   "event=0x05");
PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");
PMU_EVENT_ATTR_STRING(cpu_thermal_margin, evattr_therm, "event=0x07");
PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, evattr_therm_snap, "1");
PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, evattr_therm_unit, "C");

static struct perf_msr msr[] = {
	[PERF_MSR_TSC]    = { 0,		&evattr_tsc,	NULL,		 },
	[PERF_MSR_APERF]  = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
	[PERF_MSR_MPERF]  = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
	[PERF_MSR_PPERF]  = { MSR_PPERF,	&evattr_pperf,	test_intel,	 },
	[PERF_MSR_SMI]    = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },
	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF,	&evattr_irperf,	test_irperf,	 },
	[PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &evattr_therm,	     test_therm_status, },
	[PERF_MSR_THERM_SNAP] = { MSR_IA32_THERM_STATUS, &evattr_therm_snap, test_therm_status, },
	[PERF_MSR_THERM_UNIT] = { MSR_IA32_THERM_STATUS, &evattr_therm_unit, test_therm_status, },
};

static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
	NULL,
};

static struct attribute_group events_attr_group = {
	.name = "events",
	.attrs = events_attrs,
};

PMU_FORMAT_ATTR(event, "config:0-63");
static struct attribute *format_attrs[] = {
	&format_attr_event.attr,
	NULL,
};
static struct attribute_group format_attr_group = {
	.name = "format",
	.attrs = format_attrs,
};

static const struct attribute_group *attr_groups[] = {
	&events_attr_group,
	&format_attr_group,
	NULL,
};

static int msr_event_init(struct perf_event *event)
{
	u64 cfg = event->attr.config;

	if (event->attr.type != event->pmu->type)
		return -ENOENT;

	if (cfg >= PERF_MSR_EVENT_MAX)
		return -EINVAL;

	/* unsupported modes and filters */
	if (event->attr.exclude_user   ||
	    event->attr.exclude_kernel ||
	    event->attr.exclude_hv     ||
	    event->attr.exclude_idle   ||
	    event->attr.exclude_host   ||
	    event->attr.exclude_guest  ||
	    event->attr.sample_period) /* no sampling */
		return -EINVAL;

	if (!msr[cfg].attr)
		return -EINVAL;

	event->hw.idx = -1;
	event->hw.event_base = msr[cfg].msr;
	event->hw.config = cfg;

	return 0;
}

static inline u64 msr_read_counter(struct perf_event *event)
{
	u64 now;

	if (event->hw.event_base)
		rdmsrl(event->hw.event_base, now);
	else
		rdtscll(now);

	return now;
}
static void msr_event_update(struct perf_event *event)
{
	u64 prev, now;
	s64 delta;

	/* Careful, an NMI might modify the previous event value. */
again:
	prev = local64_read(&event->hw.prev_count);
	now = msr_read_counter(event);

	if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
		goto again;

	delta = now - prev;
	if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
		delta = sign_extend64(delta, 31);
		local64_add(delta, &event->count);
	} else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
		/* if valid, extract digital readout, other set to -1 */
		now = now & (1ULL << 31) ? (now >> 16) & 0x3f :  -1;
		local64_set(&event->count, now);
	} else
		local64_add(delta, &event->count);
}

static void msr_event_start(struct perf_event *event, int flags)
{
	u64 now;

	now = msr_read_counter(event);
	local64_set(&event->hw.prev_count, now);
}

static void msr_event_stop(struct perf_event *event, int flags)
{
	msr_event_update(event);
}

static void msr_event_del(struct perf_event *event, int flags)
{
	msr_event_stop(event, PERF_EF_UPDATE);
}

static int msr_event_add(struct perf_event *event, int flags)
{
	if (flags & PERF_EF_START)
		msr_event_start(event, flags);

	return 0;
}

static struct pmu pmu_msr = {
	.task_ctx_nr	= perf_sw_context,
	.attr_groups	= attr_groups,
	.event_init	= msr_event_init,
	.add		= msr_event_add,
	.del		= msr_event_del,
	.start		= msr_event_start,
	.stop		= msr_event_stop,
	.read		= msr_event_update,
	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
};

static int __init msr_init(void)
{
	int i, j = 0;

	if (!boot_cpu_has(X86_FEATURE_TSC)) {
		pr_cont("no MSR PMU driver.\n");
		return 0;
	}

	/* Probe the MSRs. */
	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
		u64 val;

		/*
		 * Virt sucks arse; you cannot tell if a R/O MSR is present :/
		 */
		if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
			msr[i].attr = NULL;
	}

	/* List remaining MSRs in the sysfs attrs. */
	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
		if (msr[i].attr)
			events_attrs[j++] = &msr[i].attr->attr.attr;
	}
	events_attrs[j] = NULL;

	perf_pmu_register(&pmu_msr, "msr", -1);

	return 0;
}
device_initcall(msr_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
b7b7c782	2	#include <linux/perf_event.h>
353bf605	3	#include <asm/intel-family.h>
b7b7c782 AL	4
	5	enum perf_msr_id {
	6	PERF_MSR_TSC = 0,
	7	PERF_MSR_APERF = 1,
	8	PERF_MSR_MPERF = 2,
	9	PERF_MSR_PPERF = 3,
	10	PERF_MSR_SMI = 4,
8a224261	11	PERF_MSR_PTSC = 5,
aaf24884	12	PERF_MSR_IRPERF = 6,
9ae21dd6 SE	13	PERF_MSR_THERM = 7,
	14	PERF_MSR_THERM_SNAP = 8,
	15	PERF_MSR_THERM_UNIT = 9,
b7b7c782 AL	16	PERF_MSR_EVENT_MAX,
	17	};
	18
7e5560a5	19	static bool test_aperfmperf(int idx)
19b3340c PZ	20	{
	21	return boot_cpu_has(X86_FEATURE_APERFMPERF);
	22	}
	23
8a224261 HR	24	static bool test_ptsc(int idx)
	25	{
	26	return boot_cpu_has(X86_FEATURE_PTSC);
	27	}
	28
aaf24884 HR	29	static bool test_irperf(int idx)
	30	{
	31	return boot_cpu_has(X86_FEATURE_IRPERF);
	32	}
	33
9ae21dd6 SE	34	static bool test_therm_status(int idx)
	35	{
	36	return boot_cpu_has(X86_FEATURE_DTHERM);
	37	}
	38
	39
7e5560a5	40	static bool test_intel(int idx)
19b3340c PZ	41	{
	42	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL \|\|
	43	boot_cpu_data.x86 != 6)
	44	return false;
	45
	46	switch (boot_cpu_data.x86_model) {
353bf605	47	case INTEL_FAM6_NEHALEM:
b325e04e	48	case INTEL_FAM6_NEHALEM_G:
353bf605 DH	49	case INTEL_FAM6_NEHALEM_EP:
353bf605 DH	50	case INTEL_FAM6_NEHALEM_EX:
19b3340c	51
353bf605 DH	52	case INTEL_FAM6_WESTMERE:
	53	case INTEL_FAM6_WESTMERE_EP:
	54	case INTEL_FAM6_WESTMERE_EX:
19b3340c	55
353bf605 DH	56	case INTEL_FAM6_SANDYBRIDGE:
353bf605 DH	57	case INTEL_FAM6_SANDYBRIDGE_X:
19b3340c	58
353bf605 DH	59	case INTEL_FAM6_IVYBRIDGE:
353bf605 DH	60	case INTEL_FAM6_IVYBRIDGE_X:
19b3340c	61
353bf605 DH	62	case INTEL_FAM6_HASWELL_CORE:
	63	case INTEL_FAM6_HASWELL_X:
	64	case INTEL_FAM6_HASWELL_ULT:
	65	case INTEL_FAM6_HASWELL_GT3E:
19b3340c	66
353bf605 DH	67	case INTEL_FAM6_BROADWELL_CORE:
	68	case INTEL_FAM6_BROADWELL_XEON_D:
	69	case INTEL_FAM6_BROADWELL_GT3E:
	70	case INTEL_FAM6_BROADWELL_X:
19b3340c	71
353bf605 DH	72	case INTEL_FAM6_ATOM_SILVERMONT1:
	73	case INTEL_FAM6_ATOM_SILVERMONT2:
	74	case INTEL_FAM6_ATOM_AIRMONT:
1aaccc40 KL	75
	76	case INTEL_FAM6_ATOM_GOLDMONT:
	77	case INTEL_FAM6_ATOM_DENVERTON:
	78
	79	case INTEL_FAM6_ATOM_GEMINI_LAKE:
	80
	81	case INTEL_FAM6_XEON_PHI_KNL:
	82	case INTEL_FAM6_XEON_PHI_KNM:
19b3340c PZ	83	if (idx == PERF_MSR_SMI)
	84	return true;
	85	break;
	86
353bf605 DH	87	case INTEL_FAM6_SKYLAKE_MOBILE:
353bf605 DH	88	case INTEL_FAM6_SKYLAKE_DESKTOP:
5134596c DH	89	case INTEL_FAM6_SKYLAKE_X:
	90	case INTEL_FAM6_KABYLAKE_MOBILE:
	91	case INTEL_FAM6_KABYLAKE_DESKTOP:
19b3340c PZ	92	if (idx == PERF_MSR_SMI \|\| idx == PERF_MSR_PPERF)
	93	return true;
	94	break;
	95	}
	96
	97	return false;
	98	}
	99
b7b7c782	100	struct perf_msr {
b7b7c782	101	u64 msr;
19b3340c PZ	102	struct perf_pmu_events_attr *attr;
19b3340c PZ	103	bool (*test)(int idx);
b7b7c782 AL	104	};
b7b7c782 AL	105
aaf24884 HR	106	PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00");
	107	PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
	108	PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
	109	PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
	110	PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04");
	111	PMU_EVENT_ATTR_STRING(ptsc, evattr_ptsc, "event=0x05");
	112	PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");
9ae21dd6 SE	113	PMU_EVENT_ATTR_STRING(cpu_thermal_margin, evattr_therm, "event=0x07");
	114	PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot, evattr_therm_snap, "1");
	115	PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit, evattr_therm_unit, "C");
b7b7c782	116
19b3340c	117	static struct perf_msr msr[] = {
aaf24884 HR	118	[PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, },
	119	[PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, },
	120	[PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, },
	121	[PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, },
	122	[PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, },
8a224261	123	[PERF_MSR_PTSC] = { MSR_F15H_PTSC, &evattr_ptsc, test_ptsc, },
aaf24884	124	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF, &evattr_irperf, test_irperf, },
9ae21dd6 SE	125	[PERF_MSR_THERM] = { MSR_IA32_THERM_STATUS, &evattr_therm, test_therm_status, },
	126	[PERF_MSR_THERM_SNAP] = { MSR_IA32_THERM_STATUS, &evattr_therm_snap, test_therm_status, },
	127	[PERF_MSR_THERM_UNIT] = { MSR_IA32_THERM_STATUS, &evattr_therm_unit, test_therm_status, },
19b3340c PZ	128	};
19b3340c PZ	129
b7b7c782	130	static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
19b3340c	131	NULL,
b7b7c782 AL	132	};
	133
	134	static struct attribute_group events_attr_group = {
	135	.name = "events",
	136	.attrs = events_attrs,
	137	};
	138
	139	PMU_FORMAT_ATTR(event, "config:0-63");
	140	static struct attribute *format_attrs[] = {
	141	&format_attr_event.attr,
	142	NULL,
	143	};
	144	static struct attribute_group format_attr_group = {
	145	.name = "format",
	146	.attrs = format_attrs,
	147	};
	148
	149	static const struct attribute_group *attr_groups[] = {
	150	&events_attr_group,
	151	&format_attr_group,
	152	NULL,
	153	};
	154
	155	static int msr_event_init(struct perf_event *event)
	156	{
	157	u64 cfg = event->attr.config;
	158
	159	if (event->attr.type != event->pmu->type)
	160	return -ENOENT;
	161
	162	if (cfg >= PERF_MSR_EVENT_MAX)
	163	return -EINVAL;
	164
	165	/* unsupported modes and filters */
	166	if (event->attr.exclude_user \|\|
	167	event->attr.exclude_kernel \|\|
	168	event->attr.exclude_hv \|\|
	169	event->attr.exclude_idle \|\|
	170	event->attr.exclude_host \|\|
	171	event->attr.exclude_guest \|\|
	172	event->attr.sample_period) /* no sampling */
	173	return -EINVAL;
	174
19b3340c PZ	175	if (!msr[cfg].attr)
	176	return -EINVAL;
	177
b7b7c782 AL	178	event->hw.idx = -1;
	179	event->hw.event_base = msr[cfg].msr;
	180	event->hw.config = cfg;
	181
	182	return 0;
	183	}
	184
	185	static inline u64 msr_read_counter(struct perf_event *event)
	186	{
	187	u64 now;
	188
	189	if (event->hw.event_base)
	190	rdmsrl(event->hw.event_base, now);
	191	else
82819ffb	192	rdtscll(now);
b7b7c782 AL	193
	194	return now;
	195	}
	196	static void msr_event_update(struct perf_event *event)
	197	{
	198	u64 prev, now;
	199	s64 delta;
	200
	201	/* Careful, an NMI might modify the previous event value. */
	202	again:
	203	prev = local64_read(&event->hw.prev_count);
	204	now = msr_read_counter(event);
	205
	206	if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
	207	goto again;
	208
	209	delta = now - prev;
9ae21dd6	210	if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
78e3c795	211	delta = sign_extend64(delta, 31);
9ae21dd6 SE	212	local64_add(delta, &event->count);
	213	} else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
	214	/* if valid, extract digital readout, other set to -1 */
	215	now = now & (1ULL << 31) ? (now >> 16) & 0x3f : -1;
	216	local64_set(&event->count, now);
	217	} else
	218	local64_add(delta, &event->count);
b7b7c782 AL	219	}
	220
	221	static void msr_event_start(struct perf_event *event, int flags)
	222	{
	223	u64 now;
	224
	225	now = msr_read_counter(event);
	226	local64_set(&event->hw.prev_count, now);
	227	}
	228
	229	static void msr_event_stop(struct perf_event *event, int flags)
	230	{
	231	msr_event_update(event);
	232	}
	233
	234	static void msr_event_del(struct perf_event *event, int flags)
	235	{
	236	msr_event_stop(event, PERF_EF_UPDATE);
	237	}
	238
	239	static int msr_event_add(struct perf_event *event, int flags)
	240	{
	241	if (flags & PERF_EF_START)
	242	msr_event_start(event, flags);
	243
	244	return 0;
	245	}
	246
	247	static struct pmu pmu_msr = {
	248	.task_ctx_nr = perf_sw_context,
	249	.attr_groups = attr_groups,
	250	.event_init = msr_event_init,
	251	.add = msr_event_add,
	252	.del = msr_event_del,
	253	.start = msr_event_start,
	254	.stop = msr_event_stop,
	255	.read = msr_event_update,
	256	.capabilities = PERF_PMU_CAP_NO_INTERRUPT,
	257	};
	258
b7b7c782 AL	259	static int __init msr_init(void)
b7b7c782 AL	260	{
19b3340c	261	int i, j = 0;
b7b7c782	262
19b3340c PZ	263	if (!boot_cpu_has(X86_FEATURE_TSC)) {
	264	pr_cont("no MSR PMU driver.\n");
	265	return 0;
b7b7c782 AL	266	}
b7b7c782 AL	267
19b3340c PZ	268	/* Probe the MSRs. */
	269	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
	270	u64 val;
b7b7c782	271
19b3340c PZ	272	/*
	273	* Virt sucks arse; you cannot tell if a R/O MSR is present :/
	274	*/
	275	if (!msr[i].test(i) \|\| rdmsrl_safe(msr[i].msr, &val))
	276	msr[i].attr = NULL;
b7b7c782 AL	277	}
b7b7c782 AL	278
19b3340c PZ	279	/* List remaining MSRs in the sysfs attrs. */
	280	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
	281	if (msr[i].attr)
	282	events_attrs[j++] = &msr[i].attr->attr.attr;
b7b7c782	283	}
19b3340c	284	events_attrs[j] = NULL;
b7b7c782 AL	285
	286	perf_pmu_register(&pmu_msr, "msr", -1);
	287
	288	return 0;
	289	}
	290	device_initcall(msr_init);