[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / amd_nb.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_AMD_NB_H
#define _ASM_X86_AMD_NB_H

#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/refcount.h>

struct amd_nb_bus_dev_range {
	u8 bus;
	u8 dev_base;
	u8 dev_limit;
};

extern const struct pci_device_id amd_nb_misc_ids[];
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];

extern bool early_is_amd_nb(u32 value);
extern struct resource *amd_get_mmconfig_range(struct resource *res);
extern int amd_cache_northbridges(void);
extern void amd_flush_garts(void);
extern int amd_numa_init(void);
extern int amd_get_subcaches(int);
extern int amd_set_subcaches(int, unsigned long);

extern int amd_smn_read(u16 node, u32 address, u32 *value);
extern int amd_smn_write(u16 node, u32 address, u32 value);
extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo);

struct amd_l3_cache {
	unsigned indices;
	u8	 subcaches[4];
};

struct threshold_block {
	unsigned int	 block;			/* Number within bank */
	unsigned int	 bank;			/* MCA bank the block belongs to */
	unsigned int	 cpu;			/* CPU which controls MCA bank */
	u32		 address;		/* MSR address for the block */
	u16		 interrupt_enable;	/* Enable/Disable APIC interrupt */
	bool		 interrupt_capable;	/* Bank can generate an interrupt. */

	u16		 threshold_limit;	/*
						 * Value upon which threshold
						 * interrupt is generated.
						 */

	struct kobject	 kobj;			/* sysfs object */
	struct list_head miscj;			/*
						 * List of threshold blocks
						 * within a bank.
						 */
};

struct threshold_bank {
	struct kobject		*kobj;
	struct threshold_block	*blocks;

	/* initialized to the number of CPUs on the node sharing this bank */
	refcount_t		cpus;
};

struct amd_northbridge {
	struct pci_dev *root;
	struct pci_dev *misc;
	struct pci_dev *link;
	struct amd_l3_cache l3_cache;
	struct threshold_bank *bank4;
};

struct amd_northbridge_info {
	u16 num;
	u64 flags;
	struct amd_northbridge *nb;
};

#define AMD_NB_GART			BIT(0)
#define AMD_NB_L3_INDEX_DISABLE		BIT(1)
#define AMD_NB_L3_PARTITIONING		BIT(2)

#ifdef CONFIG_AMD_NB

u16 amd_nb_num(void);
bool amd_nb_has_feature(unsigned int feature);
struct amd_northbridge *node_to_amd_nb(int node);

static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
{
	struct pci_dev *misc;
	int i;

	for (i = 0; i != amd_nb_num(); i++) {
		misc = node_to_amd_nb(i)->misc;

		if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
		    PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
			return i;
	}

	WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
	return 0;
}

static inline bool amd_gart_present(void)
{
	/* GART present only on Fam15h, upto model 0fh */
	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
	    (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
		return true;

	return false;
}

#else

#define amd_nb_num(x)		0
#define amd_nb_has_feature(x)	false
#define node_to_amd_nb(x)	NULL
#define amd_gart_present(x)	false

#endif


#endif /* _ASM_X86_AMD_NB_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
23ac4ae8 AH	2	#ifndef _ASM_X86_AMD_NB_H
23ac4ae8 AH	3	#define _ASM_X86_AMD_NB_H
a32073bf	4
24d25dbf	5	#include <linux/ioport.h>
a32073bf	6	#include <linux/pci.h>
473e90b2	7	#include <linux/refcount.h>
a32073bf	8
24d9b70b JB	9	struct amd_nb_bus_dev_range {
	10	u8 bus;
	11	u8 dev_base;
	12	u8 dev_limit;
	13	};
	14
691269f0	15	extern const struct pci_device_id amd_nb_misc_ids[];
24d9b70b	16	extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
a32073bf	17
84fd1d35	18	extern bool early_is_amd_nb(u32 value);
24d25dbf	19	extern struct resource amd_get_mmconfig_range(struct resource res);
9653a5c7	20	extern int amd_cache_northbridges(void);
eec1d4fa	21	extern void amd_flush_garts(void);
940fed2e	22	extern int amd_numa_init(void);
cabb5bd7	23	extern int amd_get_subcaches(int);
2993ae33	24	extern int amd_set_subcaches(int, unsigned long);
a32073bf	25
ddfe43cd YG	26	extern int amd_smn_read(u16 node, u32 address, u32 *value);
	27	extern int amd_smn_write(u16 node, u32 address, u32 value);
	28	extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo);
	29
d2946041 TG	30	struct amd_l3_cache {
	31	unsigned indices;
	32	u8 subcaches[4];
	33	};
	34
019f34fc	35	struct threshold_block {
ea2ca36b AG	36	unsigned int block; /* Number within bank */
	37	unsigned int bank; /* MCA bank the block belongs to */
	38	unsigned int cpu; /* CPU which controls MCA bank */
	39	u32 address; /* MSR address for the block */
	40	u16 interrupt_enable; /* Enable/Disable APIC interrupt */
	41	bool interrupt_capable; /* Bank can generate an interrupt. */
	42
	43	u16 threshold_limit; /*
	44	* Value upon which threshold
	45	* interrupt is generated.
	46	*/
	47
	48	struct kobject kobj; /* sysfs object */
	49	struct list_head miscj; /*
	50	* List of threshold blocks
	51	* within a bank.
	52	*/
019f34fc BP	53	};
	54
	55	struct threshold_bank {
	56	struct kobject *kobj;
	57	struct threshold_block *blocks;
	58
	59	/* initialized to the number of CPUs on the node sharing this bank */
473e90b2	60	refcount_t cpus;
019f34fc BP	61	};
019f34fc BP	62
9653a5c7	63	struct amd_northbridge {
ddfe43cd	64	struct pci_dev *root;
9653a5c7	65	struct pci_dev *misc;
41b2610c	66	struct pci_dev *link;
d2946041	67	struct amd_l3_cache l3_cache;
019f34fc	68	struct threshold_bank *bank4;
9653a5c7 HR	69	};
9653a5c7 HR	70
eec1d4fa	71	struct amd_northbridge_info {
900f9ac9	72	u16 num;
9653a5c7 HR	73	u64 flags;
9653a5c7 HR	74	struct amd_northbridge *nb;
900f9ac9	75	};
900f9ac9	76
84fd1d35 BP	77	#define AMD_NB_GART BIT(0)
	78	#define AMD_NB_L3_INDEX_DISABLE BIT(1)
	79	#define AMD_NB_L3_PARTITIONING BIT(2)
9653a5c7	80
23ac4ae8	81	#ifdef CONFIG_AMD_NB
ade029e2	82
c7993890 YG	83	u16 amd_nb_num(void);
	84	bool amd_nb_has_feature(unsigned int feature);
	85	struct amd_northbridge *node_to_amd_nb(int node);
9653a5c7	86
1a6775c1	87	static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
772c3ff3 DB	88	{
	89	struct pci_dev *misc;
	90	int i;
	91
	92	for (i = 0; i != amd_nb_num(); i++) {
	93	misc = node_to_amd_nb(i)->misc;
	94
	95	if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
	96	PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
	97	return i;
	98	}
	99
	100	WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
	101	return 0;
	102	}
	103
1b457429 AG	104	static inline bool amd_gart_present(void)
	105	{
	106	/* GART present only on Fam15h, upto model 0fh */
	107	if (boot_cpu_data.x86 == 0xf \|\| boot_cpu_data.x86 == 0x10 \|\|
	108	(boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
	109	return true;
	110
	111	return false;
	112	}
	113
9653a5c7 HR	114	#else
	115
	116	#define amd_nb_num(x) 0
	117	#define amd_nb_has_feature(x) false
	118	#define node_to_amd_nb(x) NULL
1b457429	119	#define amd_gart_present(x) false
9653a5c7	120
afd9fcee AH	121	#endif
	122
	123
23ac4ae8	124	#endif /* _ASM_X86_AMD_NB_H */