[mirror_ubuntu-zesty-kernel.git] / arch / x86 / include / asm / amd_nb.h

#ifndef _ASM_X86_AMD_NB_H
#define _ASM_X86_AMD_NB_H

#include <linux/ioport.h>
#include <linux/pci.h>

struct amd_nb_bus_dev_range {
	u8 bus;
	u8 dev_base;
	u8 dev_limit;
};

extern const struct pci_device_id amd_nb_misc_ids[];
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];

extern bool early_is_amd_nb(u32 value);
extern struct resource *amd_get_mmconfig_range(struct resource *res);
extern int amd_cache_northbridges(void);
extern void amd_flush_garts(void);
extern int amd_numa_init(void);
extern int amd_get_subcaches(int);
extern int amd_set_subcaches(int, unsigned long);

struct amd_l3_cache {
	unsigned indices;
	u8	 subcaches[4];
};

struct threshold_block {
	unsigned int		block;
	unsigned int		bank;
	unsigned int		cpu;
	u32			address;
	u16			interrupt_enable;
	bool			interrupt_capable;
	u16			threshold_limit;
	struct kobject		kobj;
	struct list_head	miscj;
};

struct threshold_bank {
	struct kobject		*kobj;
	struct threshold_block	*blocks;

	/* initialized to the number of CPUs on the node sharing this bank */
	atomic_t		cpus;
};

struct amd_northbridge {
	struct pci_dev *misc;
	struct pci_dev *link;
	struct amd_l3_cache l3_cache;
	struct threshold_bank *bank4;
};

struct amd_northbridge_info {
	u16 num;
	u64 flags;
	struct amd_northbridge *nb;
};
extern struct amd_northbridge_info amd_northbridges;

#define AMD_NB_GART			BIT(0)
#define AMD_NB_L3_INDEX_DISABLE		BIT(1)
#define AMD_NB_L3_PARTITIONING		BIT(2)

#ifdef CONFIG_AMD_NB

static inline u16 amd_nb_num(void)
{
	return amd_northbridges.num;
}

static inline bool amd_nb_has_feature(unsigned feature)
{
	return ((amd_northbridges.flags & feature) == feature);
}

static inline struct amd_northbridge *node_to_amd_nb(int node)
{
	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
}

static inline u16 amd_get_node_id(struct pci_dev *pdev)
{
	struct pci_dev *misc;
	int i;

	for (i = 0; i != amd_nb_num(); i++) {
		misc = node_to_amd_nb(i)->misc;

		if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
		    PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
			return i;
	}

	WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
	return 0;
}

#else

#define amd_nb_num(x)		0
#define amd_nb_has_feature(x)	false
#define node_to_amd_nb(x)	NULL

#endif


#endif /* _ASM_X86_AMD_NB_H */
Commit	Line	Data
23ac4ae8 AH	1	#ifndef _ASM_X86_AMD_NB_H
23ac4ae8 AH	2	#define _ASM_X86_AMD_NB_H
a32073bf	3
24d25dbf	4	#include <linux/ioport.h>
a32073bf AK	5	#include <linux/pci.h>
a32073bf AK	6
24d9b70b JB	7	struct amd_nb_bus_dev_range {
	8	u8 bus;
	9	u8 dev_base;
	10	u8 dev_limit;
	11	};
	12
691269f0	13	extern const struct pci_device_id amd_nb_misc_ids[];
24d9b70b	14	extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
a32073bf	15
84fd1d35	16	extern bool early_is_amd_nb(u32 value);
24d25dbf	17	extern struct resource amd_get_mmconfig_range(struct resource res);
9653a5c7	18	extern int amd_cache_northbridges(void);
eec1d4fa	19	extern void amd_flush_garts(void);
940fed2e	20	extern int amd_numa_init(void);
cabb5bd7	21	extern int amd_get_subcaches(int);
2993ae33	22	extern int amd_set_subcaches(int, unsigned long);
a32073bf	23
d2946041 TG	24	struct amd_l3_cache {
	25	unsigned indices;
	26	u8 subcaches[4];
	27	};
	28
019f34fc BP	29	struct threshold_block {
	30	unsigned int block;
	31	unsigned int bank;
	32	unsigned int cpu;
	33	u32 address;
	34	u16 interrupt_enable;
	35	bool interrupt_capable;
	36	u16 threshold_limit;
	37	struct kobject kobj;
	38	struct list_head miscj;
	39	};
	40
	41	struct threshold_bank {
	42	struct kobject *kobj;
	43	struct threshold_block *blocks;
	44
	45	/* initialized to the number of CPUs on the node sharing this bank */
	46	atomic_t cpus;
	47	};
	48
9653a5c7 HR	49	struct amd_northbridge {
9653a5c7 HR	50	struct pci_dev *misc;
41b2610c	51	struct pci_dev *link;
d2946041	52	struct amd_l3_cache l3_cache;
019f34fc	53	struct threshold_bank *bank4;
9653a5c7 HR	54	};
9653a5c7 HR	55
eec1d4fa	56	struct amd_northbridge_info {
900f9ac9	57	u16 num;
9653a5c7 HR	58	u64 flags;
9653a5c7 HR	59	struct amd_northbridge *nb;
900f9ac9	60	};
eec1d4fa	61	extern struct amd_northbridge_info amd_northbridges;
900f9ac9	62
84fd1d35 BP	63	#define AMD_NB_GART BIT(0)
	64	#define AMD_NB_L3_INDEX_DISABLE BIT(1)
	65	#define AMD_NB_L3_PARTITIONING BIT(2)
9653a5c7	66
23ac4ae8	67	#ifdef CONFIG_AMD_NB
ade029e2	68
84fd1d35	69	static inline u16 amd_nb_num(void)
b206525a	70	{
9653a5c7	71	return amd_northbridges.num;
b206525a	72	}
ade029e2	73
84fd1d35	74	static inline bool amd_nb_has_feature(unsigned feature)
9653a5c7 HR	75	{
	76	return ((amd_northbridges.flags & feature) == feature);
	77	}
ade029e2	78
9653a5c7	79	static inline struct amd_northbridge *node_to_amd_nb(int node)
b206525a	80	{
9653a5c7	81	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
b206525a	82	}
9653a5c7	83
772c3ff3 DB	84	static inline u16 amd_get_node_id(struct pci_dev *pdev)
	85	{
	86	struct pci_dev *misc;
	87	int i;
	88
	89	for (i = 0; i != amd_nb_num(); i++) {
	90	misc = node_to_amd_nb(i)->misc;
	91
	92	if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
	93	PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
	94	return i;
	95	}
	96
	97	WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
	98	return 0;
	99	}
	100
9653a5c7 HR	101	#else
	102
	103	#define amd_nb_num(x) 0
	104	#define amd_nb_has_feature(x) false
	105	#define node_to_amd_nb(x) NULL
	106
afd9fcee AH	107	#endif
	108
	109
23ac4ae8	110	#endif /* _ASM_X86_AMD_NB_H */