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1 | /* |
2 | * apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare | |
3 | * | |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * Note: | |
13 | */ | |
14 | ||
15 | #ifndef ASM_X86_APBT_H | |
16 | #define ASM_X86_APBT_H | |
17 | #include <linux/sfi.h> | |
18 | ||
19 | #ifdef CONFIG_APB_TIMER | |
20 | ||
21 | /* Langwell DW APB timer registers */ | |
22 | #define APBTMR_N_LOAD_COUNT 0x00 | |
23 | #define APBTMR_N_CURRENT_VALUE 0x04 | |
24 | #define APBTMR_N_CONTROL 0x08 | |
25 | #define APBTMR_N_EOI 0x0c | |
26 | #define APBTMR_N_INT_STATUS 0x10 | |
27 | ||
28 | #define APBTMRS_INT_STATUS 0xa0 | |
29 | #define APBTMRS_EOI 0xa4 | |
30 | #define APBTMRS_RAW_INT_STATUS 0xa8 | |
31 | #define APBTMRS_COMP_VERSION 0xac | |
32 | #define APBTMRS_REG_SIZE 0x14 | |
33 | ||
34 | /* register bits */ | |
35 | #define APBTMR_CONTROL_ENABLE (1<<0) | |
36 | #define APBTMR_CONTROL_MODE_PERIODIC (1<<1) /*1: periodic 0:free running */ | |
37 | #define APBTMR_CONTROL_INT (1<<2) | |
38 | ||
39 | /* default memory mapped register base */ | |
40 | #define LNW_SCU_ADDR 0xFF100000 | |
41 | #define LNW_EXT_TIMER_OFFSET 0x1B800 | |
42 | #define APBT_DEFAULT_BASE (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET) | |
43 | #define LNW_EXT_TIMER_PGOFFSET 0x800 | |
44 | ||
45 | /* APBT clock speed range from PCLK to fabric base, 25-100MHz */ | |
46 | #define APBT_MAX_FREQ 50 | |
47 | #define APBT_MIN_FREQ 1 | |
48 | #define APBT_MMAP_SIZE 1024 | |
49 | ||
50 | #define APBT_DEV_USED 1 | |
51 | ||
52 | extern void apbt_time_init(void); | |
53 | extern struct clock_event_device *global_clock_event; | |
54 | extern unsigned long apbt_quick_calibrate(void); | |
55 | extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu); | |
56 | extern void apbt_setup_secondary_clock(void); | |
bb24c471 JP |
57 | |
58 | extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); | |
59 | extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr); | |
60 | extern int sfi_mtimer_num; | |
61 | ||
62 | #else /* CONFIG_APB_TIMER */ | |
63 | ||
64 | static inline unsigned long apbt_quick_calibrate(void) {return 0; } | |
65 | static inline void apbt_time_init(void) {return 0; } | |
66 | ||
67 | #endif | |
68 | #endif /* ASM_X86_APBT_H */ |