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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c | 3 | |
e2780a68 | 4 | #include <linux/cpumask.h> |
593f4a78 MR |
5 | |
6 | #include <asm/alternative.h> | |
e2780a68 | 7 | #include <asm/cpufeature.h> |
e2780a68 | 8 | #include <asm/apicdef.h> |
60063497 | 9 | #include <linux/atomic.h> |
e2780a68 IM |
10 | #include <asm/fixmap.h> |
11 | #include <asm/mpspec.h> | |
13c88fb5 | 12 | #include <asm/msr.h> |
67c5fc5c TG |
13 | |
14 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
15 | ||
67c5fc5c TG |
16 | /* |
17 | * Debugging macros | |
18 | */ | |
19 | #define APIC_QUIET 0 | |
20 | #define APIC_VERBOSE 1 | |
21 | #define APIC_DEBUG 2 | |
22 | ||
b7c4948e HK |
23 | /* Macros for apic_extnmi which controls external NMI masking */ |
24 | #define APIC_EXTNMI_BSP 0 /* Default */ | |
25 | #define APIC_EXTNMI_ALL 1 | |
26 | #define APIC_EXTNMI_NONE 2 | |
27 | ||
67c5fc5c TG |
28 | /* |
29 | * Define the default level of output to be very little | |
30 | * This can be turned up by using apic=verbose for more | |
31 | * information and apic=debug for _lots_ of information. | |
32 | * apic_verbosity is defined in apic.c | |
33 | */ | |
34 | #define apic_printk(v, s, a...) do { \ | |
35 | if ((v) <= apic_verbosity) \ | |
36 | printk(s, ##a); \ | |
37 | } while (0) | |
38 | ||
39 | ||
160d8dac | 40 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
67c5fc5c | 41 | extern void generic_apic_probe(void); |
160d8dac IM |
42 | #else |
43 | static inline void generic_apic_probe(void) | |
44 | { | |
45 | } | |
46 | #endif | |
67c5fc5c TG |
47 | |
48 | #ifdef CONFIG_X86_LOCAL_APIC | |
49 | ||
baa13188 | 50 | extern unsigned int apic_verbosity; |
67c5fc5c | 51 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 52 | |
3c999f14 | 53 | extern int disable_apic; |
1ade93ef | 54 | extern unsigned int lapic_timer_frequency; |
0939e4fd IM |
55 | |
56 | #ifdef CONFIG_SMP | |
57 | extern void __inquire_remote_apic(int apicid); | |
58 | #else /* CONFIG_SMP */ | |
59 | static inline void __inquire_remote_apic(int apicid) | |
60 | { | |
61 | } | |
62 | #endif /* CONFIG_SMP */ | |
63 | ||
64 | static inline void default_inquire_remote_apic(int apicid) | |
65 | { | |
66 | if (apic_verbosity >= APIC_DEBUG) | |
67 | __inquire_remote_apic(apicid); | |
68 | } | |
69 | ||
8312136f CG |
70 | /* |
71 | * With 82489DX we can't rely on apic feature bit | |
72 | * retrieved via cpuid but still have to deal with | |
73 | * such an apic chip so we assume that SMP configuration | |
74 | * is found from MP table (64bit case uses ACPI mostly | |
75 | * which set smp presence flag as well so we are safe | |
76 | * to use this helper too). | |
77 | */ | |
78 | static inline bool apic_from_smp_config(void) | |
79 | { | |
80 | return smp_found_config && !disable_apic; | |
81 | } | |
82 | ||
67c5fc5c TG |
83 | /* |
84 | * Basic functions accessing APICs. | |
85 | */ | |
86 | #ifdef CONFIG_PARAVIRT | |
87 | #include <asm/paravirt.h> | |
96a388de | 88 | #endif |
67c5fc5c | 89 | |
2b97df06 | 90 | extern int setup_profiling_timer(unsigned int); |
aa7d8e25 | 91 | |
1b374e4d | 92 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 93 | { |
593f4a78 | 94 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 95 | |
a930dc45 | 96 | alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, |
593f4a78 MR |
97 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), |
98 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
99 | } |
100 | ||
1b374e4d | 101 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
102 | { |
103 | return *((volatile u32 *)(APIC_BASE + reg)); | |
104 | } | |
105 | ||
c1eeb2de YL |
106 | extern void native_apic_wait_icr_idle(void); |
107 | extern u32 native_safe_apic_wait_icr_idle(void); | |
108 | extern void native_apic_icr_write(u32 low, u32 id); | |
109 | extern u64 native_apic_icr_read(void); | |
110 | ||
8d806960 TG |
111 | static inline bool apic_is_x2apic_enabled(void) |
112 | { | |
113 | u64 msr; | |
114 | ||
115 | if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) | |
116 | return false; | |
117 | return msr & X2APIC_ENABLE; | |
118 | } | |
119 | ||
e02ae387 PB |
120 | extern void enable_IR_x2apic(void); |
121 | ||
122 | extern int get_physical_broadcast(void); | |
123 | ||
124 | extern int lapic_get_maxlvt(void); | |
125 | extern void clear_local_APIC(void); | |
126 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
127 | extern void disable_local_APIC(void); | |
128 | extern void lapic_shutdown(void); | |
129 | extern void sync_Arb_IDs(void); | |
130 | extern void init_bsp_APIC(void); | |
131 | extern void setup_local_APIC(void); | |
132 | extern void init_apic_mappings(void); | |
133 | void register_lapic_address(unsigned long address); | |
134 | extern void setup_boot_APIC_clock(void); | |
135 | extern void setup_secondary_APIC_clock(void); | |
6731b0d6 | 136 | extern void lapic_update_tsc_freq(void); |
e02ae387 PB |
137 | extern int APIC_init_uniprocessor(void); |
138 | ||
139 | #ifdef CONFIG_X86_64 | |
140 | static inline int apic_force_enable(unsigned long addr) | |
141 | { | |
142 | return -1; | |
143 | } | |
144 | #else | |
145 | extern int apic_force_enable(unsigned long addr); | |
146 | #endif | |
147 | ||
148 | extern int apic_bsp_setup(bool upmode); | |
149 | extern void apic_ap_setup(void); | |
150 | ||
151 | /* | |
152 | * On 32bit this is mach-xxx local | |
153 | */ | |
154 | #ifdef CONFIG_X86_64 | |
155 | extern int apic_is_clustered_box(void); | |
156 | #else | |
157 | static inline int apic_is_clustered_box(void) | |
158 | { | |
159 | return 0; | |
160 | } | |
161 | #endif | |
162 | ||
163 | extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); | |
164 | ||
165 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
166 | static inline void lapic_shutdown(void) { } | |
167 | #define local_apic_timer_c2_ok 1 | |
168 | static inline void init_apic_mappings(void) { } | |
169 | static inline void disable_local_APIC(void) { } | |
170 | # define setup_boot_APIC_clock x86_init_noop | |
171 | # define setup_secondary_APIC_clock x86_init_noop | |
6731b0d6 | 172 | static inline void lapic_update_tsc_freq(void) { } |
e02ae387 PB |
173 | #endif /* !CONFIG_X86_LOCAL_APIC */ |
174 | ||
d0b03bd1 | 175 | #ifdef CONFIG_X86_X2APIC |
ce4e240c SS |
176 | /* |
177 | * Make previous memory operations globally visible before | |
178 | * sending the IPI through x2apic wrmsr. We need a serializing instruction or | |
179 | * mfence for this. | |
180 | */ | |
181 | static inline void x2apic_wrmsr_fence(void) | |
182 | { | |
183 | asm volatile("mfence" : : : "memory"); | |
184 | } | |
185 | ||
13c88fb5 SS |
186 | static inline void native_apic_msr_write(u32 reg, u32 v) |
187 | { | |
188 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
189 | reg == APIC_LVR) | |
190 | return; | |
191 | ||
192 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
193 | } | |
194 | ||
0ab711ae MT |
195 | static inline void native_apic_msr_eoi_write(u32 reg, u32 v) |
196 | { | |
a585df8e | 197 | __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); |
0ab711ae MT |
198 | } |
199 | ||
13c88fb5 SS |
200 | static inline u32 native_apic_msr_read(u32 reg) |
201 | { | |
0059b243 | 202 | u64 msr; |
13c88fb5 SS |
203 | |
204 | if (reg == APIC_DFR) | |
205 | return -1; | |
206 | ||
0059b243 AK |
207 | rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); |
208 | return (u32)msr; | |
13c88fb5 SS |
209 | } |
210 | ||
c1eeb2de YL |
211 | static inline void native_x2apic_wait_icr_idle(void) |
212 | { | |
213 | /* no need to wait for icr idle in x2apic */ | |
214 | return; | |
215 | } | |
216 | ||
217 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
218 | { | |
219 | /* no need to wait for icr idle in x2apic */ | |
220 | return 0; | |
221 | } | |
222 | ||
223 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
224 | { | |
225 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
226 | } | |
227 | ||
228 | static inline u64 native_x2apic_icr_read(void) | |
229 | { | |
230 | unsigned long val; | |
231 | ||
232 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
233 | return val; | |
234 | } | |
235 | ||
81a46dd8 | 236 | extern int x2apic_mode; |
fc1edaf9 | 237 | extern int x2apic_phys; |
d524165c | 238 | extern void __init check_x2apic(void); |
659006bf | 239 | extern void x2apic_setup(void); |
a11b5abe YL |
240 | static inline int x2apic_enabled(void) |
241 | { | |
62436a4d | 242 | return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); |
a11b5abe | 243 | } |
fc1edaf9 | 244 | |
62436a4d | 245 | #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) |
e02ae387 | 246 | #else /* !CONFIG_X86_X2APIC */ |
55eae7de | 247 | static inline void check_x2apic(void) { } |
659006bf | 248 | static inline void x2apic_setup(void) { } |
55eae7de | 249 | static inline int x2apic_enabled(void) { return 0; } |
cf6567fe | 250 | |
81a46dd8 | 251 | #define x2apic_mode (0) |
81a46dd8 | 252 | #define x2apic_supported() (0) |
e02ae387 | 253 | #endif /* !CONFIG_X86_X2APIC */ |
67c5fc5c | 254 | |
0e24f7c9 TG |
255 | struct irq_data; |
256 | ||
e2780a68 IM |
257 | /* |
258 | * Copyright 2004 James Cleverdon, IBM. | |
259 | * Subject to the GNU Public License, v.2 | |
260 | * | |
261 | * Generic APIC sub-arch data struct. | |
262 | * | |
263 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
264 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
265 | * James Cleverdon. | |
266 | */ | |
be163a15 | 267 | struct apic { |
e2780a68 IM |
268 | char *name; |
269 | ||
270 | int (*probe)(void); | |
271 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
fa63030e | 272 | int (*apic_id_valid)(int apicid); |
e2780a68 IM |
273 | int (*apic_id_registered)(void); |
274 | ||
275 | u32 irq_delivery_mode; | |
276 | u32 irq_dest_mode; | |
277 | ||
278 | const struct cpumask *(*target_cpus)(void); | |
279 | ||
280 | int disable_esr; | |
281 | ||
282 | int dest_logical; | |
7abc0753 | 283 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); |
e2780a68 | 284 | |
1ac322d0 SS |
285 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, |
286 | const struct cpumask *mask); | |
e2780a68 IM |
287 | void (*init_apic_ldr)(void); |
288 | ||
7abc0753 | 289 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); |
e2780a68 IM |
290 | |
291 | void (*setup_apic_routing)(void); | |
e2780a68 | 292 | int (*cpu_present_to_apicid)(int mps_cpu); |
7abc0753 | 293 | void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); |
e11dadab | 294 | int (*check_phys_apicid_present)(int phys_apicid); |
e2780a68 IM |
295 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); |
296 | ||
e2780a68 | 297 | unsigned int (*get_apic_id)(unsigned long x); |
5d64d209 | 298 | /* Can't be NULL on 64-bit */ |
e2780a68 | 299 | unsigned long (*set_apic_id)(unsigned int id); |
e2780a68 | 300 | |
91cd9cb7 | 301 | int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, |
0e24f7c9 | 302 | struct irq_data *irqdata, |
91cd9cb7 | 303 | unsigned int *apicid); |
e2780a68 IM |
304 | |
305 | /* ipi */ | |
539da787 | 306 | void (*send_IPI)(int cpu, int vector); |
e2780a68 IM |
307 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); |
308 | void (*send_IPI_mask_allbutself)(const struct cpumask *mask, | |
309 | int vector); | |
310 | void (*send_IPI_allbutself)(int vector); | |
311 | void (*send_IPI_all)(int vector); | |
312 | void (*send_IPI_self)(int vector); | |
313 | ||
314 | /* wakeup_secondary_cpu */ | |
1f5bcabf | 315 | int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); |
e2780a68 | 316 | |
e2780a68 IM |
317 | void (*inquire_remote_apic)(int apicid); |
318 | ||
319 | /* apic ops */ | |
320 | u32 (*read)(u32 reg); | |
321 | void (*write)(u32 reg, u32 v); | |
2a43195d MT |
322 | /* |
323 | * ->eoi_write() has the same signature as ->write(). | |
324 | * | |
325 | * Drivers can support both ->eoi_write() and ->write() by passing the same | |
326 | * callback value. Kernel can override ->eoi_write() and fall back | |
327 | * on write for EOI. | |
328 | */ | |
329 | void (*eoi_write)(u32 reg, u32 v); | |
8ca22552 | 330 | void (*native_eoi_write)(u32 reg, u32 v); |
e2780a68 IM |
331 | u64 (*icr_read)(void); |
332 | void (*icr_write)(u32 low, u32 high); | |
333 | void (*wait_icr_idle)(void); | |
334 | u32 (*safe_wait_icr_idle)(void); | |
acb8bc09 TH |
335 | |
336 | #ifdef CONFIG_X86_32 | |
337 | /* | |
338 | * Called very early during boot from get_smp_config(). It should | |
339 | * return the logical apicid. x86_[bios]_cpu_to_apicid is | |
340 | * initialized before this function is called. | |
341 | * | |
342 | * If logical apicid can't be determined that early, the function | |
343 | * may return BAD_APICID. Logical apicid will be configured after | |
344 | * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity | |
345 | * won't be applied properly during early boot in this case. | |
346 | */ | |
347 | int (*x86_32_early_logical_apicid)(int cpu); | |
348 | #endif | |
e2780a68 IM |
349 | }; |
350 | ||
0917c01f IM |
351 | /* |
352 | * Pointer to the local APIC driver in use on this system (there's | |
353 | * always just one such driver in use - the kernel decides via an | |
354 | * early probing process which one it picks - and then sticks to it): | |
355 | */ | |
be163a15 | 356 | extern struct apic *apic; |
0917c01f | 357 | |
107e0e0c SS |
358 | /* |
359 | * APIC drivers are probed based on how they are listed in the .apicdrivers | |
360 | * section. So the order is important and enforced by the ordering | |
361 | * of different apic driver files in the Makefile. | |
362 | * | |
363 | * For the files having two apic drivers, we use apic_drivers() | |
364 | * to enforce the order with in them. | |
365 | */ | |
366 | #define apic_driver(sym) \ | |
75fdd155 | 367 | static const struct apic *__apicdrivers_##sym __used \ |
107e0e0c SS |
368 | __aligned(sizeof(struct apic *)) \ |
369 | __section(.apicdrivers) = { &sym } | |
370 | ||
371 | #define apic_drivers(sym1, sym2) \ | |
372 | static struct apic *__apicdrivers_##sym1##sym2[2] __used \ | |
373 | __aligned(sizeof(struct apic *)) \ | |
374 | __section(.apicdrivers) = { &sym1, &sym2 } | |
375 | ||
376 | extern struct apic *__apicdrivers[], *__apicdrivers_end[]; | |
377 | ||
0917c01f IM |
378 | /* |
379 | * APIC functionality to boot other CPUs - only used on SMP: | |
380 | */ | |
381 | #ifdef CONFIG_SMP | |
2b6163bf | 382 | extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); |
0917c01f | 383 | #endif |
e2780a68 | 384 | |
d674cd19 | 385 | #ifdef CONFIG_X86_LOCAL_APIC |
346b46be | 386 | |
e2780a68 IM |
387 | static inline u32 apic_read(u32 reg) |
388 | { | |
389 | return apic->read(reg); | |
390 | } | |
391 | ||
392 | static inline void apic_write(u32 reg, u32 val) | |
393 | { | |
394 | apic->write(reg, val); | |
395 | } | |
396 | ||
2a43195d MT |
397 | static inline void apic_eoi(void) |
398 | { | |
399 | apic->eoi_write(APIC_EOI, APIC_EOI_ACK); | |
400 | } | |
401 | ||
e2780a68 IM |
402 | static inline u64 apic_icr_read(void) |
403 | { | |
404 | return apic->icr_read(); | |
405 | } | |
406 | ||
407 | static inline void apic_icr_write(u32 low, u32 high) | |
408 | { | |
409 | apic->icr_write(low, high); | |
410 | } | |
411 | ||
412 | static inline void apic_wait_icr_idle(void) | |
413 | { | |
414 | apic->wait_icr_idle(); | |
415 | } | |
416 | ||
417 | static inline u32 safe_apic_wait_icr_idle(void) | |
418 | { | |
419 | return apic->safe_wait_icr_idle(); | |
420 | } | |
421 | ||
1551df64 MT |
422 | extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); |
423 | ||
d674cd19 CG |
424 | #else /* CONFIG_X86_LOCAL_APIC */ |
425 | ||
426 | static inline u32 apic_read(u32 reg) { return 0; } | |
427 | static inline void apic_write(u32 reg, u32 val) { } | |
2a43195d | 428 | static inline void apic_eoi(void) { } |
d674cd19 CG |
429 | static inline u64 apic_icr_read(void) { return 0; } |
430 | static inline void apic_icr_write(u32 low, u32 high) { } | |
431 | static inline void apic_wait_icr_idle(void) { } | |
432 | static inline u32 safe_apic_wait_icr_idle(void) { return 0; } | |
1551df64 | 433 | static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} |
d674cd19 CG |
434 | |
435 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
e2780a68 IM |
436 | |
437 | static inline void ack_APIC_irq(void) | |
438 | { | |
439 | /* | |
440 | * ack_APIC_irq() actually gets compiled as a single instruction | |
441 | * ... yummie. | |
442 | */ | |
2a43195d | 443 | apic_eoi(); |
e2780a68 IM |
444 | } |
445 | ||
446 | static inline unsigned default_get_apic_id(unsigned long x) | |
447 | { | |
448 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
449 | ||
42937e81 | 450 | if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) |
e2780a68 IM |
451 | return (x >> 24) & 0xFF; |
452 | else | |
453 | return (x >> 24) & 0x0F; | |
454 | } | |
455 | ||
456 | /* | |
6ab1b27c | 457 | * Warm reset vector position: |
e2780a68 | 458 | */ |
6ab1b27c DR |
459 | #define TRAMPOLINE_PHYS_LOW 0x467 |
460 | #define TRAMPOLINE_PHYS_HIGH 0x469 | |
e2780a68 | 461 | |
2b6163bf | 462 | #ifdef CONFIG_X86_64 |
e2780a68 IM |
463 | extern void apic_send_IPI_self(int vector); |
464 | ||
e2780a68 IM |
465 | DECLARE_PER_CPU(int, x2apic_extra_bits); |
466 | ||
467 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 468 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
469 | #endif |
470 | ||
838312be | 471 | extern void generic_bigsmp_probe(void); |
e2780a68 IM |
472 | |
473 | ||
474 | #ifdef CONFIG_X86_LOCAL_APIC | |
475 | ||
476 | #include <asm/smp.h> | |
477 | ||
478 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
479 | ||
480 | static inline const struct cpumask *default_target_cpus(void) | |
481 | { | |
482 | #ifdef CONFIG_SMP | |
483 | return cpu_online_mask; | |
484 | #else | |
485 | return cpumask_of(0); | |
486 | #endif | |
487 | } | |
488 | ||
bf721d3a AG |
489 | static inline const struct cpumask *online_target_cpus(void) |
490 | { | |
491 | return cpu_online_mask; | |
492 | } | |
493 | ||
0816b0f0 | 494 | DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); |
e2780a68 IM |
495 | |
496 | ||
497 | static inline unsigned int read_apic_id(void) | |
498 | { | |
499 | unsigned int reg; | |
500 | ||
501 | reg = apic_read(APIC_ID); | |
502 | ||
503 | return apic->get_apic_id(reg); | |
504 | } | |
505 | ||
fa63030e DB |
506 | static inline int default_apic_id_valid(int apicid) |
507 | { | |
b7157acf | 508 | return (apicid < 255); |
fa63030e DB |
509 | } |
510 | ||
a491cc90 JL |
511 | extern int default_acpi_madt_oem_check(char *, char *); |
512 | ||
e2780a68 IM |
513 | extern void default_setup_apic_routing(void); |
514 | ||
9844ab11 CG |
515 | extern struct apic apic_noop; |
516 | ||
e2780a68 | 517 | #ifdef CONFIG_X86_32 |
2c1b284e | 518 | |
acb8bc09 TH |
519 | static inline int noop_x86_32_early_logical_apicid(int cpu) |
520 | { | |
521 | return BAD_APICID; | |
522 | } | |
523 | ||
e2780a68 IM |
524 | /* |
525 | * Set up the logical destination ID. | |
526 | * | |
527 | * Intel recommends to set DFR, LDR and TPR before enabling | |
528 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
529 | * document number 292116). So here it goes... | |
530 | */ | |
531 | extern void default_init_apic_ldr(void); | |
532 | ||
533 | static inline int default_apic_id_registered(void) | |
534 | { | |
535 | return physid_isset(read_apic_id(), phys_cpu_present_map); | |
536 | } | |
537 | ||
f56e5034 YL |
538 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) |
539 | { | |
540 | return cpuid_apic >> index_msb; | |
541 | } | |
542 | ||
f56e5034 YL |
543 | #endif |
544 | ||
91cd9cb7 | 545 | extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, |
0e24f7c9 | 546 | struct irq_data *irqdata, |
91cd9cb7 TG |
547 | unsigned int *apicid); |
548 | extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, | |
0e24f7c9 | 549 | struct irq_data *irqdata, |
91cd9cb7 | 550 | unsigned int *apicid); |
6398268d | 551 | |
b39f25a8 | 552 | static inline void |
1ac322d0 SS |
553 | flat_vector_allocation_domain(int cpu, struct cpumask *retmask, |
554 | const struct cpumask *mask) | |
9d8e1066 AG |
555 | { |
556 | /* Careful. Some cpus do not strictly honor the set of cpus | |
557 | * specified in the interrupt destination when using lowest | |
558 | * priority interrupt delivery mode. | |
559 | * | |
560 | * In particular there was a hyperthreading cpu observed to | |
561 | * deliver interrupts to the wrong hyperthread when only one | |
562 | * hyperthread was specified in the interrupt desitination. | |
563 | */ | |
564 | cpumask_clear(retmask); | |
565 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | |
566 | } | |
567 | ||
b39f25a8 | 568 | static inline void |
1ac322d0 SS |
569 | default_vector_allocation_domain(int cpu, struct cpumask *retmask, |
570 | const struct cpumask *mask) | |
9d8e1066 AG |
571 | { |
572 | cpumask_copy(retmask, cpumask_of(cpu)); | |
573 | } | |
574 | ||
7abc0753 | 575 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) |
e2780a68 | 576 | { |
7abc0753 | 577 | return physid_isset(apicid, *map); |
e2780a68 IM |
578 | } |
579 | ||
7abc0753 | 580 | static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) |
e2780a68 | 581 | { |
7abc0753 | 582 | *retmap = *phys_map; |
e2780a68 IM |
583 | } |
584 | ||
e2780a68 IM |
585 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
586 | { | |
587 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | |
588 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
589 | else | |
590 | return BAD_APICID; | |
591 | } | |
592 | ||
593 | static inline int | |
e11dadab | 594 | __default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 595 | { |
e11dadab | 596 | return physid_isset(phys_apicid, phys_cpu_present_map); |
e2780a68 IM |
597 | } |
598 | ||
599 | #ifdef CONFIG_X86_32 | |
600 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
601 | { | |
602 | return __default_cpu_present_to_apicid(mps_cpu); | |
603 | } | |
604 | ||
605 | static inline int | |
e11dadab | 606 | default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 607 | { |
e11dadab | 608 | return __default_check_phys_apicid_present(phys_apicid); |
e2780a68 IM |
609 | } |
610 | #else | |
611 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 612 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
613 | #endif |
614 | ||
e2780a68 | 615 | #endif /* CONFIG_X86_LOCAL_APIC */ |
eddc0e92 SA |
616 | extern void irq_enter(void); |
617 | extern void irq_exit(void); | |
618 | ||
619 | static inline void entering_irq(void) | |
620 | { | |
621 | irq_enter(); | |
eddc0e92 SA |
622 | } |
623 | ||
624 | static inline void entering_ack_irq(void) | |
625 | { | |
eddc0e92 | 626 | entering_irq(); |
7834c103 | 627 | ack_APIC_irq(); |
eddc0e92 SA |
628 | } |
629 | ||
6dc17876 TG |
630 | static inline void ipi_entering_ack_irq(void) |
631 | { | |
6dc17876 | 632 | irq_enter(); |
b0f48706 | 633 | ack_APIC_irq(); |
6dc17876 TG |
634 | } |
635 | ||
eddc0e92 SA |
636 | static inline void exiting_irq(void) |
637 | { | |
638 | irq_exit(); | |
639 | } | |
640 | ||
641 | static inline void exiting_ack_irq(void) | |
642 | { | |
eddc0e92 | 643 | ack_APIC_irq(); |
b0f48706 | 644 | irq_exit(); |
eddc0e92 | 645 | } |
e2780a68 | 646 | |
17405453 YY |
647 | extern void ioapic_zap_locks(void); |
648 | ||
1965aae3 | 649 | #endif /* _ASM_X86_APIC_H */ |