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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c | 3 | |
e2780a68 | 4 | #include <linux/cpumask.h> |
593f4a78 MR |
5 | |
6 | #include <asm/alternative.h> | |
e2780a68 | 7 | #include <asm/cpufeature.h> |
e2780a68 | 8 | #include <asm/apicdef.h> |
60063497 | 9 | #include <linux/atomic.h> |
e2780a68 IM |
10 | #include <asm/fixmap.h> |
11 | #include <asm/mpspec.h> | |
13c88fb5 | 12 | #include <asm/msr.h> |
9dcfef9f | 13 | #include <asm/hardirq.h> |
67c5fc5c TG |
14 | |
15 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
16 | ||
67c5fc5c TG |
17 | /* |
18 | * Debugging macros | |
19 | */ | |
20 | #define APIC_QUIET 0 | |
21 | #define APIC_VERBOSE 1 | |
22 | #define APIC_DEBUG 2 | |
23 | ||
b7c4948e HK |
24 | /* Macros for apic_extnmi which controls external NMI masking */ |
25 | #define APIC_EXTNMI_BSP 0 /* Default */ | |
26 | #define APIC_EXTNMI_ALL 1 | |
27 | #define APIC_EXTNMI_NONE 2 | |
28 | ||
67c5fc5c TG |
29 | /* |
30 | * Define the default level of output to be very little | |
31 | * This can be turned up by using apic=verbose for more | |
32 | * information and apic=debug for _lots_ of information. | |
33 | * apic_verbosity is defined in apic.c | |
34 | */ | |
35 | #define apic_printk(v, s, a...) do { \ | |
36 | if ((v) <= apic_verbosity) \ | |
37 | printk(s, ##a); \ | |
38 | } while (0) | |
39 | ||
40 | ||
160d8dac | 41 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
67c5fc5c | 42 | extern void generic_apic_probe(void); |
160d8dac IM |
43 | #else |
44 | static inline void generic_apic_probe(void) | |
45 | { | |
46 | } | |
47 | #endif | |
67c5fc5c TG |
48 | |
49 | #ifdef CONFIG_X86_LOCAL_APIC | |
50 | ||
3c40398b | 51 | extern int apic_verbosity; |
67c5fc5c | 52 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 53 | |
3c999f14 | 54 | extern int disable_apic; |
1ade93ef | 55 | extern unsigned int lapic_timer_frequency; |
0939e4fd | 56 | |
4f45ed9f DL |
57 | extern enum apic_intr_mode_id apic_intr_mode; |
58 | enum apic_intr_mode_id { | |
59 | APIC_PIC, | |
60 | APIC_VIRTUAL_WIRE, | |
61 | APIC_VIRTUAL_WIRE_NO_CONFIG, | |
62 | APIC_SYMMETRIC_IO, | |
63 | APIC_SYMMETRIC_IO_NO_ROUTING | |
64 | }; | |
65 | ||
0939e4fd IM |
66 | #ifdef CONFIG_SMP |
67 | extern void __inquire_remote_apic(int apicid); | |
68 | #else /* CONFIG_SMP */ | |
69 | static inline void __inquire_remote_apic(int apicid) | |
70 | { | |
71 | } | |
72 | #endif /* CONFIG_SMP */ | |
73 | ||
74 | static inline void default_inquire_remote_apic(int apicid) | |
75 | { | |
76 | if (apic_verbosity >= APIC_DEBUG) | |
77 | __inquire_remote_apic(apicid); | |
78 | } | |
79 | ||
8312136f CG |
80 | /* |
81 | * With 82489DX we can't rely on apic feature bit | |
82 | * retrieved via cpuid but still have to deal with | |
83 | * such an apic chip so we assume that SMP configuration | |
84 | * is found from MP table (64bit case uses ACPI mostly | |
85 | * which set smp presence flag as well so we are safe | |
86 | * to use this helper too). | |
87 | */ | |
88 | static inline bool apic_from_smp_config(void) | |
89 | { | |
90 | return smp_found_config && !disable_apic; | |
91 | } | |
92 | ||
67c5fc5c TG |
93 | /* |
94 | * Basic functions accessing APICs. | |
95 | */ | |
96 | #ifdef CONFIG_PARAVIRT | |
97 | #include <asm/paravirt.h> | |
96a388de | 98 | #endif |
67c5fc5c | 99 | |
2b97df06 | 100 | extern int setup_profiling_timer(unsigned int); |
aa7d8e25 | 101 | |
1b374e4d | 102 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 103 | { |
593f4a78 | 104 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 105 | |
a930dc45 | 106 | alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, |
593f4a78 MR |
107 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), |
108 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
109 | } |
110 | ||
1b374e4d | 111 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
112 | { |
113 | return *((volatile u32 *)(APIC_BASE + reg)); | |
114 | } | |
115 | ||
c1eeb2de YL |
116 | extern void native_apic_wait_icr_idle(void); |
117 | extern u32 native_safe_apic_wait_icr_idle(void); | |
118 | extern void native_apic_icr_write(u32 low, u32 id); | |
119 | extern u64 native_apic_icr_read(void); | |
120 | ||
8d806960 TG |
121 | static inline bool apic_is_x2apic_enabled(void) |
122 | { | |
123 | u64 msr; | |
124 | ||
125 | if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) | |
126 | return false; | |
127 | return msr & X2APIC_ENABLE; | |
128 | } | |
129 | ||
e02ae387 PB |
130 | extern void enable_IR_x2apic(void); |
131 | ||
132 | extern int get_physical_broadcast(void); | |
133 | ||
134 | extern int lapic_get_maxlvt(void); | |
135 | extern void clear_local_APIC(void); | |
136 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
137 | extern void disable_local_APIC(void); | |
138 | extern void lapic_shutdown(void); | |
139 | extern void sync_Arb_IDs(void); | |
fc90ccfd | 140 | extern void init_bsp_APIC(void); |
4b1669e8 | 141 | extern void apic_intr_mode_init(void); |
e02ae387 PB |
142 | extern void setup_local_APIC(void); |
143 | extern void init_apic_mappings(void); | |
144 | void register_lapic_address(unsigned long address); | |
145 | extern void setup_boot_APIC_clock(void); | |
146 | extern void setup_secondary_APIC_clock(void); | |
6731b0d6 | 147 | extern void lapic_update_tsc_freq(void); |
e02ae387 PB |
148 | |
149 | #ifdef CONFIG_X86_64 | |
150 | static inline int apic_force_enable(unsigned long addr) | |
151 | { | |
152 | return -1; | |
153 | } | |
154 | #else | |
155 | extern int apic_force_enable(unsigned long addr); | |
156 | #endif | |
157 | ||
4b1244b4 | 158 | extern void apic_bsp_setup(bool upmode); |
e02ae387 PB |
159 | extern void apic_ap_setup(void); |
160 | ||
161 | /* | |
162 | * On 32bit this is mach-xxx local | |
163 | */ | |
164 | #ifdef CONFIG_X86_64 | |
165 | extern int apic_is_clustered_box(void); | |
166 | #else | |
167 | static inline int apic_is_clustered_box(void) | |
168 | { | |
169 | return 0; | |
170 | } | |
171 | #endif | |
172 | ||
173 | extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); | |
0fa115da TG |
174 | extern void lapic_assign_system_vectors(void); |
175 | extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); | |
176 | extern void lapic_online(void); | |
177 | extern void lapic_offline(void); | |
f723dd26 | 178 | extern bool apic_needs_pit(void); |
e02ae387 PB |
179 | |
180 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
181 | static inline void lapic_shutdown(void) { } | |
182 | #define local_apic_timer_c2_ok 1 | |
183 | static inline void init_apic_mappings(void) { } | |
184 | static inline void disable_local_APIC(void) { } | |
185 | # define setup_boot_APIC_clock x86_init_noop | |
186 | # define setup_secondary_APIC_clock x86_init_noop | |
6731b0d6 | 187 | static inline void lapic_update_tsc_freq(void) { } |
4b1669e8 | 188 | static inline void apic_intr_mode_init(void) { } |
0fa115da TG |
189 | static inline void lapic_assign_system_vectors(void) { } |
190 | static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } | |
f723dd26 | 191 | static inline bool apic_needs_pit(void) { return true; } |
e02ae387 PB |
192 | #endif /* !CONFIG_X86_LOCAL_APIC */ |
193 | ||
d0b03bd1 | 194 | #ifdef CONFIG_X86_X2APIC |
ce4e240c SS |
195 | /* |
196 | * Make previous memory operations globally visible before | |
197 | * sending the IPI through x2apic wrmsr. We need a serializing instruction or | |
198 | * mfence for this. | |
199 | */ | |
200 | static inline void x2apic_wrmsr_fence(void) | |
201 | { | |
202 | asm volatile("mfence" : : : "memory"); | |
203 | } | |
204 | ||
13c88fb5 SS |
205 | static inline void native_apic_msr_write(u32 reg, u32 v) |
206 | { | |
207 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
208 | reg == APIC_LVR) | |
209 | return; | |
210 | ||
211 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
212 | } | |
213 | ||
0ab711ae MT |
214 | static inline void native_apic_msr_eoi_write(u32 reg, u32 v) |
215 | { | |
a585df8e | 216 | __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); |
0ab711ae MT |
217 | } |
218 | ||
13c88fb5 SS |
219 | static inline u32 native_apic_msr_read(u32 reg) |
220 | { | |
0059b243 | 221 | u64 msr; |
13c88fb5 SS |
222 | |
223 | if (reg == APIC_DFR) | |
224 | return -1; | |
225 | ||
0059b243 AK |
226 | rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); |
227 | return (u32)msr; | |
13c88fb5 SS |
228 | } |
229 | ||
c1eeb2de YL |
230 | static inline void native_x2apic_wait_icr_idle(void) |
231 | { | |
232 | /* no need to wait for icr idle in x2apic */ | |
233 | return; | |
234 | } | |
235 | ||
236 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
237 | { | |
238 | /* no need to wait for icr idle in x2apic */ | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
243 | { | |
244 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
245 | } | |
246 | ||
247 | static inline u64 native_x2apic_icr_read(void) | |
248 | { | |
249 | unsigned long val; | |
250 | ||
251 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
252 | return val; | |
253 | } | |
254 | ||
81a46dd8 | 255 | extern int x2apic_mode; |
fc1edaf9 | 256 | extern int x2apic_phys; |
d524165c | 257 | extern void __init check_x2apic(void); |
659006bf | 258 | extern void x2apic_setup(void); |
a11b5abe YL |
259 | static inline int x2apic_enabled(void) |
260 | { | |
62436a4d | 261 | return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); |
a11b5abe | 262 | } |
fc1edaf9 | 263 | |
62436a4d | 264 | #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) |
e02ae387 | 265 | #else /* !CONFIG_X86_X2APIC */ |
55eae7de | 266 | static inline void check_x2apic(void) { } |
659006bf | 267 | static inline void x2apic_setup(void) { } |
55eae7de | 268 | static inline int x2apic_enabled(void) { return 0; } |
cf6567fe | 269 | |
81a46dd8 | 270 | #define x2apic_mode (0) |
81a46dd8 | 271 | #define x2apic_supported() (0) |
e02ae387 | 272 | #endif /* !CONFIG_X86_X2APIC */ |
67c5fc5c | 273 | |
0e24f7c9 TG |
274 | struct irq_data; |
275 | ||
e2780a68 IM |
276 | /* |
277 | * Copyright 2004 James Cleverdon, IBM. | |
278 | * Subject to the GNU Public License, v.2 | |
279 | * | |
280 | * Generic APIC sub-arch data struct. | |
281 | * | |
282 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
283 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
284 | * James Cleverdon. | |
285 | */ | |
be163a15 | 286 | struct apic { |
72f48a38 TG |
287 | /* Hotpath functions first */ |
288 | void (*eoi_write)(u32 reg, u32 v); | |
289 | void (*native_eoi_write)(u32 reg, u32 v); | |
290 | void (*write)(u32 reg, u32 v); | |
291 | u32 (*read)(u32 reg); | |
292 | ||
293 | /* IPI related functions */ | |
294 | void (*wait_icr_idle)(void); | |
295 | u32 (*safe_wait_icr_idle)(void); | |
296 | ||
297 | void (*send_IPI)(int cpu, int vector); | |
298 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); | |
299 | void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); | |
300 | void (*send_IPI_allbutself)(int vector); | |
301 | void (*send_IPI_all)(int vector); | |
302 | void (*send_IPI_self)(int vector); | |
303 | ||
304 | /* dest_logical is used by the IPI functions */ | |
305 | u32 dest_logical; | |
306 | u32 disable_esr; | |
307 | u32 irq_delivery_mode; | |
308 | u32 irq_dest_mode; | |
309 | ||
310 | /* Functions and data related to vector allocation */ | |
72f48a38 TG |
311 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, |
312 | const struct cpumask *mask); | |
313 | int (*cpu_mask_to_apicid)(const struct cpumask *cpumask, | |
314 | struct irq_data *irqdata, | |
315 | unsigned int *apicid); | |
9f9e3bb1 | 316 | u32 (*calc_dest_apicid)(unsigned int cpu); |
72f48a38 TG |
317 | |
318 | /* ICR related functions */ | |
319 | u64 (*icr_read)(void); | |
320 | void (*icr_write)(u32 low, u32 high); | |
321 | ||
322 | /* Probe, setup and smpboot functions */ | |
323 | int (*probe)(void); | |
324 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
8738749c | 325 | int (*apic_id_valid)(u32 apicid); |
72f48a38 TG |
326 | int (*apic_id_registered)(void); |
327 | ||
328 | bool (*check_apicid_used)(physid_mask_t *map, int apicid); | |
329 | void (*init_apic_ldr)(void); | |
330 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); | |
331 | void (*setup_apic_routing)(void); | |
332 | int (*cpu_present_to_apicid)(int mps_cpu); | |
333 | void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); | |
334 | int (*check_phys_apicid_present)(int phys_apicid); | |
335 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); | |
336 | ||
337 | u32 (*get_apic_id)(unsigned long x); | |
338 | u32 (*set_apic_id)(unsigned int id); | |
e2780a68 IM |
339 | |
340 | /* wakeup_secondary_cpu */ | |
72f48a38 | 341 | int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); |
e2780a68 | 342 | |
72f48a38 | 343 | void (*inquire_remote_apic)(int apicid); |
acb8bc09 TH |
344 | |
345 | #ifdef CONFIG_X86_32 | |
346 | /* | |
347 | * Called very early during boot from get_smp_config(). It should | |
348 | * return the logical apicid. x86_[bios]_cpu_to_apicid is | |
349 | * initialized before this function is called. | |
350 | * | |
351 | * If logical apicid can't be determined that early, the function | |
352 | * may return BAD_APICID. Logical apicid will be configured after | |
353 | * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity | |
354 | * won't be applied properly during early boot in this case. | |
355 | */ | |
356 | int (*x86_32_early_logical_apicid)(int cpu); | |
357 | #endif | |
72f48a38 | 358 | char *name; |
e2780a68 IM |
359 | }; |
360 | ||
0917c01f IM |
361 | /* |
362 | * Pointer to the local APIC driver in use on this system (there's | |
363 | * always just one such driver in use - the kernel decides via an | |
364 | * early probing process which one it picks - and then sticks to it): | |
365 | */ | |
be163a15 | 366 | extern struct apic *apic; |
0917c01f | 367 | |
107e0e0c SS |
368 | /* |
369 | * APIC drivers are probed based on how they are listed in the .apicdrivers | |
370 | * section. So the order is important and enforced by the ordering | |
371 | * of different apic driver files in the Makefile. | |
372 | * | |
373 | * For the files having two apic drivers, we use apic_drivers() | |
374 | * to enforce the order with in them. | |
375 | */ | |
376 | #define apic_driver(sym) \ | |
75fdd155 | 377 | static const struct apic *__apicdrivers_##sym __used \ |
107e0e0c SS |
378 | __aligned(sizeof(struct apic *)) \ |
379 | __section(.apicdrivers) = { &sym } | |
380 | ||
381 | #define apic_drivers(sym1, sym2) \ | |
382 | static struct apic *__apicdrivers_##sym1##sym2[2] __used \ | |
383 | __aligned(sizeof(struct apic *)) \ | |
384 | __section(.apicdrivers) = { &sym1, &sym2 } | |
385 | ||
386 | extern struct apic *__apicdrivers[], *__apicdrivers_end[]; | |
387 | ||
0917c01f IM |
388 | /* |
389 | * APIC functionality to boot other CPUs - only used on SMP: | |
390 | */ | |
391 | #ifdef CONFIG_SMP | |
2b6163bf | 392 | extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); |
2cffad7b | 393 | extern int lapic_can_unplug_cpu(void); |
0917c01f | 394 | #endif |
e2780a68 | 395 | |
d674cd19 | 396 | #ifdef CONFIG_X86_LOCAL_APIC |
346b46be | 397 | |
e2780a68 IM |
398 | static inline u32 apic_read(u32 reg) |
399 | { | |
400 | return apic->read(reg); | |
401 | } | |
402 | ||
403 | static inline void apic_write(u32 reg, u32 val) | |
404 | { | |
405 | apic->write(reg, val); | |
406 | } | |
407 | ||
2a43195d MT |
408 | static inline void apic_eoi(void) |
409 | { | |
410 | apic->eoi_write(APIC_EOI, APIC_EOI_ACK); | |
411 | } | |
412 | ||
e2780a68 IM |
413 | static inline u64 apic_icr_read(void) |
414 | { | |
415 | return apic->icr_read(); | |
416 | } | |
417 | ||
418 | static inline void apic_icr_write(u32 low, u32 high) | |
419 | { | |
420 | apic->icr_write(low, high); | |
421 | } | |
422 | ||
423 | static inline void apic_wait_icr_idle(void) | |
424 | { | |
425 | apic->wait_icr_idle(); | |
426 | } | |
427 | ||
428 | static inline u32 safe_apic_wait_icr_idle(void) | |
429 | { | |
430 | return apic->safe_wait_icr_idle(); | |
431 | } | |
432 | ||
1551df64 MT |
433 | extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); |
434 | ||
d674cd19 CG |
435 | #else /* CONFIG_X86_LOCAL_APIC */ |
436 | ||
437 | static inline u32 apic_read(u32 reg) { return 0; } | |
438 | static inline void apic_write(u32 reg, u32 val) { } | |
2a43195d | 439 | static inline void apic_eoi(void) { } |
d674cd19 CG |
440 | static inline u64 apic_icr_read(void) { return 0; } |
441 | static inline void apic_icr_write(u32 low, u32 high) { } | |
442 | static inline void apic_wait_icr_idle(void) { } | |
443 | static inline u32 safe_apic_wait_icr_idle(void) { return 0; } | |
1551df64 | 444 | static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} |
d674cd19 CG |
445 | |
446 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
e2780a68 | 447 | |
99014a2c TG |
448 | extern void apic_ack_irq(struct irq_data *data); |
449 | ||
e2780a68 IM |
450 | static inline void ack_APIC_irq(void) |
451 | { | |
452 | /* | |
453 | * ack_APIC_irq() actually gets compiled as a single instruction | |
454 | * ... yummie. | |
455 | */ | |
2a43195d | 456 | apic_eoi(); |
e2780a68 IM |
457 | } |
458 | ||
92e06be2 TG |
459 | |
460 | static inline bool lapic_vector_set_in_irr(unsigned int vector) | |
461 | { | |
462 | u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
463 | ||
464 | return !!(irr & (1U << (vector % 32))); | |
465 | } | |
466 | ||
e2780a68 IM |
467 | static inline unsigned default_get_apic_id(unsigned long x) |
468 | { | |
469 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
470 | ||
42937e81 | 471 | if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) |
e2780a68 IM |
472 | return (x >> 24) & 0xFF; |
473 | else | |
474 | return (x >> 24) & 0x0F; | |
475 | } | |
476 | ||
477 | /* | |
6ab1b27c | 478 | * Warm reset vector position: |
e2780a68 | 479 | */ |
6ab1b27c DR |
480 | #define TRAMPOLINE_PHYS_LOW 0x467 |
481 | #define TRAMPOLINE_PHYS_HIGH 0x469 | |
e2780a68 | 482 | |
2b6163bf | 483 | #ifdef CONFIG_X86_64 |
e2780a68 IM |
484 | extern void apic_send_IPI_self(int vector); |
485 | ||
e2780a68 | 486 | DECLARE_PER_CPU(int, x2apic_extra_bits); |
e2780a68 IM |
487 | #endif |
488 | ||
838312be | 489 | extern void generic_bigsmp_probe(void); |
e2780a68 | 490 | |
e2780a68 IM |
491 | #ifdef CONFIG_X86_LOCAL_APIC |
492 | ||
493 | #include <asm/smp.h> | |
494 | ||
495 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
496 | ||
0816b0f0 | 497 | DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); |
e2780a68 | 498 | |
83a10522 | 499 | extern struct apic apic_noop; |
e2780a68 IM |
500 | |
501 | static inline unsigned int read_apic_id(void) | |
502 | { | |
83a10522 | 503 | unsigned int reg = apic_read(APIC_ID); |
e2780a68 IM |
504 | |
505 | return apic->get_apic_id(reg); | |
506 | } | |
507 | ||
8738749c | 508 | extern int default_apic_id_valid(u32 apicid); |
a491cc90 | 509 | extern int default_acpi_madt_oem_check(char *, char *); |
e2780a68 | 510 | extern void default_setup_apic_routing(void); |
9f9e3bb1 TG |
511 | |
512 | extern u32 apic_default_calc_apicid(unsigned int cpu); | |
513 | extern u32 apic_flat_calc_apicid(unsigned int cpu); | |
514 | ||
91cd9cb7 | 515 | extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask, |
0e24f7c9 | 516 | struct irq_data *irqdata, |
91cd9cb7 TG |
517 | unsigned int *apicid); |
518 | extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask, | |
0e24f7c9 | 519 | struct irq_data *irqdata, |
91cd9cb7 | 520 | unsigned int *apicid); |
83a10522 TG |
521 | extern bool default_check_apicid_used(physid_mask_t *map, int apicid); |
522 | extern void flat_vector_allocation_domain(int cpu, struct cpumask *retmask, | |
523 | const struct cpumask *mask); | |
524 | extern void default_vector_allocation_domain(int cpu, struct cpumask *retmask, | |
525 | const struct cpumask *mask); | |
526 | extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); | |
e2780a68 | 527 | extern int default_cpu_present_to_apicid(int mps_cpu); |
e11dadab | 528 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 | 529 | |
e2780a68 | 530 | #endif /* CONFIG_X86_LOCAL_APIC */ |
83a10522 | 531 | |
b133f8e9 TG |
532 | #ifdef CONFIG_SMP |
533 | bool apic_id_is_primary_thread(unsigned int id); | |
a61e3193 | 534 | bool apic_id_disabled(unsigned int id); |
b133f8e9 TG |
535 | #else |
536 | static inline bool apic_id_is_primary_thread(unsigned int id) { return false; } | |
a61e3193 | 537 | static inline bool apic_id_disabled(unsigned int id) { return false; } |
b133f8e9 TG |
538 | #endif |
539 | ||
eddc0e92 SA |
540 | extern void irq_enter(void); |
541 | extern void irq_exit(void); | |
542 | ||
543 | static inline void entering_irq(void) | |
544 | { | |
545 | irq_enter(); | |
9dcfef9f | 546 | kvm_set_cpu_l1tf_flush_l1d(); |
eddc0e92 SA |
547 | } |
548 | ||
549 | static inline void entering_ack_irq(void) | |
550 | { | |
eddc0e92 | 551 | entering_irq(); |
7834c103 | 552 | ack_APIC_irq(); |
eddc0e92 SA |
553 | } |
554 | ||
6dc17876 TG |
555 | static inline void ipi_entering_ack_irq(void) |
556 | { | |
6dc17876 | 557 | irq_enter(); |
b0f48706 | 558 | ack_APIC_irq(); |
9dcfef9f | 559 | kvm_set_cpu_l1tf_flush_l1d(); |
6dc17876 TG |
560 | } |
561 | ||
eddc0e92 SA |
562 | static inline void exiting_irq(void) |
563 | { | |
564 | irq_exit(); | |
565 | } | |
566 | ||
567 | static inline void exiting_ack_irq(void) | |
568 | { | |
eddc0e92 | 569 | ack_APIC_irq(); |
b0f48706 | 570 | irq_exit(); |
eddc0e92 | 571 | } |
e2780a68 | 572 | |
17405453 YY |
573 | extern void ioapic_zap_locks(void); |
574 | ||
1965aae3 | 575 | #endif /* _ASM_X86_APIC_H */ |