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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c | 3 | |
e2780a68 | 4 | #include <linux/cpumask.h> |
e2780a68 | 5 | #include <linux/pm.h> |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
e2780a68 | 8 | #include <asm/cpufeature.h> |
67c5fc5c | 9 | #include <asm/processor.h> |
e2780a68 | 10 | #include <asm/apicdef.h> |
60063497 | 11 | #include <linux/atomic.h> |
e2780a68 IM |
12 | #include <asm/fixmap.h> |
13 | #include <asm/mpspec.h> | |
13c88fb5 | 14 | #include <asm/msr.h> |
eddc0e92 | 15 | #include <asm/idle.h> |
67c5fc5c TG |
16 | |
17 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
18 | ||
67c5fc5c TG |
19 | /* |
20 | * Debugging macros | |
21 | */ | |
22 | #define APIC_QUIET 0 | |
23 | #define APIC_VERBOSE 1 | |
24 | #define APIC_DEBUG 2 | |
25 | ||
26 | /* | |
27 | * Define the default level of output to be very little | |
28 | * This can be turned up by using apic=verbose for more | |
29 | * information and apic=debug for _lots_ of information. | |
30 | * apic_verbosity is defined in apic.c | |
31 | */ | |
32 | #define apic_printk(v, s, a...) do { \ | |
33 | if ((v) <= apic_verbosity) \ | |
34 | printk(s, ##a); \ | |
35 | } while (0) | |
36 | ||
37 | ||
160d8dac | 38 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
67c5fc5c | 39 | extern void generic_apic_probe(void); |
160d8dac IM |
40 | #else |
41 | static inline void generic_apic_probe(void) | |
42 | { | |
43 | } | |
44 | #endif | |
67c5fc5c TG |
45 | |
46 | #ifdef CONFIG_X86_LOCAL_APIC | |
47 | ||
baa13188 | 48 | extern unsigned int apic_verbosity; |
67c5fc5c | 49 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 50 | |
3c999f14 | 51 | extern int disable_apic; |
1ade93ef | 52 | extern unsigned int lapic_timer_frequency; |
0939e4fd IM |
53 | |
54 | #ifdef CONFIG_SMP | |
55 | extern void __inquire_remote_apic(int apicid); | |
56 | #else /* CONFIG_SMP */ | |
57 | static inline void __inquire_remote_apic(int apicid) | |
58 | { | |
59 | } | |
60 | #endif /* CONFIG_SMP */ | |
61 | ||
62 | static inline void default_inquire_remote_apic(int apicid) | |
63 | { | |
64 | if (apic_verbosity >= APIC_DEBUG) | |
65 | __inquire_remote_apic(apicid); | |
66 | } | |
67 | ||
8312136f CG |
68 | /* |
69 | * With 82489DX we can't rely on apic feature bit | |
70 | * retrieved via cpuid but still have to deal with | |
71 | * such an apic chip so we assume that SMP configuration | |
72 | * is found from MP table (64bit case uses ACPI mostly | |
73 | * which set smp presence flag as well so we are safe | |
74 | * to use this helper too). | |
75 | */ | |
76 | static inline bool apic_from_smp_config(void) | |
77 | { | |
78 | return smp_found_config && !disable_apic; | |
79 | } | |
80 | ||
67c5fc5c TG |
81 | /* |
82 | * Basic functions accessing APICs. | |
83 | */ | |
84 | #ifdef CONFIG_PARAVIRT | |
85 | #include <asm/paravirt.h> | |
96a388de | 86 | #endif |
67c5fc5c | 87 | |
70511134 | 88 | #ifdef CONFIG_X86_64 |
aa7d8e25 | 89 | extern int is_vsmp_box(void); |
129d8bc8 YL |
90 | #else |
91 | static inline int is_vsmp_box(void) | |
92 | { | |
93 | return 0; | |
94 | } | |
95 | #endif | |
2b97df06 | 96 | extern int setup_profiling_timer(unsigned int); |
aa7d8e25 | 97 | |
1b374e4d | 98 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 99 | { |
593f4a78 | 100 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 101 | |
593f4a78 MR |
102 | alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, |
103 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), | |
104 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
105 | } |
106 | ||
1b374e4d | 107 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
108 | { |
109 | return *((volatile u32 *)(APIC_BASE + reg)); | |
110 | } | |
111 | ||
c1eeb2de YL |
112 | extern void native_apic_wait_icr_idle(void); |
113 | extern u32 native_safe_apic_wait_icr_idle(void); | |
114 | extern void native_apic_icr_write(u32 low, u32 id); | |
115 | extern u64 native_apic_icr_read(void); | |
116 | ||
fc1edaf9 | 117 | extern int x2apic_mode; |
b24696bc | 118 | |
d0b03bd1 | 119 | #ifdef CONFIG_X86_X2APIC |
ce4e240c SS |
120 | /* |
121 | * Make previous memory operations globally visible before | |
122 | * sending the IPI through x2apic wrmsr. We need a serializing instruction or | |
123 | * mfence for this. | |
124 | */ | |
125 | static inline void x2apic_wrmsr_fence(void) | |
126 | { | |
127 | asm volatile("mfence" : : : "memory"); | |
128 | } | |
129 | ||
13c88fb5 SS |
130 | static inline void native_apic_msr_write(u32 reg, u32 v) |
131 | { | |
132 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
133 | reg == APIC_LVR) | |
134 | return; | |
135 | ||
136 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
137 | } | |
138 | ||
0ab711ae MT |
139 | static inline void native_apic_msr_eoi_write(u32 reg, u32 v) |
140 | { | |
141 | wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); | |
142 | } | |
143 | ||
13c88fb5 SS |
144 | static inline u32 native_apic_msr_read(u32 reg) |
145 | { | |
0059b243 | 146 | u64 msr; |
13c88fb5 SS |
147 | |
148 | if (reg == APIC_DFR) | |
149 | return -1; | |
150 | ||
0059b243 AK |
151 | rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); |
152 | return (u32)msr; | |
13c88fb5 SS |
153 | } |
154 | ||
c1eeb2de YL |
155 | static inline void native_x2apic_wait_icr_idle(void) |
156 | { | |
157 | /* no need to wait for icr idle in x2apic */ | |
158 | return; | |
159 | } | |
160 | ||
161 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
162 | { | |
163 | /* no need to wait for icr idle in x2apic */ | |
164 | return 0; | |
165 | } | |
166 | ||
167 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
168 | { | |
169 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
170 | } | |
171 | ||
172 | static inline u64 native_x2apic_icr_read(void) | |
173 | { | |
174 | unsigned long val; | |
175 | ||
176 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
177 | return val; | |
178 | } | |
179 | ||
fc1edaf9 | 180 | extern int x2apic_phys; |
fb209bd8 | 181 | extern int x2apic_preenabled; |
6e1cb38a SS |
182 | extern void check_x2apic(void); |
183 | extern void enable_x2apic(void); | |
a11b5abe YL |
184 | static inline int x2apic_enabled(void) |
185 | { | |
0059b243 | 186 | u64 msr; |
a11b5abe YL |
187 | |
188 | if (!cpu_has_x2apic) | |
189 | return 0; | |
190 | ||
0059b243 | 191 | rdmsrl(MSR_IA32_APICBASE, msr); |
a11b5abe YL |
192 | if (msr & X2APIC_ENABLE) |
193 | return 1; | |
194 | return 0; | |
195 | } | |
fc1edaf9 SS |
196 | |
197 | #define x2apic_supported() (cpu_has_x2apic) | |
ce69a784 GN |
198 | static inline void x2apic_force_phys(void) |
199 | { | |
200 | x2apic_phys = 1; | |
201 | } | |
a11b5abe | 202 | #else |
fb209bd8 YL |
203 | static inline void disable_x2apic(void) |
204 | { | |
205 | } | |
06cd9a7d YL |
206 | static inline void check_x2apic(void) |
207 | { | |
208 | } | |
209 | static inline void enable_x2apic(void) | |
210 | { | |
211 | } | |
06cd9a7d YL |
212 | static inline int x2apic_enabled(void) |
213 | { | |
214 | return 0; | |
215 | } | |
ce69a784 GN |
216 | static inline void x2apic_force_phys(void) |
217 | { | |
218 | } | |
cf6567fe | 219 | |
93758238 | 220 | #define x2apic_preenabled 0 |
fc1edaf9 | 221 | #define x2apic_supported() 0 |
c535b6a1 | 222 | #endif |
1b374e4d | 223 | |
93758238 WH |
224 | extern void enable_IR_x2apic(void); |
225 | ||
67c5fc5c TG |
226 | extern int get_physical_broadcast(void); |
227 | ||
67c5fc5c TG |
228 | extern int lapic_get_maxlvt(void); |
229 | extern void clear_local_APIC(void); | |
230 | extern void connect_bsp_APIC(void); | |
231 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
232 | extern void disable_local_APIC(void); | |
233 | extern void lapic_shutdown(void); | |
234 | extern int verify_local_APIC(void); | |
67c5fc5c TG |
235 | extern void sync_Arb_IDs(void); |
236 | extern void init_bsp_APIC(void); | |
237 | extern void setup_local_APIC(void); | |
739f33b3 | 238 | extern void end_local_APIC_setup(void); |
2fb270f3 | 239 | extern void bsp_end_local_APIC_setup(void); |
67c5fc5c | 240 | extern void init_apic_mappings(void); |
c0104d38 | 241 | void register_lapic_address(unsigned long address); |
67c5fc5c TG |
242 | extern void setup_boot_APIC_clock(void); |
243 | extern void setup_secondary_APIC_clock(void); | |
244 | extern int APIC_init_uniprocessor(void); | |
a906fdaa | 245 | extern int apic_force_enable(unsigned long addr); |
67c5fc5c TG |
246 | |
247 | /* | |
248 | * On 32bit this is mach-xxx local | |
249 | */ | |
250 | #ifdef CONFIG_X86_64 | |
8fbbc4b4 AK |
251 | extern int apic_is_clustered_box(void); |
252 | #else | |
253 | static inline int apic_is_clustered_box(void) | |
254 | { | |
255 | return 0; | |
256 | } | |
67c5fc5c TG |
257 | #endif |
258 | ||
27afdf20 | 259 | extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); |
67c5fc5c TG |
260 | |
261 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
262 | static inline void lapic_shutdown(void) { } | |
263 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 264 | static inline void init_apic_mappings(void) { } |
d3ec5cae | 265 | static inline void disable_local_APIC(void) { } |
736decac TG |
266 | # define setup_boot_APIC_clock x86_init_noop |
267 | # define setup_secondary_APIC_clock x86_init_noop | |
67c5fc5c TG |
268 | #endif /* !CONFIG_X86_LOCAL_APIC */ |
269 | ||
1f75ed0c IM |
270 | #ifdef CONFIG_X86_64 |
271 | #define SET_APIC_ID(x) (apic->set_apic_id(x)) | |
272 | #else | |
273 | ||
1f75ed0c IM |
274 | #endif |
275 | ||
e2780a68 IM |
276 | /* |
277 | * Copyright 2004 James Cleverdon, IBM. | |
278 | * Subject to the GNU Public License, v.2 | |
279 | * | |
280 | * Generic APIC sub-arch data struct. | |
281 | * | |
282 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
283 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
284 | * James Cleverdon. | |
285 | */ | |
be163a15 | 286 | struct apic { |
e2780a68 IM |
287 | char *name; |
288 | ||
289 | int (*probe)(void); | |
290 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
fa63030e | 291 | int (*apic_id_valid)(int apicid); |
e2780a68 IM |
292 | int (*apic_id_registered)(void); |
293 | ||
294 | u32 irq_delivery_mode; | |
295 | u32 irq_dest_mode; | |
296 | ||
297 | const struct cpumask *(*target_cpus)(void); | |
298 | ||
299 | int disable_esr; | |
300 | ||
301 | int dest_logical; | |
7abc0753 | 302 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); |
e2780a68 IM |
303 | unsigned long (*check_apicid_present)(int apicid); |
304 | ||
1ac322d0 SS |
305 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, |
306 | const struct cpumask *mask); | |
e2780a68 IM |
307 | void (*init_apic_ldr)(void); |
308 | ||
7abc0753 | 309 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); |
e2780a68 IM |
310 | |
311 | void (*setup_apic_routing)(void); | |
312 | int (*multi_timer_check)(int apic, int irq); | |
e2780a68 | 313 | int (*cpu_present_to_apicid)(int mps_cpu); |
7abc0753 | 314 | void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); |
e2780a68 | 315 | void (*setup_portio_remap)(void); |
e11dadab | 316 | int (*check_phys_apicid_present)(int phys_apicid); |
e2780a68 IM |
317 | void (*enable_apic_mode)(void); |
318 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); | |
319 | ||
320 | /* | |
be163a15 | 321 | * When one of the next two hooks returns 1 the apic |
e2780a68 IM |
322 | * is switched to this. Essentially they are additional |
323 | * probe functions: | |
324 | */ | |
325 | int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); | |
326 | ||
327 | unsigned int (*get_apic_id)(unsigned long x); | |
328 | unsigned long (*set_apic_id)(unsigned int id); | |
329 | unsigned long apic_id_mask; | |
330 | ||
ff164324 AG |
331 | int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, |
332 | const struct cpumask *andmask, | |
333 | unsigned int *apicid); | |
e2780a68 IM |
334 | |
335 | /* ipi */ | |
336 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); | |
337 | void (*send_IPI_mask_allbutself)(const struct cpumask *mask, | |
338 | int vector); | |
339 | void (*send_IPI_allbutself)(int vector); | |
340 | void (*send_IPI_all)(int vector); | |
341 | void (*send_IPI_self)(int vector); | |
342 | ||
343 | /* wakeup_secondary_cpu */ | |
1f5bcabf | 344 | int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); |
e2780a68 IM |
345 | |
346 | int trampoline_phys_low; | |
347 | int trampoline_phys_high; | |
348 | ||
465822cf | 349 | bool wait_for_init_deassert; |
e2780a68 | 350 | void (*smp_callin_clear_local_apic)(void); |
e2780a68 IM |
351 | void (*inquire_remote_apic)(int apicid); |
352 | ||
353 | /* apic ops */ | |
354 | u32 (*read)(u32 reg); | |
355 | void (*write)(u32 reg, u32 v); | |
2a43195d MT |
356 | /* |
357 | * ->eoi_write() has the same signature as ->write(). | |
358 | * | |
359 | * Drivers can support both ->eoi_write() and ->write() by passing the same | |
360 | * callback value. Kernel can override ->eoi_write() and fall back | |
361 | * on write for EOI. | |
362 | */ | |
363 | void (*eoi_write)(u32 reg, u32 v); | |
e2780a68 IM |
364 | u64 (*icr_read)(void); |
365 | void (*icr_write)(u32 low, u32 high); | |
366 | void (*wait_icr_idle)(void); | |
367 | u32 (*safe_wait_icr_idle)(void); | |
acb8bc09 TH |
368 | |
369 | #ifdef CONFIG_X86_32 | |
370 | /* | |
371 | * Called very early during boot from get_smp_config(). It should | |
372 | * return the logical apicid. x86_[bios]_cpu_to_apicid is | |
373 | * initialized before this function is called. | |
374 | * | |
375 | * If logical apicid can't be determined that early, the function | |
376 | * may return BAD_APICID. Logical apicid will be configured after | |
377 | * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity | |
378 | * won't be applied properly during early boot in this case. | |
379 | */ | |
380 | int (*x86_32_early_logical_apicid)(int cpu); | |
89e5dc21 | 381 | |
84914ed0 TH |
382 | /* |
383 | * Optional method called from setup_local_APIC() after logical | |
384 | * apicid is guaranteed to be known to initialize apicid -> node | |
385 | * mapping if NUMA initialization hasn't done so already. Don't | |
386 | * add new users. | |
387 | */ | |
89e5dc21 | 388 | int (*x86_32_numa_cpu_node)(int cpu); |
acb8bc09 | 389 | #endif |
e2780a68 IM |
390 | }; |
391 | ||
0917c01f IM |
392 | /* |
393 | * Pointer to the local APIC driver in use on this system (there's | |
394 | * always just one such driver in use - the kernel decides via an | |
395 | * early probing process which one it picks - and then sticks to it): | |
396 | */ | |
be163a15 | 397 | extern struct apic *apic; |
0917c01f | 398 | |
107e0e0c SS |
399 | /* |
400 | * APIC drivers are probed based on how they are listed in the .apicdrivers | |
401 | * section. So the order is important and enforced by the ordering | |
402 | * of different apic driver files in the Makefile. | |
403 | * | |
404 | * For the files having two apic drivers, we use apic_drivers() | |
405 | * to enforce the order with in them. | |
406 | */ | |
407 | #define apic_driver(sym) \ | |
75fdd155 | 408 | static const struct apic *__apicdrivers_##sym __used \ |
107e0e0c SS |
409 | __aligned(sizeof(struct apic *)) \ |
410 | __section(.apicdrivers) = { &sym } | |
411 | ||
412 | #define apic_drivers(sym1, sym2) \ | |
413 | static struct apic *__apicdrivers_##sym1##sym2[2] __used \ | |
414 | __aligned(sizeof(struct apic *)) \ | |
415 | __section(.apicdrivers) = { &sym1, &sym2 } | |
416 | ||
417 | extern struct apic *__apicdrivers[], *__apicdrivers_end[]; | |
418 | ||
0917c01f IM |
419 | /* |
420 | * APIC functionality to boot other CPUs - only used on SMP: | |
421 | */ | |
422 | #ifdef CONFIG_SMP | |
2b6163bf YL |
423 | extern atomic_t init_deasserted; |
424 | extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); | |
0917c01f | 425 | #endif |
e2780a68 | 426 | |
d674cd19 | 427 | #ifdef CONFIG_X86_LOCAL_APIC |
346b46be | 428 | |
e2780a68 IM |
429 | static inline u32 apic_read(u32 reg) |
430 | { | |
431 | return apic->read(reg); | |
432 | } | |
433 | ||
434 | static inline void apic_write(u32 reg, u32 val) | |
435 | { | |
436 | apic->write(reg, val); | |
437 | } | |
438 | ||
2a43195d MT |
439 | static inline void apic_eoi(void) |
440 | { | |
441 | apic->eoi_write(APIC_EOI, APIC_EOI_ACK); | |
442 | } | |
443 | ||
e2780a68 IM |
444 | static inline u64 apic_icr_read(void) |
445 | { | |
446 | return apic->icr_read(); | |
447 | } | |
448 | ||
449 | static inline void apic_icr_write(u32 low, u32 high) | |
450 | { | |
451 | apic->icr_write(low, high); | |
452 | } | |
453 | ||
454 | static inline void apic_wait_icr_idle(void) | |
455 | { | |
456 | apic->wait_icr_idle(); | |
457 | } | |
458 | ||
459 | static inline u32 safe_apic_wait_icr_idle(void) | |
460 | { | |
461 | return apic->safe_wait_icr_idle(); | |
462 | } | |
463 | ||
1551df64 MT |
464 | extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); |
465 | ||
d674cd19 CG |
466 | #else /* CONFIG_X86_LOCAL_APIC */ |
467 | ||
468 | static inline u32 apic_read(u32 reg) { return 0; } | |
469 | static inline void apic_write(u32 reg, u32 val) { } | |
2a43195d | 470 | static inline void apic_eoi(void) { } |
d674cd19 CG |
471 | static inline u64 apic_icr_read(void) { return 0; } |
472 | static inline void apic_icr_write(u32 low, u32 high) { } | |
473 | static inline void apic_wait_icr_idle(void) { } | |
474 | static inline u32 safe_apic_wait_icr_idle(void) { return 0; } | |
1551df64 | 475 | static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} |
d674cd19 CG |
476 | |
477 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
e2780a68 IM |
478 | |
479 | static inline void ack_APIC_irq(void) | |
480 | { | |
481 | /* | |
482 | * ack_APIC_irq() actually gets compiled as a single instruction | |
483 | * ... yummie. | |
484 | */ | |
2a43195d | 485 | apic_eoi(); |
e2780a68 IM |
486 | } |
487 | ||
488 | static inline unsigned default_get_apic_id(unsigned long x) | |
489 | { | |
490 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
491 | ||
42937e81 | 492 | if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) |
e2780a68 IM |
493 | return (x >> 24) & 0xFF; |
494 | else | |
495 | return (x >> 24) & 0x0F; | |
496 | } | |
497 | ||
498 | /* | |
499 | * Warm reset vector default position: | |
500 | */ | |
501 | #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 | |
502 | #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 | |
503 | ||
2b6163bf | 504 | #ifdef CONFIG_X86_64 |
e2780a68 IM |
505 | extern int default_acpi_madt_oem_check(char *, char *); |
506 | ||
507 | extern void apic_send_IPI_self(int vector); | |
508 | ||
e2780a68 IM |
509 | DECLARE_PER_CPU(int, x2apic_extra_bits); |
510 | ||
511 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 512 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
513 | #endif |
514 | ||
838312be | 515 | extern void generic_bigsmp_probe(void); |
e2780a68 IM |
516 | |
517 | ||
518 | #ifdef CONFIG_X86_LOCAL_APIC | |
519 | ||
520 | #include <asm/smp.h> | |
521 | ||
522 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
523 | ||
524 | static inline const struct cpumask *default_target_cpus(void) | |
525 | { | |
526 | #ifdef CONFIG_SMP | |
527 | return cpu_online_mask; | |
528 | #else | |
529 | return cpumask_of(0); | |
530 | #endif | |
531 | } | |
532 | ||
bf721d3a AG |
533 | static inline const struct cpumask *online_target_cpus(void) |
534 | { | |
535 | return cpu_online_mask; | |
536 | } | |
537 | ||
0816b0f0 | 538 | DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); |
e2780a68 IM |
539 | |
540 | ||
541 | static inline unsigned int read_apic_id(void) | |
542 | { | |
543 | unsigned int reg; | |
544 | ||
545 | reg = apic_read(APIC_ID); | |
546 | ||
547 | return apic->get_apic_id(reg); | |
548 | } | |
549 | ||
fa63030e DB |
550 | static inline int default_apic_id_valid(int apicid) |
551 | { | |
b7157acf | 552 | return (apicid < 255); |
fa63030e DB |
553 | } |
554 | ||
e2780a68 IM |
555 | extern void default_setup_apic_routing(void); |
556 | ||
9844ab11 CG |
557 | extern struct apic apic_noop; |
558 | ||
e2780a68 | 559 | #ifdef CONFIG_X86_32 |
2c1b284e | 560 | |
acb8bc09 TH |
561 | static inline int noop_x86_32_early_logical_apicid(int cpu) |
562 | { | |
563 | return BAD_APICID; | |
564 | } | |
565 | ||
e2780a68 IM |
566 | /* |
567 | * Set up the logical destination ID. | |
568 | * | |
569 | * Intel recommends to set DFR, LDR and TPR before enabling | |
570 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
571 | * document number 292116). So here it goes... | |
572 | */ | |
573 | extern void default_init_apic_ldr(void); | |
574 | ||
575 | static inline int default_apic_id_registered(void) | |
576 | { | |
577 | return physid_isset(read_apic_id(), phys_cpu_present_map); | |
578 | } | |
579 | ||
f56e5034 YL |
580 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) |
581 | { | |
582 | return cpuid_apic >> index_msb; | |
583 | } | |
584 | ||
f56e5034 YL |
585 | #endif |
586 | ||
ff164324 | 587 | static inline int |
a5a39156 AG |
588 | flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
589 | const struct cpumask *andmask, | |
590 | unsigned int *apicid) | |
e2780a68 | 591 | { |
a5a39156 AG |
592 | unsigned long cpu_mask = cpumask_bits(cpumask)[0] & |
593 | cpumask_bits(andmask)[0] & | |
594 | cpumask_bits(cpu_online_mask)[0] & | |
595 | APIC_ALL_CPUS; | |
596 | ||
ff164324 AG |
597 | if (likely(cpu_mask)) { |
598 | *apicid = (unsigned int)cpu_mask; | |
599 | return 0; | |
600 | } else { | |
601 | return -EINVAL; | |
602 | } | |
603 | } | |
604 | ||
ff164324 | 605 | extern int |
6398268d | 606 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
607 | const struct cpumask *andmask, |
608 | unsigned int *apicid); | |
6398268d | 609 | |
b39f25a8 | 610 | static inline void |
1ac322d0 SS |
611 | flat_vector_allocation_domain(int cpu, struct cpumask *retmask, |
612 | const struct cpumask *mask) | |
9d8e1066 AG |
613 | { |
614 | /* Careful. Some cpus do not strictly honor the set of cpus | |
615 | * specified in the interrupt destination when using lowest | |
616 | * priority interrupt delivery mode. | |
617 | * | |
618 | * In particular there was a hyperthreading cpu observed to | |
619 | * deliver interrupts to the wrong hyperthread when only one | |
620 | * hyperthread was specified in the interrupt desitination. | |
621 | */ | |
622 | cpumask_clear(retmask); | |
623 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | |
624 | } | |
625 | ||
b39f25a8 | 626 | static inline void |
1ac322d0 SS |
627 | default_vector_allocation_domain(int cpu, struct cpumask *retmask, |
628 | const struct cpumask *mask) | |
9d8e1066 AG |
629 | { |
630 | cpumask_copy(retmask, cpumask_of(cpu)); | |
631 | } | |
632 | ||
7abc0753 | 633 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) |
e2780a68 | 634 | { |
7abc0753 | 635 | return physid_isset(apicid, *map); |
e2780a68 IM |
636 | } |
637 | ||
638 | static inline unsigned long default_check_apicid_present(int bit) | |
639 | { | |
640 | return physid_isset(bit, phys_cpu_present_map); | |
641 | } | |
642 | ||
7abc0753 | 643 | static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) |
e2780a68 | 644 | { |
7abc0753 | 645 | *retmap = *phys_map; |
e2780a68 IM |
646 | } |
647 | ||
e2780a68 IM |
648 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
649 | { | |
650 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | |
651 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
652 | else | |
653 | return BAD_APICID; | |
654 | } | |
655 | ||
656 | static inline int | |
e11dadab | 657 | __default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 658 | { |
e11dadab | 659 | return physid_isset(phys_apicid, phys_cpu_present_map); |
e2780a68 IM |
660 | } |
661 | ||
662 | #ifdef CONFIG_X86_32 | |
663 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
664 | { | |
665 | return __default_cpu_present_to_apicid(mps_cpu); | |
666 | } | |
667 | ||
668 | static inline int | |
e11dadab | 669 | default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 670 | { |
e11dadab | 671 | return __default_check_phys_apicid_present(phys_apicid); |
e2780a68 IM |
672 | } |
673 | #else | |
674 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 675 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
676 | #endif |
677 | ||
e2780a68 | 678 | #endif /* CONFIG_X86_LOCAL_APIC */ |
eddc0e92 SA |
679 | extern void irq_enter(void); |
680 | extern void irq_exit(void); | |
681 | ||
682 | static inline void entering_irq(void) | |
683 | { | |
684 | irq_enter(); | |
685 | exit_idle(); | |
686 | } | |
687 | ||
688 | static inline void entering_ack_irq(void) | |
689 | { | |
690 | ack_APIC_irq(); | |
691 | entering_irq(); | |
692 | } | |
693 | ||
694 | static inline void exiting_irq(void) | |
695 | { | |
696 | irq_exit(); | |
697 | } | |
698 | ||
699 | static inline void exiting_ack_irq(void) | |
700 | { | |
701 | irq_exit(); | |
702 | /* Ack only at the end to avoid potential reentry */ | |
703 | ack_APIC_irq(); | |
704 | } | |
e2780a68 | 705 | |
17405453 YY |
706 | extern void ioapic_zap_locks(void); |
707 | ||
1965aae3 | 708 | #endif /* _ASM_X86_APIC_H */ |