projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1965aae3 PA |
1 | #ifndef _ASM_X86_CPUFEATURE_H |
| 2 | #define _ASM_X86_CPUFEATURE_H | |
| 7b11fb51 | 3 | |
| cd4d09ec | 4 | #include <asm/processor.h> |
| e2604b49 | 5 | |
| fa1408e4 PA |
6 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 7 | ||
| a3c8acd0 | 8 | #include <asm/asm.h> |
| fa1408e4 PA |
9 | #include <linux/bitops.h> |
| 10 | ||
| 39c06df4 BP |
11 | enum cpuid_leafs |
| 12 | { | |
| 13 | CPUID_1_EDX = 0, | |
| 14 | CPUID_8000_0001_EDX, | |
| 15 | CPUID_8086_0001_EDX, | |
| 16 | CPUID_LNX_1, | |
| 17 | CPUID_1_ECX, | |
| 18 | CPUID_C000_0001_EDX, | |
| 19 | CPUID_8000_0001_ECX, | |
| 20 | CPUID_LNX_2, | |
| 21 | CPUID_LNX_3, | |
| 22 | CPUID_7_0_EBX, | |
| 23 | CPUID_D_1_EAX, | |
| 24 | CPUID_F_0_EDX, | |
| 25 | CPUID_F_1_EDX, | |
| 26 | CPUID_8000_0008_EBX, | |
| 27 | CPUID_6_EAX, | |
| 28 | CPUID_8000_000A_EDX, | |
| dfb4a70f | 29 | CPUID_7_ECX, |
| 71faad43 | 30 | CPUID_8000_0007_EBX, |
| 39c06df4 BP |
31 | }; |
| 32 | ||
| 9def39be | 33 | #ifdef CONFIG_X86_FEATURE_NAMES |
| fa1408e4 PA |
34 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
| 35 | extern const char * const x86_power_flags[32]; | |
| 9def39be JT |
36 | #define X86_CAP_FMT "%s" |
| 37 | #define x86_cap_flag(flag) x86_cap_flags[flag] | |
| 38 | #else | |
| 39 | #define X86_CAP_FMT "%d:%d" | |
| 40 | #define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31) | |
| 41 | #endif | |
| fa1408e4 | 42 | |
| 80a208bd BP |
43 | /* |
| 44 | * In order to save room, we index into this array by doing | |
| 45 | * X86_BUG_<name> - NCAPINTS*32. | |
| 46 | */ | |
| 47 | extern const char * const x86_bug_flags[NBUGINTS*32]; | |
| 48 | ||
| 0f8d2b92 IM |
49 | #define test_cpu_cap(c, bit) \ |
| 50 | test_bit(bit, (unsigned long *)((c)->x86_capability)) | |
| 51 | ||
| 349c004e | 52 | #define REQUIRED_MASK_BIT_SET(bit) \ |
| dfb4a70f DH |
53 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0 )) || \ |
| 54 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1 )) || \ | |
| 55 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2 )) || \ | |
| 56 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3 )) || \ | |
| 57 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4 )) || \ | |
| 58 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5 )) || \ | |
| 59 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6 )) || \ | |
| 60 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7 )) || \ | |
| 61 | (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8 )) || \ | |
| 62 | (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9 )) || \ | |
| 63 | (((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) || \ | |
| 64 | (((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) || \ | |
| 65 | (((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) || \ | |
| 66 | (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \ | |
| 67 | (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ | |
| 68 | (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ | |
| 69 | (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK16)) ) | |
| 349c004e | 70 | |
| 381aa07a | 71 | #define DISABLED_MASK_BIT_SET(bit) \ |
| dfb4a70f DH |
72 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \ |
| 73 | (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1 )) || \ | |
| 74 | (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2 )) || \ | |
| 75 | (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3 )) || \ | |
| 76 | (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4 )) || \ | |
| 77 | (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5 )) || \ | |
| 78 | (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6 )) || \ | |
| 79 | (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7 )) || \ | |
| 80 | (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8 )) || \ | |
| 81 | (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9 )) || \ | |
| 82 | (((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) || \ | |
| 83 | (((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) || \ | |
| 84 | (((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) || \ | |
| 85 | (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \ | |
| 86 | (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ | |
| 87 | (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ | |
| 88 | (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK16)) ) | |
| 381aa07a | 89 | |
| 349c004e CL |
90 | #define cpu_has(c, bit) \ |
| 91 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
| 0f8d2b92 IM |
92 | test_cpu_cap(c, bit)) |
| 93 | ||
| 349c004e CL |
94 | #define this_cpu_has(bit) \ |
| 95 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
| 96 | x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) | |
| 97 | ||
| 381aa07a DH |
98 | /* |
| 99 | * This macro is for detection of features which need kernel | |
| 100 | * infrastructure to be used. It may *not* directly test the CPU | |
| 101 | * itself. Use the cpu_has() family if you want true runtime | |
| 102 | * testing of CPU features, like in hypervisor code where you are | |
| 103 | * supporting a possible guest feature where host support for it | |
| 104 | * is not relevant. | |
| 105 | */ | |
| 106 | #define cpu_feature_enabled(bit) \ | |
| f2cc8e07 | 107 | (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit)) |
| 381aa07a | 108 | |
| 7b11fb51 PA |
109 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
| 110 | ||
| 53756d37 JF |
111 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
| 112 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) | |
| 7d851c8d AK |
113 | #define setup_clear_cpu_cap(bit) do { \ |
| 114 | clear_cpu_cap(&boot_cpu_data, bit); \ | |
| 3e0c3737 | 115 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ |
| 7d851c8d | 116 | } while (0) |
| 404ee5b1 AK |
117 | #define setup_force_cpu_cap(bit) do { \ |
| 118 | set_cpu_cap(&boot_cpu_data, bit); \ | |
| 3e0c3737 | 119 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
| 404ee5b1 | 120 | } while (0) |
| 53756d37 | 121 | |
| 7b11fb51 | 122 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
| 7b11fb51 PA |
123 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
| 124 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) | |
| 7b11fb51 PA |
125 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
| 126 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) | |
| 7b11fb51 PA |
127 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
| 128 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) | |
| 129 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) | |
| 54b6a1bd | 130 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
| 66be8951 | 131 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
| 60488010 | 132 | #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
| 840d2830 | 133 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
| 019c3e7c | 134 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
| 86975101 | 135 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
| 2e5d9c85 | 136 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
| 32e1d0a0 | 137 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
| f1240c00 | 138 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
| 6229ad27 | 139 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
| 66be8951 | 140 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
| 49ab56ac | 141 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
| 362f924b | 142 | /* |
| bc696ca0 | 143 | * Do not add any more of those clumsy macros - use static_cpu_has() for |
| 362f924b BP |
144 | * fast paths and boot_cpu_has() otherwise! |
| 145 | */ | |
| 7b11fb51 | 146 | |
| a362bf9f | 147 | #if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS) |
| a3c8acd0 PA |
148 | /* |
| 149 | * Static testing of CPU features. Used the same as boot_cpu_has(). | |
| a362bf9f BP |
150 | * These will statically patch the target code for additional |
| 151 | * performance. | |
| a3c8acd0 | 152 | */ |
| bc696ca0 | 153 | static __always_inline __pure bool _static_cpu_has(u16 bit) |
| 4a90a99c | 154 | { |
| 2476f2fa | 155 | asm_volatile_goto("1: jmp 6f\n" |
| 4a90a99c | 156 | "2:\n" |
| 4332195c BP |
157 | ".skip -(((5f-4f) - (2b-1b)) > 0) * " |
| 158 | "((5f-4f) - (2b-1b)),0x90\n" | |
| 159 | "3:\n" | |
| 4a90a99c BP |
160 | ".section .altinstructions,\"a\"\n" |
| 161 | " .long 1b - .\n" /* src offset */ | |
| 4332195c | 162 | " .long 4f - .\n" /* repl offset */ |
| 4a90a99c | 163 | " .word %P1\n" /* always replace */ |
| 4332195c BP |
164 | " .byte 3b - 1b\n" /* src len */ |
| 165 | " .byte 5f - 4f\n" /* repl len */ | |
| 166 | " .byte 3b - 2b\n" /* pad len */ | |
| 4a90a99c BP |
167 | ".previous\n" |
| 168 | ".section .altinstr_replacement,\"ax\"\n" | |
| 48c7a250 | 169 | "4: jmp %l[t_no]\n" |
| 4332195c | 170 | "5:\n" |
| 4a90a99c BP |
171 | ".previous\n" |
| 172 | ".section .altinstructions,\"a\"\n" | |
| 173 | " .long 1b - .\n" /* src offset */ | |
| 174 | " .long 0\n" /* no replacement */ | |
| 175 | " .word %P0\n" /* feature bit */ | |
| 4332195c | 176 | " .byte 3b - 1b\n" /* src len */ |
| 4a90a99c | 177 | " .byte 0\n" /* repl len */ |
| 4332195c | 178 | " .byte 0\n" /* pad len */ |
| 4a90a99c | 179 | ".previous\n" |
| 2476f2fa BG |
180 | ".section .altinstr_aux,\"ax\"\n" |
| 181 | "6:\n" | |
| 182 | " testb %[bitnum],%[cap_byte]\n" | |
| 183 | " jnz %l[t_yes]\n" | |
| 184 | " jmp %l[t_no]\n" | |
| 185 | ".previous\n" | |
| 186 | : : "i" (bit), "i" (X86_FEATURE_ALWAYS), | |
| 187 | [bitnum] "i" (1 << (bit & 7)), | |
| 188 | [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3]) | |
| 189 | : : t_yes, t_no); | |
| 190 | t_yes: | |
| 4a90a99c BP |
191 | return true; |
| 192 | t_no: | |
| 193 | return false; | |
| 4a90a99c BP |
194 | } |
| 195 | ||
| bc696ca0 | 196 | #define static_cpu_has(bit) \ |
| 4a90a99c BP |
197 | ( \ |
| 198 | __builtin_constant_p(boot_cpu_has(bit)) ? \ | |
| 199 | boot_cpu_has(bit) : \ | |
| bc696ca0 | 200 | _static_cpu_has(bit) \ |
| 4a90a99c | 201 | ) |
| 1ba4f22c PA |
202 | #else |
| 203 | /* | |
| a362bf9f BP |
204 | * Fall back to dynamic for gcc versions which don't support asm goto. Should be |
| 205 | * a minority now anyway. | |
| 1ba4f22c | 206 | */ |
| 4a90a99c | 207 | #define static_cpu_has(bit) boot_cpu_has(bit) |
| 1ba4f22c | 208 | #endif |
| a3c8acd0 | 209 | |
| 9b13a93d BP |
210 | #define cpu_has_bug(c, bit) cpu_has(c, (bit)) |
| 211 | #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) | |
| 212 | #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) | |
| 65fc985b | 213 | |
| 9b13a93d | 214 | #define static_cpu_has_bug(bit) static_cpu_has((bit)) |
| 9b13a93d | 215 | #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) |
| 65fc985b | 216 | |
| 9b13a93d BP |
217 | #define MAX_CPU_FEATURES (NCAPINTS * 32) |
| 218 | #define cpu_have_feature boot_cpu_has | |
| 2b9c1f03 | 219 | |
| 9b13a93d BP |
220 | #define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" |
| 221 | #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ | |
| 222 | boot_cpu_data.x86_model | |
| 2b9c1f03 | 223 | |
| fa1408e4 | 224 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
| 1965aae3 | 225 | #endif /* _ASM_X86_CPUFEATURE_H */ |