projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 7b11fb51 PA |
1 | /* |
| 2 | * Defines x86 CPU feature bits | |
| 3 | */ | |
| 1965aae3 PA |
4 | #ifndef _ASM_X86_CPUFEATURE_H |
| 5 | #define _ASM_X86_CPUFEATURE_H | |
| 7b11fb51 | 6 | |
| abbf1590 | 7 | #ifndef _ASM_X86_REQUIRED_FEATURES_H |
| 7b11fb51 | 8 | #include <asm/required-features.h> |
| abbf1590 | 9 | #endif |
| 7b11fb51 | 10 | |
| 381aa07a DH |
11 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
| 12 | #include <asm/disabled-features.h> | |
| 13 | #endif | |
| 14 | ||
| 6229ad27 | 15 | #define NCAPINTS 11 /* N 32-bit words worth of info */ |
| 65fc985b | 16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
| 7b11fb51 | 17 | |
| 7414aa41 PA |
18 | /* |
| 19 | * Note: If the comment begins with a quoted string, that string is used | |
| 20 | * in /proc/cpuinfo instead of the macro name. If the string is "", | |
| 21 | * this feature bit is not displayed in /proc/cpuinfo at all. | |
| 22 | */ | |
| 7b11fb51 PA |
23 | |
| 24 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
| 446fd806 FY |
25 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ |
| 26 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | |
| 27 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | |
| 28 | #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ | |
| 29 | #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ | |
| 30 | #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ | |
| 31 | #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ | |
| 32 | #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ | |
| 33 | #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ | |
| 34 | #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ | |
| 35 | #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ | |
| 36 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | |
| 37 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | |
| 38 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | |
| 39 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ | |
| 2798c63e | 40 | /* (plus FCMOVcc, FCOMI with FPU) */ |
| 446fd806 FY |
41 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ |
| 42 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | |
| 43 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | |
| 44 | #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ | |
| 45 | #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ | |
| 46 | #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ | |
| 47 | #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ | |
| 48 | #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | |
| 49 | #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ | |
| 50 | #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ | |
| 51 | #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ | |
| 52 | #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ | |
| 53 | #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ | |
| 54 | #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ | |
| 55 | #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ | |
| 7b11fb51 PA |
56 | |
| 57 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
| 58 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
| 446fd806 FY |
59 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ |
| 60 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ | |
| 61 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | |
| 62 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | |
| 63 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | |
| 64 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | |
| 65 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | |
| 66 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ | |
| 67 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ | |
| 68 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ | |
| 7b11fb51 PA |
69 | |
| 70 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
| 446fd806 FY |
71 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ |
| 72 | #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ | |
| 73 | #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ | |
| 7b11fb51 PA |
74 | |
| 75 | /* Other features, Linux-defined mapping, word 3 */ | |
| 76 | /* This range is used for feature bits which conflict or are synthesized */ | |
| 446fd806 FY |
77 | #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ |
| 78 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
| 79 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
| 80 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
| 7b11fb51 | 81 | /* cpu types for specific tunings: */ |
| 446fd806 FY |
82 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ |
| 83 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | |
| 84 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | |
| 85 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | |
| 86 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | |
| 87 | #define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ | |
| 9b13a93d | 88 | /* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ |
| 446fd806 FY |
89 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ |
| 90 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | |
| 91 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | |
| 92 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ | |
| 93 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ | |
| 94 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ | |
| 95 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ | |
| 96 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ | |
| 9b13a93d | 97 | /* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ |
| 446fd806 FY |
98 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
| 99 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | |
| 100 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ | |
| 101 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | |
| 102 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | |
| 9b13a93d | 103 | /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ |
| 446fd806 FY |
104 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ |
| 105 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ | |
| 106 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ | |
| 107 | #define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */ | |
| 108 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ | |
| 7b11fb51 PA |
109 | |
| 110 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
| 446fd806 FY |
111 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ |
| 112 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | |
| 113 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | |
| 114 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ | |
| 115 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | |
| 116 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | |
| 117 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ | |
| 118 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | |
| 119 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | |
| 120 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | |
| 121 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | |
| 122 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | |
| 123 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ | |
| 124 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | |
| 125 | #define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ | |
| 126 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | |
| 127 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | |
| 128 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | |
| 129 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | |
| 130 | #define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ | |
| 131 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | |
| 132 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | |
| 133 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ | |
| 134 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | |
| 135 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | |
| 136 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ | |
| 137 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | |
| 138 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ | |
| 139 | #define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ | |
| 140 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | |
| 7b11fb51 PA |
141 | |
| 142 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
| 446fd806 FY |
143 | #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ |
| 144 | #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ | |
| 145 | #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | |
| 146 | #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | |
| 147 | #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ | |
| 148 | #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ | |
| 149 | #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ | |
| 150 | #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ | |
| 151 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | |
| 152 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | |
| 7b11fb51 PA |
153 | |
| 154 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
| 446fd806 FY |
155 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ |
| 156 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | |
| 157 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ | |
| 158 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | |
| 159 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | |
| 160 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | |
| 161 | #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ | |
| 162 | #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ | |
| 163 | #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ | |
| 164 | #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ | |
| 165 | #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ | |
| 166 | #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ | |
| 167 | #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ | |
| 168 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | |
| 169 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | |
| 170 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | |
| 171 | #define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ | |
| 172 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | |
| 173 | #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ | |
| 174 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ | |
| 175 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ | |
| 176 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | |
| d6d55f0b | 177 | #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ |
| 446fd806 | 178 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ |
| 7b11fb51 PA |
179 | |
| 180 | /* | |
| 181 | * Auxiliary flags: Linux defined - For features scattered in various | |
| bdc802dc | 182 | * CPUID levels like 0x6, 0xA etc, word 7 |
| 7b11fb51 | 183 | */ |
| 446fd806 FY |
184 | #define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ |
| 185 | #define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ | |
| 186 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ | |
| 187 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | |
| 446fd806 FY |
188 | #define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ |
| 189 | #define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ | |
| 190 | #define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ | |
| 191 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ | |
| 192 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | |
| 7b11fb51 | 193 | |
| bdc802dc | 194 | /* Virtualization flags: Linux defined, word 8 */ |
| 446fd806 FY |
195 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
| 196 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ | |
| 197 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ | |
| 198 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | |
| 199 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | |
| 200 | #define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ | |
| 201 | #define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ | |
| 202 | #define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ | |
| 203 | #define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ | |
| 204 | #define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ | |
| 205 | #define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ | |
| 206 | #define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ | |
| 207 | #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ | |
| 208 | #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ | |
| 209 | #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ | |
| c1118b36 | 210 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
| aeb9c7d6 | 211 | |
| e38e05a8 | 212 | |
| bdc802dc | 213 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ |
| 446fd806 FY |
214 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
| 215 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ | |
| 216 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | |
| 217 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | |
| 218 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | |
| 219 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | |
| 220 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | |
| 221 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | |
| 222 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | |
| 223 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | |
| 224 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ | |
| 225 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ | |
| 226 | #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ | |
| 227 | #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ | |
| 228 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | |
| 229 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ | |
| 230 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ | |
| 231 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | |
| 232 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | |
| bdc802dc | 233 | |
| 6229ad27 FY |
234 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ |
| 235 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ | |
| 236 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ | |
| 237 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ | |
| 238 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ | |
| 239 | ||
| 65fc985b BP |
240 | /* |
| 241 | * BUG word(s) | |
| 242 | */ | |
| 243 | #define X86_BUG(x) (NCAPINTS*32 + (x)) | |
| 244 | ||
| e2604b49 | 245 | #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ |
| 93a829e8 | 246 | #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ |
| c5b41a67 | 247 | #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ |
| 80a208bd BP |
248 | #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ |
| 249 | #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ | |
| 9b13a93d BP |
250 | #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ |
| 251 | #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ | |
| 252 | #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ | |
| e2604b49 | 253 | |
| fa1408e4 PA |
254 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 255 | ||
| a3c8acd0 | 256 | #include <asm/asm.h> |
| fa1408e4 PA |
257 | #include <linux/bitops.h> |
| 258 | ||
| 9def39be | 259 | #ifdef CONFIG_X86_FEATURE_NAMES |
| fa1408e4 PA |
260 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
| 261 | extern const char * const x86_power_flags[32]; | |
| 9def39be JT |
262 | #define X86_CAP_FMT "%s" |
| 263 | #define x86_cap_flag(flag) x86_cap_flags[flag] | |
| 264 | #else | |
| 265 | #define X86_CAP_FMT "%d:%d" | |
| 266 | #define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31) | |
| 267 | #endif | |
| fa1408e4 | 268 | |
| 80a208bd BP |
269 | /* |
| 270 | * In order to save room, we index into this array by doing | |
| 271 | * X86_BUG_<name> - NCAPINTS*32. | |
| 272 | */ | |
| 273 | extern const char * const x86_bug_flags[NBUGINTS*32]; | |
| 274 | ||
| 0f8d2b92 IM |
275 | #define test_cpu_cap(c, bit) \ |
| 276 | test_bit(bit, (unsigned long *)((c)->x86_capability)) | |
| 277 | ||
| 349c004e | 278 | #define REQUIRED_MASK_BIT_SET(bit) \ |
| 7b11fb51 PA |
279 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
| 280 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ | |
| 281 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ | |
| 282 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ | |
| 283 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ | |
| 284 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ | |
| 285 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ | |
| bdc802dc PA |
286 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ |
| 287 | (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ | |
| 349c004e CL |
288 | (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) |
| 289 | ||
| 381aa07a DH |
290 | #define DISABLED_MASK_BIT_SET(bit) \ |
| 291 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \ | |
| 292 | (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \ | |
| 293 | (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \ | |
| 294 | (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \ | |
| 295 | (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \ | |
| 296 | (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \ | |
| 297 | (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \ | |
| 298 | (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \ | |
| 299 | (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \ | |
| 300 | (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) ) | |
| 301 | ||
| 349c004e CL |
302 | #define cpu_has(c, bit) \ |
| 303 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
| 0f8d2b92 IM |
304 | test_cpu_cap(c, bit)) |
| 305 | ||
| 349c004e CL |
306 | #define this_cpu_has(bit) \ |
| 307 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
| 308 | x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) | |
| 309 | ||
| 381aa07a DH |
310 | /* |
| 311 | * This macro is for detection of features which need kernel | |
| 312 | * infrastructure to be used. It may *not* directly test the CPU | |
| 313 | * itself. Use the cpu_has() family if you want true runtime | |
| 314 | * testing of CPU features, like in hypervisor code where you are | |
| 315 | * supporting a possible guest feature where host support for it | |
| 316 | * is not relevant. | |
| 317 | */ | |
| 318 | #define cpu_feature_enabled(bit) \ | |
| 319 | (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \ | |
| 320 | cpu_has(&boot_cpu_data, bit)) | |
| 321 | ||
| 7b11fb51 PA |
322 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
| 323 | ||
| 53756d37 JF |
324 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
| 325 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) | |
| 7d851c8d AK |
326 | #define setup_clear_cpu_cap(bit) do { \ |
| 327 | clear_cpu_cap(&boot_cpu_data, bit); \ | |
| 3e0c3737 | 328 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ |
| 7d851c8d | 329 | } while (0) |
| 404ee5b1 AK |
330 | #define setup_force_cpu_cap(bit) do { \ |
| 331 | set_cpu_cap(&boot_cpu_data, bit); \ | |
| 3e0c3737 | 332 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
| 404ee5b1 | 333 | } while (0) |
| 53756d37 | 334 | |
| 7b11fb51 | 335 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
| 7b11fb51 PA |
336 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
| 337 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) | |
| 338 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) | |
| 7b11fb51 PA |
339 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
| 340 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) | |
| 341 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) | |
| 342 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) | |
| 343 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) | |
| 344 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) | |
| 345 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) | |
| 346 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) | |
| 347 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) | |
| 66be8951 | 348 | #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) |
| 54b6a1bd | 349 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
| 66be8951 | 350 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
| 60488010 | 351 | #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
| 7b11fb51 | 352 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
| 7b11fb51 | 353 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
| 7b11fb51 PA |
354 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
| 355 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) | |
| 356 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) | |
| 357 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) | |
| 358 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) | |
| 359 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) | |
| 360 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) | |
| 361 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) | |
| 362 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) | |
| 363 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) | |
| 364 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) | |
| 365 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) | |
| 840d2830 | 366 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
| 7b11fb51 | 367 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
| 019c3e7c | 368 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
| 86975101 | 369 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
| 2e5d9c85 | 370 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
| f1240c00 | 371 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
| 2a61812a | 372 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
| 32e1d0a0 | 373 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
| f1240c00 | 374 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
| 212b0212 | 375 | #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) |
| 6229ad27 | 376 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
| 66be8951 | 377 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
| 49ab56ac | 378 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
| 0e1227d3 | 379 | #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
| 4979d272 | 380 | #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) |
| e259514e | 381 | #define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB) |
| c43ca509 | 382 | #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) |
| 3824abd1 CL |
383 | #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) |
| 384 | #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) | |
| 5d2bd700 | 385 | #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) |
| 193f3fcb | 386 | #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) |
| d6d55f0b | 387 | #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) |
| 7b11fb51 | 388 | |
| 2fd81864 | 389 | #if __GNUC__ >= 4 |
| 5700f743 | 390 | extern void warn_pre_alternatives(void); |
| 4a90a99c | 391 | extern bool __static_cpu_has_safe(u16 bit); |
| 5700f743 | 392 | |
| a3c8acd0 PA |
393 | /* |
| 394 | * Static testing of CPU features. Used the same as boot_cpu_has(). | |
| 395 | * These are only valid after alternatives have run, but will statically | |
| 396 | * patch the target code for additional performance. | |
| a3c8acd0 | 397 | */ |
| 83a7a2ad | 398 | static __always_inline __pure bool __static_cpu_has(u16 bit) |
| a3c8acd0 | 399 | { |
| 62122fd7 | 400 | #ifdef CC_HAVE_ASM_GOTO |
| 5700f743 BP |
401 | |
| 402 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
| 62122fd7 | 403 | |
| 5700f743 BP |
404 | /* |
| 405 | * Catch too early usage of this before alternatives | |
| 406 | * have run. | |
| 407 | */ | |
| 3f0116c3 | 408 | asm_volatile_goto("1: jmp %l[t_warn]\n" |
| 5700f743 BP |
409 | "2:\n" |
| 410 | ".section .altinstructions,\"a\"\n" | |
| 411 | " .long 1b - .\n" | |
| 412 | " .long 0\n" /* no replacement */ | |
| 413 | " .word %P0\n" /* 1: do replace */ | |
| 414 | " .byte 2b - 1b\n" /* source len */ | |
| 415 | " .byte 0\n" /* replacement len */ | |
| 416 | ".previous\n" | |
| 417 | /* skipping size check since replacement size = 0 */ | |
| 418 | : : "i" (X86_FEATURE_ALWAYS) : : t_warn); | |
| 62122fd7 | 419 | |
| 5700f743 BP |
420 | #endif |
| 421 | ||
| 3f0116c3 | 422 | asm_volatile_goto("1: jmp %l[t_no]\n" |
| a3c8acd0 PA |
423 | "2:\n" |
| 424 | ".section .altinstructions,\"a\"\n" | |
| 59e97e4d AL |
425 | " .long 1b - .\n" |
| 426 | " .long 0\n" /* no replacement */ | |
| 83a7a2ad | 427 | " .word %P0\n" /* feature bit */ |
| a3c8acd0 PA |
428 | " .byte 2b - 1b\n" /* source len */ |
| 429 | " .byte 0\n" /* replacement len */ | |
| a3c8acd0 | 430 | ".previous\n" |
| 83a7a2ad | 431 | /* skipping size check since replacement size = 0 */ |
| a3c8acd0 PA |
432 | : : "i" (bit) : : t_no); |
| 433 | return true; | |
| 434 | t_no: | |
| 435 | return false; | |
| 5700f743 BP |
436 | |
| 437 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
| 438 | t_warn: | |
| 439 | warn_pre_alternatives(); | |
| 440 | return false; | |
| 441 | #endif | |
| 62122fd7 BP |
442 | |
| 443 | #else /* CC_HAVE_ASM_GOTO */ | |
| 444 | ||
| a3c8acd0 PA |
445 | u8 flag; |
| 446 | /* Open-coded due to __stringify() in ALTERNATIVE() */ | |
| 447 | asm volatile("1: movb $0,%0\n" | |
| 448 | "2:\n" | |
| 449 | ".section .altinstructions,\"a\"\n" | |
| 59e97e4d AL |
450 | " .long 1b - .\n" |
| 451 | " .long 3f - .\n" | |
| 83a7a2ad | 452 | " .word %P1\n" /* feature bit */ |
| a3c8acd0 PA |
453 | " .byte 2b - 1b\n" /* source len */ |
| 454 | " .byte 4f - 3f\n" /* replacement len */ | |
| 83a7a2ad PA |
455 | ".previous\n" |
| 456 | ".section .discard,\"aw\",@progbits\n" | |
| 457 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ | |
| a3c8acd0 PA |
458 | ".previous\n" |
| 459 | ".section .altinstr_replacement,\"ax\"\n" | |
| 460 | "3: movb $1,%0\n" | |
| 461 | "4:\n" | |
| 462 | ".previous\n" | |
| 463 | : "=qm" (flag) : "i" (bit)); | |
| 464 | return flag; | |
| 62122fd7 BP |
465 | |
| 466 | #endif /* CC_HAVE_ASM_GOTO */ | |
| a3c8acd0 PA |
467 | } |
| 468 | ||
| 469 | #define static_cpu_has(bit) \ | |
| 470 | ( \ | |
| 471 | __builtin_constant_p(boot_cpu_has(bit)) ? \ | |
| 472 | boot_cpu_has(bit) : \ | |
| 83a7a2ad | 473 | __builtin_constant_p(bit) ? \ |
| a3c8acd0 PA |
474 | __static_cpu_has(bit) : \ |
| 475 | boot_cpu_has(bit) \ | |
| 476 | ) | |
| 4a90a99c BP |
477 | |
| 478 | static __always_inline __pure bool _static_cpu_has_safe(u16 bit) | |
| 479 | { | |
| 62122fd7 | 480 | #ifdef CC_HAVE_ASM_GOTO |
| 4a90a99c BP |
481 | /* |
| 482 | * We need to spell the jumps to the compiler because, depending on the offset, | |
| 483 | * the replacement jump can be bigger than the original jump, and this we cannot | |
| 484 | * have. Thus, we force the jump to the widest, 4-byte, signed relative | |
| 485 | * offset even though the last would often fit in less bytes. | |
| 486 | */ | |
| 3f0116c3 | 487 | asm_volatile_goto("1: .byte 0xe9\n .long %l[t_dynamic] - 2f\n" |
| 4a90a99c BP |
488 | "2:\n" |
| 489 | ".section .altinstructions,\"a\"\n" | |
| 490 | " .long 1b - .\n" /* src offset */ | |
| 491 | " .long 3f - .\n" /* repl offset */ | |
| 492 | " .word %P1\n" /* always replace */ | |
| 493 | " .byte 2b - 1b\n" /* src len */ | |
| 494 | " .byte 4f - 3f\n" /* repl len */ | |
| 495 | ".previous\n" | |
| 496 | ".section .altinstr_replacement,\"ax\"\n" | |
| 497 | "3: .byte 0xe9\n .long %l[t_no] - 2b\n" | |
| 498 | "4:\n" | |
| 499 | ".previous\n" | |
| 500 | ".section .altinstructions,\"a\"\n" | |
| 501 | " .long 1b - .\n" /* src offset */ | |
| 502 | " .long 0\n" /* no replacement */ | |
| 503 | " .word %P0\n" /* feature bit */ | |
| 504 | " .byte 2b - 1b\n" /* src len */ | |
| 505 | " .byte 0\n" /* repl len */ | |
| 506 | ".previous\n" | |
| 507 | : : "i" (bit), "i" (X86_FEATURE_ALWAYS) | |
| 508 | : : t_dynamic, t_no); | |
| 509 | return true; | |
| 510 | t_no: | |
| 511 | return false; | |
| 512 | t_dynamic: | |
| 513 | return __static_cpu_has_safe(bit); | |
| 62122fd7 | 514 | #else |
| 4a90a99c BP |
515 | u8 flag; |
| 516 | /* Open-coded due to __stringify() in ALTERNATIVE() */ | |
| 517 | asm volatile("1: movb $2,%0\n" | |
| 518 | "2:\n" | |
| 519 | ".section .altinstructions,\"a\"\n" | |
| 520 | " .long 1b - .\n" /* src offset */ | |
| 521 | " .long 3f - .\n" /* repl offset */ | |
| 522 | " .word %P2\n" /* always replace */ | |
| 523 | " .byte 2b - 1b\n" /* source len */ | |
| 524 | " .byte 4f - 3f\n" /* replacement len */ | |
| 525 | ".previous\n" | |
| 526 | ".section .discard,\"aw\",@progbits\n" | |
| 527 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ | |
| 528 | ".previous\n" | |
| 529 | ".section .altinstr_replacement,\"ax\"\n" | |
| 530 | "3: movb $0,%0\n" | |
| 531 | "4:\n" | |
| 532 | ".previous\n" | |
| 533 | ".section .altinstructions,\"a\"\n" | |
| 534 | " .long 1b - .\n" /* src offset */ | |
| 535 | " .long 5f - .\n" /* repl offset */ | |
| 536 | " .word %P1\n" /* feature bit */ | |
| 537 | " .byte 4b - 3b\n" /* src len */ | |
| 538 | " .byte 6f - 5f\n" /* repl len */ | |
| 539 | ".previous\n" | |
| 540 | ".section .discard,\"aw\",@progbits\n" | |
| 541 | " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */ | |
| 542 | ".previous\n" | |
| 543 | ".section .altinstr_replacement,\"ax\"\n" | |
| 544 | "5: movb $1,%0\n" | |
| 545 | "6:\n" | |
| 546 | ".previous\n" | |
| 547 | : "=qm" (flag) | |
| 548 | : "i" (bit), "i" (X86_FEATURE_ALWAYS)); | |
| 549 | return (flag == 2 ? __static_cpu_has_safe(bit) : flag); | |
| 62122fd7 | 550 | #endif /* CC_HAVE_ASM_GOTO */ |
| 4a90a99c BP |
551 | } |
| 552 | ||
| 553 | #define static_cpu_has_safe(bit) \ | |
| 554 | ( \ | |
| 555 | __builtin_constant_p(boot_cpu_has(bit)) ? \ | |
| 556 | boot_cpu_has(bit) : \ | |
| 557 | _static_cpu_has_safe(bit) \ | |
| 558 | ) | |
| 1ba4f22c PA |
559 | #else |
| 560 | /* | |
| 561 | * gcc 3.x is too stupid to do the static test; fall back to dynamic. | |
| 562 | */ | |
| 4a90a99c BP |
563 | #define static_cpu_has(bit) boot_cpu_has(bit) |
| 564 | #define static_cpu_has_safe(bit) boot_cpu_has(bit) | |
| 1ba4f22c | 565 | #endif |
| a3c8acd0 | 566 | |
| 9b13a93d BP |
567 | #define cpu_has_bug(c, bit) cpu_has(c, (bit)) |
| 568 | #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) | |
| 569 | #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) | |
| 65fc985b | 570 | |
| 9b13a93d BP |
571 | #define static_cpu_has_bug(bit) static_cpu_has((bit)) |
| 572 | #define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit)) | |
| 573 | #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) | |
| 65fc985b | 574 | |
| 9b13a93d BP |
575 | #define MAX_CPU_FEATURES (NCAPINTS * 32) |
| 576 | #define cpu_have_feature boot_cpu_has | |
| 2b9c1f03 | 577 | |
| 9b13a93d BP |
578 | #define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" |
| 579 | #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ | |
| 580 | boot_cpu_data.x86_model | |
| 2b9c1f03 | 581 | |
| fa1408e4 | 582 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
| 1965aae3 | 583 | #endif /* _ASM_X86_CPUFEATURE_H */ |