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1 | #ifndef _ASM_X86_CPUFEATURES_H |
2 | #define _ASM_X86_CPUFEATURES_H | |
3 | ||
4 | #ifndef _ASM_X86_REQUIRED_FEATURES_H | |
5 | #include <asm/required-features.h> | |
6 | #endif | |
7 | ||
8 | #ifndef _ASM_X86_DISABLED_FEATURES_H | |
9 | #include <asm/disabled-features.h> | |
10 | #endif | |
11 | ||
12 | /* | |
13 | * Defines x86 CPU feature bits | |
14 | */ | |
71faad43 | 15 | #define NCAPINTS 18 /* N 32-bit words worth of info */ |
cd4d09ec BP |
16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
17 | ||
18 | /* | |
19 | * Note: If the comment begins with a quoted string, that string is used | |
20 | * in /proc/cpuinfo instead of the macro name. If the string is "", | |
21 | * this feature bit is not displayed in /proc/cpuinfo at all. | |
22 | */ | |
23 | ||
24 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
25 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ | |
26 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ | |
27 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ | |
28 | #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ | |
29 | #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ | |
30 | #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ | |
31 | #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ | |
32 | #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ | |
33 | #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ | |
34 | #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ | |
35 | #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ | |
36 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ | |
37 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ | |
38 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ | |
39 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ | |
40 | /* (plus FCMOVcc, FCOMI with FPU) */ | |
41 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ | |
42 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ | |
43 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ | |
44 | #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ | |
45 | #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ | |
46 | #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ | |
47 | #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ | |
48 | #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ | |
49 | #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ | |
50 | #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ | |
51 | #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ | |
52 | #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ | |
53 | #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ | |
54 | #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ | |
55 | #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ | |
56 | ||
57 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
58 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
59 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ | |
60 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ | |
61 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ | |
62 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ | |
63 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ | |
64 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ | |
65 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ | |
66 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ | |
67 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ | |
68 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ | |
69 | ||
70 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
71 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ | |
72 | #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ | |
73 | #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ | |
74 | ||
75 | /* Other features, Linux-defined mapping, word 3 */ | |
76 | /* This range is used for feature bits which conflict or are synthesized */ | |
77 | #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ | |
78 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
79 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
80 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
81 | /* cpu types for specific tunings: */ | |
82 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ | |
83 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ | |
84 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ | |
85 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ | |
86 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ | |
87 | #define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ | |
8a284c06 | 88 | #define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */ |
cd4d09ec BP |
89 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ |
90 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ | |
91 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ | |
92 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ | |
93 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ | |
94 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ | |
95 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ | |
96 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ | |
01fe03ff | 97 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ |
cd4d09ec BP |
98 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
99 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ | |
100 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ | |
101 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ | |
102 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ | |
78d1b296 | 103 | #define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */ |
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104 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ |
105 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ | |
106 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ | |
cd4d09ec | 107 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ |
47c95a46 | 108 | #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ |
cd4d09ec BP |
109 | |
110 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
111 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ | |
112 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ | |
113 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ | |
114 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ | |
115 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | |
116 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ | |
117 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ | |
118 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ | |
119 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ | |
120 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ | |
121 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ | |
122 | #define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */ | |
123 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ | |
124 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ | |
125 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ | |
126 | #define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ | |
127 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ | |
128 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ | |
129 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ | |
130 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ | |
131 | #define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ | |
132 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ | |
133 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ | |
134 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ | |
135 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ | |
136 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | |
137 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ | |
138 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ | |
139 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ | |
140 | #define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ | |
141 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ | |
142 | ||
143 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
144 | #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ | |
145 | #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ | |
146 | #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | |
147 | #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | |
148 | #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ | |
149 | #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ | |
150 | #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ | |
151 | #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ | |
152 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ | |
153 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ | |
154 | ||
155 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
156 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ | |
157 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ | |
158 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ | |
159 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ | |
160 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ | |
161 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ | |
162 | #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ | |
163 | #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ | |
164 | #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ | |
165 | #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ | |
166 | #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ | |
167 | #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ | |
168 | #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ | |
169 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ | |
170 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ | |
171 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ | |
172 | #define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ | |
173 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ | |
174 | #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ | |
175 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ | |
176 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ | |
177 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ | |
178 | #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ | |
8a224261 | 179 | #define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ |
910448bb | 180 | #define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ |
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181 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ |
182 | ||
183 | /* | |
184 | * Auxiliary flags: Linux defined - For features scattered in various | |
185 | * CPUID levels like 0x6, 0xA etc, word 7. | |
186 | * | |
187 | * Reuse free bits when adding new feature flags! | |
188 | */ | |
3bba73b1 | 189 | #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */ |
90218ac7 | 190 | #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */ |
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191 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
192 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ | |
4ab15864 FY |
193 | #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */ |
194 | #define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */ | |
195 | #define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */ | |
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196 | |
197 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ | |
198 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ | |
872cbefd | 199 | #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ |
cd4d09ec | 200 | |
3f5a7896 | 201 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ |
cd4d09ec | 202 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
82148993 PL |
203 | #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ |
204 | #define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ | |
cd4d09ec | 205 | |
ab66a33b VS |
206 | #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ |
207 | ||
cd4d09ec BP |
208 | /* Virtualization flags: Linux defined, word 8 */ |
209 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ | |
210 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ | |
211 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ | |
212 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ | |
213 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ | |
214 | ||
215 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ | |
216 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ | |
217 | ||
218 | ||
219 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ | |
220 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ | |
221 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ | |
222 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ | |
223 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ | |
224 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ | |
225 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ | |
226 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ | |
227 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ | |
228 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ | |
229 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ | |
230 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ | |
231 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ | |
4ab15864 | 232 | #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ |
cd4d09ec | 233 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ |
d0500494 | 234 | #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ |
cd4d09ec BP |
235 | #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ |
236 | #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ | |
237 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ | |
a8d9df5a | 238 | #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ |
cd4d09ec BP |
239 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ |
240 | #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ | |
241 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ | |
242 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ | |
243 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ | |
244 | #define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ | |
d0500494 FY |
245 | #define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */ |
246 | #define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */ | |
cd4d09ec BP |
247 | |
248 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ | |
249 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ | |
250 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ | |
251 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ | |
252 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ | |
253 | ||
254 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ | |
255 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ | |
256 | ||
257 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ | |
258 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ | |
33c3cc7a VS |
259 | #define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ |
260 | #define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ | |
cd4d09ec BP |
261 | |
262 | /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ | |
263 | #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ | |
aaf24884 | 264 | #define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */ |
cd4d09ec BP |
265 | |
266 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ | |
267 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ | |
268 | #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ | |
269 | #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ | |
270 | #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ | |
271 | #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ | |
272 | #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ | |
273 | #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ | |
274 | #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ | |
275 | #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ | |
276 | #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ | |
277 | ||
278 | /* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ | |
279 | #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ | |
280 | #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ | |
281 | #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ | |
282 | #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ | |
283 | #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ | |
284 | #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ | |
285 | #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ | |
286 | #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ | |
287 | #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ | |
288 | #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ | |
289 | #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ | |
5442c269 | 290 | #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ |
d837312d | 291 | #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ |
cd4d09ec | 292 | |
0d47638f | 293 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ |
a8d9df5a | 294 | #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ |
0d47638f DH |
295 | #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ |
296 | #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ | |
06b35d93 | 297 | #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ |
6fb89569 KS |
298 | #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ |
299 | #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ | |
0d47638f | 300 | |
71faad43 YG |
301 | /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ |
302 | #define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ | |
303 | #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ | |
304 | #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ | |
305 | ||
cd4d09ec BP |
306 | /* |
307 | * BUG word(s) | |
308 | */ | |
309 | #define X86_BUG(x) (NCAPINTS*32 + (x)) | |
310 | ||
311 | #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ | |
312 | #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ | |
313 | #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ | |
314 | #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ | |
315 | #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ | |
316 | #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ | |
317 | #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ | |
318 | #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ | |
319 | #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ | |
58a5aac5 AL |
320 | #ifdef CONFIG_X86_32 |
321 | /* | |
322 | * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional | |
323 | * to avoid confusion. | |
324 | */ | |
325 | #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */ | |
326 | #endif | |
8709ed4d DH |
327 | #define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */ |
328 | #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */ | |
08e237fa | 329 | #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */ |
3344ed30 | 330 | #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */ |
cd4d09ec | 331 | #endif /* _ASM_X86_CPUFEATURES_H */ |