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1965aae3 PA |
1 | #ifndef _ASM_X86_DEBUGREG_H |
2 | #define _ASM_X86_DEBUGREG_H | |
21ebddd3 TG |
3 | |
4 | ||
5 | /* Indicate the register numbers for a number of the specific | |
6 | debug registers. Registers 0-3 contain the addresses we wish to trap on */ | |
7 | #define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */ | |
8 | #define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */ | |
9 | ||
10 | #define DR_STATUS 6 /* u_debugreg[DR_STATUS] */ | |
11 | #define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */ | |
12 | ||
13 | /* Define a few things for the status register. We can use this to determine | |
14 | which debugging register was responsible for the trap. The other bits | |
15 | are either reserved or not of interest to us. */ | |
16 | ||
40f9249a P |
17 | /* Define reserved bits in DR6 which are always set to 1 */ |
18 | #define DR6_RESERVED (0xFFFF0FF0) | |
19 | ||
21ebddd3 TG |
20 | #define DR_TRAP0 (0x1) /* db0 */ |
21 | #define DR_TRAP1 (0x2) /* db1 */ | |
22 | #define DR_TRAP2 (0x4) /* db2 */ | |
23 | #define DR_TRAP3 (0x8) /* db3 */ | |
b332828c | 24 | #define DR_TRAP_BITS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3) |
21ebddd3 TG |
25 | |
26 | #define DR_STEP (0x4000) /* single-step */ | |
27 | #define DR_SWITCH (0x8000) /* task switch */ | |
28 | ||
29 | /* Now define a bunch of things for manipulating the control register. | |
30 | The top two bytes of the control register consist of 4 fields of 4 | |
31 | bits - each field corresponds to one of the four debug registers, | |
32 | and indicates what types of access we trap on, and how large the data | |
33 | field is that we are looking at */ | |
34 | ||
35 | #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */ | |
36 | #define DR_CONTROL_SIZE 4 /* 4 control bits per register */ | |
37 | ||
38 | #define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */ | |
39 | #define DR_RW_WRITE (0x1) | |
40 | #define DR_RW_READ (0x3) | |
41 | ||
42 | #define DR_LEN_1 (0x0) /* Settings for data length to trap on */ | |
43 | #define DR_LEN_2 (0x4) | |
44 | #define DR_LEN_4 (0xC) | |
45 | #define DR_LEN_8 (0x8) | |
46 | ||
47 | /* The low byte to the control register determine which registers are | |
48 | enabled. There are 4 fields of two bits. One bit is "local", meaning | |
49 | that the processor will reset the bit after a task switch and the other | |
50 | is global meaning that we have to explicitly reset the bit. With linux, | |
51 | you can use either one, since we explicitly zero the register when we enter | |
52 | kernel mode. */ | |
53 | ||
54 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */ | |
55 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */ | |
b332828c P |
56 | #define DR_LOCAL_ENABLE (0x1) /* Local enable for reg 0 */ |
57 | #define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */ | |
21ebddd3 TG |
58 | #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */ |
59 | ||
60 | #define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */ | |
61 | #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */ | |
62 | ||
63 | /* The second byte to the control register has a few special things. | |
64 | We can slow the instruction pipeline for instructions coming via the | |
65 | gdt or the ldt if we want to. I am not sure why this is an advantage */ | |
66 | ||
67 | #ifdef __i386__ | |
68 | #define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */ | |
96a388de | 69 | #else |
21ebddd3 TG |
70 | #define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */ |
71 | #endif | |
72 | ||
73 | #define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */ | |
74 | #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */ | |
75 | ||
b332828c P |
76 | /* |
77 | * HW breakpoint additions | |
78 | */ | |
79 | #ifdef __KERNEL__ | |
80 | ||
28b4e0d8 | 81 | DECLARE_PER_CPU(unsigned long, cpu_dr7); |
b332828c | 82 | |
b332828c P |
83 | static inline void hw_breakpoint_disable(void) |
84 | { | |
85 | /* Zero the control register for HW Breakpoint */ | |
86 | set_debugreg(0UL, 7); | |
87 | ||
88 | /* Zero-out the individual HW breakpoint address registers */ | |
89 | set_debugreg(0UL, 0); | |
90 | set_debugreg(0UL, 1); | |
91 | set_debugreg(0UL, 2); | |
92 | set_debugreg(0UL, 3); | |
93 | } | |
94 | ||
59d8eb53 FW |
95 | static inline int hw_breakpoint_active(void) |
96 | { | |
28b4e0d8 | 97 | return __get_cpu_var(cpu_dr7) & DR_GLOBAL_ENABLE_MASK; |
59d8eb53 FW |
98 | } |
99 | ||
9f6b3c2c FW |
100 | extern void aout_dump_debugregs(struct user *dump); |
101 | ||
24f1e32c | 102 | extern void hw_breakpoint_restore(void); |
24f1e32c | 103 | |
b332828c P |
104 | #endif /* __KERNEL__ */ |
105 | ||
1965aae3 | 106 | #endif /* _ASM_X86_DEBUGREG_H */ |