[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / desc.h

#ifndef _ASM_X86_DESC_H
#define _ASM_X86_DESC_H

#include <asm/desc_defs.h>
#include <asm/ldt.h>
#include <asm/mmu.h>
#include <asm/fixmap.h>

#include <linux/smp.h>
#include <linux/percpu.h>

static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
{
	desc->limit0		= info->limit & 0x0ffff;

	desc->base0		= (info->base_addr & 0x0000ffff);
	desc->base1		= (info->base_addr & 0x00ff0000) >> 16;

	desc->type		= (info->read_exec_only ^ 1) << 1;
	desc->type	       |= info->contents << 2;

	desc->s			= 1;
	desc->dpl		= 0x3;
	desc->p			= info->seg_not_present ^ 1;
	desc->limit		= (info->limit & 0xf0000) >> 16;
	desc->avl		= info->useable;
	desc->d			= info->seg_32bit;
	desc->g			= info->limit_in_pages;

	desc->base2		= (info->base_addr & 0xff000000) >> 24;
	/*
	 * Don't allow setting of the lm bit. It would confuse
	 * user_64bit_mode and would get overridden by sysret anyway.
	 */
	desc->l			= 0;
}

extern struct desc_ptr idt_descr;
extern gate_desc idt_table[];
extern const struct desc_ptr debug_idt_descr;
extern gate_desc debug_idt_table[];

struct gdt_page {
	struct desc_struct gdt[GDT_ENTRIES];
} __attribute__((aligned(PAGE_SIZE)));

DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);

/* Provide the original GDT */
static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
{
	return per_cpu(gdt_page, cpu).gdt;
}

/* Provide the current original GDT */
static inline struct desc_struct *get_current_gdt_rw(void)
{
	return this_cpu_ptr(&gdt_page)->gdt;
}

/* Get the fixmap index for a specific processor */
static inline unsigned int get_cpu_gdt_ro_index(int cpu)
{
	return FIX_GDT_REMAP_BEGIN + cpu;
}

/* Provide the fixmap address of the remapped GDT */
static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
{
	unsigned int idx = get_cpu_gdt_ro_index(cpu);
	return (struct desc_struct *)__fix_to_virt(idx);
}

/* Provide the current read-only GDT */
static inline struct desc_struct *get_current_gdt_ro(void)
{
	return get_cpu_gdt_ro(smp_processor_id());
}

/* Provide the physical address of the GDT page. */
static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
{
	return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
}

#ifdef CONFIG_X86_64

static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate->offset_low	= PTR_LOW(func);
	gate->segment		= __KERNEL_CS;
	gate->ist		= ist;
	gate->p			= 1;
	gate->dpl		= dpl;
	gate->zero0		= 0;
	gate->zero1		= 0;
	gate->type		= type;
	gate->offset_middle	= PTR_MIDDLE(func);
	gate->offset_high	= PTR_HIGH(func);
}

#else
static inline void pack_gate(gate_desc *gate, unsigned char type,
			     unsigned long base, unsigned dpl, unsigned flags,
			     unsigned short seg)
{
	gate->a = (seg << 16) | (base & 0xffff);
	gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);
}

#endif

static inline int desc_empty(const void *ptr)
{
	const u32 *desc = ptr;

	return !(desc[0] | desc[1]);
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define load_TR_desc()				native_load_tr_desc()
#define load_gdt(dtr)				native_load_gdt(dtr)
#define load_idt(dtr)				native_load_idt(dtr)
#define load_tr(tr)				asm volatile("ltr %0"::"m" (tr))
#define load_ldt(ldt)				asm volatile("lldt %0"::"m" (ldt))

#define store_gdt(dtr)				native_store_gdt(dtr)
#define store_idt(dtr)				native_store_idt(dtr)
#define store_tr(tr)				(tr = native_store_tr())

#define load_TLS(t, cpu)			native_load_tls(t, cpu)
#define set_ldt					native_set_ldt

#define write_ldt_entry(dt, entry, desc)	native_write_ldt_entry(dt, entry, desc)
#define write_gdt_entry(dt, entry, desc, type)	native_write_gdt_entry(dt, entry, desc, type)
#define write_idt_entry(dt, entry, g)		native_write_idt_entry(dt, entry, g)

static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
{
}

static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
{
}
#endif	/* CONFIG_PARAVIRT */

#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))

static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
{
	memcpy(&idt[entry], gate, sizeof(*gate));
}

static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
{
	memcpy(&ldt[entry], desc, 8);
}

static inline void
native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
{
	unsigned int size;

	switch (type) {
	case DESC_TSS:	size = sizeof(tss_desc);	break;
	case DESC_LDT:	size = sizeof(ldt_desc);	break;
	default:	size = sizeof(*gdt);		break;
	}

	memcpy(&gdt[entry], desc, size);
}

static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
				   unsigned long limit, unsigned char type,
				   unsigned char flags)
{
	desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
	desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
		(limit & 0x000f0000) | ((type & 0xff) << 8) |
		((flags & 0xf) << 20);
	desc->p = 1;
}


static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
{
#ifdef CONFIG_X86_64
	struct ldttss_desc64 *desc = d;

	memset(desc, 0, sizeof(*desc));

	desc->limit0		= size & 0xFFFF;
	desc->base0		= PTR_LOW(addr);
	desc->base1		= PTR_MIDDLE(addr) & 0xFF;
	desc->type		= type;
	desc->p			= 1;
	desc->limit1		= (size >> 16) & 0xF;
	desc->base2		= (PTR_MIDDLE(addr) >> 8) & 0xFF;
	desc->base3		= PTR_HIGH(addr);
#else
	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
#endif
}

static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
{
	struct desc_struct *d = get_cpu_gdt_rw(cpu);
	tss_desc tss;

	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
			      __KERNEL_TSS_LIMIT);
	write_gdt_entry(d, entry, &tss, DESC_TSS);
}

#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)

static inline void native_set_ldt(const void *addr, unsigned int entries)
{
	if (likely(entries == 0))
		asm volatile("lldt %w0"::"q" (0));
	else {
		unsigned cpu = smp_processor_id();
		ldt_desc ldt;

		set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
				      entries * LDT_ENTRY_SIZE - 1);
		write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
				&ldt, DESC_LDT);
		asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
	}
}

static inline void native_load_gdt(const struct desc_ptr *dtr)
{
	asm volatile("lgdt %0"::"m" (*dtr));
}

static inline void native_load_idt(const struct desc_ptr *dtr)
{
	asm volatile("lidt %0"::"m" (*dtr));
}

static inline void native_store_gdt(struct desc_ptr *dtr)
{
	asm volatile("sgdt %0":"=m" (*dtr));
}

static inline void native_store_idt(struct desc_ptr *dtr)
{
	asm volatile("sidt %0":"=m" (*dtr));
}

/*
 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
 * a read-only remapping. To prevent a page fault, the GDT is switched to the
 * original writeable version when needed.
 */
#ifdef CONFIG_X86_64
static inline void native_load_tr_desc(void)
{
	struct desc_ptr gdt;
	int cpu = raw_smp_processor_id();
	bool restore = 0;
	struct desc_struct *fixmap_gdt;

	native_store_gdt(&gdt);
	fixmap_gdt = get_cpu_gdt_ro(cpu);

	/*
	 * If the current GDT is the read-only fixmap, swap to the original
	 * writeable version. Swap back at the end.
	 */
	if (gdt.address == (unsigned long)fixmap_gdt) {
		load_direct_gdt(cpu);
		restore = 1;
	}
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	if (restore)
		load_fixmap_gdt(cpu);
}
#else
static inline void native_load_tr_desc(void)
{
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
}
#endif

static inline unsigned long native_store_tr(void)
{
	unsigned long tr;

	asm volatile("str %0":"=r" (tr));

	return tr;
}

static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
{
	struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
	unsigned int i;

	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
}

DECLARE_PER_CPU(bool, __tss_limit_invalid);

static inline void force_reload_TR(void)
{
	struct desc_struct *d = get_current_gdt_rw();
	tss_desc tss;

	memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));

	/*
	 * LTR requires an available TSS, and the TSS is currently
	 * busy.  Make it be available so that LTR will work.
	 */
	tss.type = DESC_TSS;
	write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);

	load_TR_desc();
	this_cpu_write(__tss_limit_invalid, false);
}

/*
 * Call this if you need the TSS limit to be correct, which should be the case
 * if and only if you have TIF_IO_BITMAP set or you're switching to a task
 * with TIF_IO_BITMAP set.
 */
static inline void refresh_tss_limit(void)
{
	DEBUG_LOCKS_WARN_ON(preemptible());

	if (unlikely(this_cpu_read(__tss_limit_invalid)))
		force_reload_TR();
}

/*
 * If you do something evil that corrupts the cached TSS limit (I'm looking
 * at you, VMX exits), call this function.
 *
 * The optimization here is that the TSS limit only matters for Linux if the
 * IO bitmap is in use.  If the TSS limit gets forced to its minimum value,
 * everything works except that IO bitmap will be ignored and all CPL 3 IO
 * instructions will #GP, which is exactly what we want for normal tasks.
 */
static inline void invalidate_tss_limit(void)
{
	DEBUG_LOCKS_WARN_ON(preemptible());

	if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
		force_reload_TR();
	else
		this_cpu_write(__tss_limit_invalid, true);
}

/* This intentionally ignores lm, since 32-bit apps don't have that field. */
#define LDT_empty(info)					\
	((info)->base_addr		== 0	&&	\
	 (info)->limit			== 0	&&	\
	 (info)->contents		== 0	&&	\
	 (info)->read_exec_only		== 1	&&	\
	 (info)->seg_32bit		== 0	&&	\
	 (info)->limit_in_pages		== 0	&&	\
	 (info)->seg_not_present	== 1	&&	\
	 (info)->useable		== 0)

/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
static inline bool LDT_zero(const struct user_desc *info)
{
	return (info->base_addr		== 0 &&
		info->limit		== 0 &&
		info->contents		== 0 &&
		info->read_exec_only	== 0 &&
		info->seg_32bit		== 0 &&
		info->limit_in_pages	== 0 &&
		info->seg_not_present	== 0 &&
		info->useable		== 0);
}

static inline void clear_LDT(void)
{
	set_ldt(NULL, 0);
}

static inline unsigned long get_desc_base(const struct desc_struct *desc)
{
	return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
}

static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
{
	desc->base0 = base & 0xffff;
	desc->base1 = (base >> 16) & 0xff;
	desc->base2 = (base >> 24) & 0xff;
}

static inline unsigned long get_desc_limit(const struct desc_struct *desc)
{
	return desc->limit0 | (desc->limit << 16);
}

static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
{
	desc->limit0 = limit & 0xffff;
	desc->limit = (limit >> 16) & 0xf;
}

#ifdef CONFIG_X86_64
static inline void set_nmi_gate(int gate, void *addr)
{
	gate_desc s;

	pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
	write_idt_entry(debug_idt_table, gate, &s);
}
#endif

#ifdef CONFIG_TRACING
extern struct desc_ptr trace_idt_descr;
extern gate_desc trace_idt_table[];
static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
{
	write_idt_entry(trace_idt_table, entry, gate);
}

static inline void _trace_set_gate(int gate, unsigned type, void *addr,
				   unsigned dpl, unsigned ist, unsigned seg)
{
	gate_desc s;

	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	/*
	 * does not need to be atomic because it is only done once at
	 * setup time
	 */
	write_trace_idt_entry(gate, &s);
}
#else
static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
{
}

#define _trace_set_gate(gate, type, addr, dpl, ist, seg)
#endif

static inline void _set_gate(int gate, unsigned type, void *addr,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate_desc s;

	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	/*
	 * does not need to be atomic because it is only done once at
	 * setup time
	 */
	write_idt_entry(idt_table, gate, &s);
	write_trace_idt_entry(gate, &s);
}

/*
 * This needs to use 'idt_table' rather than 'idt', and
 * thus use the _nonmapped_ version of the IDT, as the
 * Pentium F0 0F bugfix can have resulted in the mapped
 * IDT being write-protected.
 */
#define set_intr_gate_notrace(n, addr)					\
	do {								\
		BUG_ON((unsigned)n > 0xFF);				\
		_set_gate(n, GATE_INTERRUPT, (void *)addr, 0, 0,	\
			  __KERNEL_CS);					\
	} while (0)

#define set_intr_gate(n, addr)						\
	do {								\
		set_intr_gate_notrace(n, addr);				\
		_trace_set_gate(n, GATE_INTERRUPT, (void *)trace_##addr,\
				0, 0, __KERNEL_CS);			\
	} while (0)

extern int first_system_vector;
/* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
extern unsigned long used_vectors[];

static inline void alloc_system_vector(int vector)
{
	if (!test_bit(vector, used_vectors)) {
		set_bit(vector, used_vectors);
		if (first_system_vector > vector)
			first_system_vector = vector;
	} else {
		BUG();
	}
}

#define alloc_intr_gate(n, addr)				\
	do {							\
		alloc_system_vector(n);				\
		set_intr_gate(n, addr);				\
	} while (0)

/*
 * This routine sets up an interrupt gate at directory privilege level 3.
 */
static inline void set_system_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_system_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
}

static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
}

static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
}

static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
}

#ifdef CONFIG_X86_64
DECLARE_PER_CPU(u32, debug_idt_ctr);
static inline bool is_debug_idt_enabled(void)
{
	if (this_cpu_read(debug_idt_ctr))
		return true;

	return false;
}

static inline void load_debug_idt(void)
{
	load_idt((const struct desc_ptr *)&debug_idt_descr);
}
#else
static inline bool is_debug_idt_enabled(void)
{
	return false;
}

static inline void load_debug_idt(void)
{
}
#endif

#ifdef CONFIG_TRACING
extern atomic_t trace_idt_ctr;
static inline bool is_trace_idt_enabled(void)
{
	if (atomic_read(&trace_idt_ctr))
		return true;

	return false;
}

static inline void load_trace_idt(void)
{
	load_idt((const struct desc_ptr *)&trace_idt_descr);
}
#else
static inline bool is_trace_idt_enabled(void)
{
	return false;
}

static inline void load_trace_idt(void)
{
}
#endif

/*
 * The load_current_idt() must be called with interrupts disabled
 * to avoid races. That way the IDT will always be set back to the expected
 * descriptor. It's also called when a CPU is being initialized, and
 * that doesn't need to disable interrupts, as nothing should be
 * bothering the CPU then.
 */
static inline void load_current_idt(void)
{
	if (is_debug_idt_enabled())
		load_debug_idt();
	else if (is_trace_idt_enabled())
		load_trace_idt();
	else
		load_idt((const struct desc_ptr *)&idt_descr);
}
#endif /* _ASM_X86_DESC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_DESC_H
1965aae3 PA	2	#define _ASM_X86_DESC_H
80fbb69a	3
80fbb69a GOC	4	#include <asm/desc_defs.h>
80fbb69a GOC	5	#include <asm/ldt.h>
881c2975	6	#include <asm/mmu.h>
69218e47	7	#include <asm/fixmap.h>
9a3865b1	8
54cd0eac	9	#include <linux/smp.h>
c6ae41e7	10	#include <linux/percpu.h>
80fbb69a	11
9a3865b1 IM	12	static inline void fill_ldt(struct desc_struct desc, const struct user_desc info)
	13	{
	14	desc->limit0 = info->limit & 0x0ffff;
	15
	16	desc->base0 = (info->base_addr & 0x0000ffff);
	17	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	18
	19	desc->type = (info->read_exec_only ^ 1) << 1;
	20	desc->type \|= info->contents << 2;
	21
	22	desc->s = 1;
	23	desc->dpl = 0x3;
	24	desc->p = info->seg_not_present ^ 1;
	25	desc->limit = (info->limit & 0xf0000) >> 16;
	26	desc->avl = info->useable;
	27	desc->d = info->seg_32bit;
	28	desc->g = info->limit_in_pages;
	29
	30	desc->base2 = (info->base_addr & 0xff000000) >> 24;
64f53a04	31	/*
318f5a2a AL	32	* Don't allow setting of the lm bit. It would confuse
318f5a2a AL	33	* user_64bit_mode and would get overridden by sysret anyway.
64f53a04	34	*/
9a3865b1	35	desc->l = 0;
80fbb69a GOC	36	}
80fbb69a GOC	37
881c2975 GOC	38	extern struct desc_ptr idt_descr;
881c2975 GOC	39	extern gate_desc idt_table[];
404f6aac	40	extern const struct desc_ptr debug_idt_descr;
629f4f9d	41	extern gate_desc debug_idt_table[];
80fbb69a	42
a939098a GC	43	struct gdt_page {
	44	struct desc_struct gdt[GDT_ENTRIES];
	45	} __attribute__((aligned(PAGE_SIZE)));
9a3865b1	46
9b8de747	47	DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
a939098a	48
69218e47 TG	49	/* Provide the original GDT */
69218e47 TG	50	static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
a939098a GC	51	{
	52	return per_cpu(gdt_page, cpu).gdt;
	53	}
	54
69218e47 TG	55	/* Provide the current original GDT */
	56	static inline struct desc_struct *get_current_gdt_rw(void)
	57	{
	58	return this_cpu_ptr(&gdt_page)->gdt;
	59	}
	60
69218e47 TG	61	/* Get the fixmap index for a specific processor */
	62	static inline unsigned int get_cpu_gdt_ro_index(int cpu)
	63	{
	64	return FIX_GDT_REMAP_BEGIN + cpu;
	65	}
	66
	67	/* Provide the fixmap address of the remapped GDT */
	68	static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
	69	{
	70	unsigned int idx = get_cpu_gdt_ro_index(cpu);
	71	return (struct desc_struct *)__fix_to_virt(idx);
	72	}
	73
69218e47 TG	74	/* Provide the current read-only GDT */
	75	static inline struct desc_struct *get_current_gdt_ro(void)
	76	{
	77	return get_cpu_gdt_ro(smp_processor_id());
	78	}
	79
aa4ea675 AL	80	/* Provide the physical address of the GDT page. */
	81	static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
	82	{
	83	return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
	84	}
	85
54cd0eac	86	#ifdef CONFIG_X86_64
507f90c9 GOC	87
	88	static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
	89	unsigned dpl, unsigned ist, unsigned seg)
	90	{
9a3865b1 IM	91	gate->offset_low = PTR_LOW(func);
	92	gate->segment = __KERNEL_CS;
	93	gate->ist = ist;
	94	gate->p = 1;
	95	gate->dpl = dpl;
	96	gate->zero0 = 0;
	97	gate->zero1 = 0;
	98	gate->type = type;
	99	gate->offset_middle = PTR_MIDDLE(func);
	100	gate->offset_high = PTR_HIGH(func);
507f90c9 GOC	101	}
507f90c9 GOC	102
54cd0eac	103	#else
507f90c9	104	static inline void pack_gate(gate_desc *gate, unsigned char type,
c1773a16 JP	105	unsigned long base, unsigned dpl, unsigned flags,
c1773a16 JP	106	unsigned short seg)
507f90c9 GOC	107	{
507f90c9 GOC	108	gate->a = (seg << 16) \| (base & 0xffff);
9a3865b1	109	gate->b = (base & 0xffff0000) \| (((0x80 \| type \| (dpl << 5)) & 0xff) << 8);
507f90c9 GOC	110	}
507f90c9 GOC	111
54cd0eac GOC	112	#endif
54cd0eac GOC	113
746ff60f GOC	114	static inline int desc_empty(const void *ptr)
	115	{
	116	const u32 *desc = ptr;
9a3865b1	117
746ff60f GOC	118	return !(desc[0] \| desc[1]);
	119	}
	120
54cd0eac GOC	121	#ifdef CONFIG_PARAVIRT
	122	#include <asm/paravirt.h>
	123	#else
9a3865b1 IM	124	#define load_TR_desc() native_load_tr_desc()
	125	#define load_gdt(dtr) native_load_gdt(dtr)
	126	#define load_idt(dtr) native_load_idt(dtr)
	127	#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
	128	#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
	129
	130	#define store_gdt(dtr) native_store_gdt(dtr)
	131	#define store_idt(dtr) native_store_idt(dtr)
	132	#define store_tr(tr) (tr = native_store_tr())
	133
	134	#define load_TLS(t, cpu) native_load_tls(t, cpu)
	135	#define set_ldt native_set_ldt
	136
	137	#define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
	138	#define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
	139	#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
38ffbe66 JF	140
	141	static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
	142	{
	143	}
	144
	145	static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
	146	{
	147	}
	148	#endif /* CONFIG_PARAVIRT */
54cd0eac	149
8229d754 JSR	150	#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
8229d754 JSR	151
9a3865b1	152	static inline void native_write_idt_entry(gate_desc idt, int entry, const gate_desc gate)
54cd0eac GOC	153	{
	154	memcpy(&idt[entry], gate, sizeof(*gate));
	155	}
	156
9a3865b1	157	static inline void native_write_ldt_entry(struct desc_struct ldt, int entry, const void desc)
54cd0eac GOC	158	{
	159	memcpy(&ldt[entry], desc, 8);
	160	}
	161
9a3865b1 IM	162	static inline void
9a3865b1 IM	163	native_write_gdt_entry(struct desc_struct gdt, int entry, const void desc, int type)
54cd0eac GOC	164	{
54cd0eac GOC	165	unsigned int size;
9a3865b1	166
54cd0eac	167	switch (type) {
9a3865b1 IM	168	case DESC_TSS: size = sizeof(tss_desc); break;
	169	case DESC_LDT: size = sizeof(ldt_desc); break;
	170	default: size = sizeof(*gdt); break;
54cd0eac	171	}
9a3865b1	172
54cd0eac GOC	173	memcpy(&gdt[entry], desc, size);
	174	}
	175
54cd0eac GOC	176	static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
	177	unsigned long limit, unsigned char type,
	178	unsigned char flags)
	179	{
	180	desc->a = ((base & 0xffff) << 16) \| (limit & 0xffff);
	181	desc->b = (base & 0xff000000) \| ((base & 0xff0000) >> 16) \|
c1773a16 JP	182	(limit & 0x000f0000) \| ((type & 0xff) << 8) \|
c1773a16 JP	183	((flags & 0xf) << 20);
54cd0eac GOC	184	desc->p = 1;
	185	}
	186
54cd0eac	187
9a3865b1	188	static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
c81c6ca4 GOC	189	{
c81c6ca4 GOC	190	#ifdef CONFIG_X86_64
f6e0eba1	191	struct ldttss_desc64 *desc = d;
9a3865b1	192
f6e0eba1	193	memset(desc, 0, sizeof(*desc));
9a3865b1 IM	194
	195	desc->limit0 = size & 0xFFFF;
	196	desc->base0 = PTR_LOW(addr);
	197	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	198	desc->type = type;
	199	desc->p = 1;
	200	desc->limit1 = (size >> 16) & 0xF;
	201	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	202	desc->base3 = PTR_HIGH(addr);
c81c6ca4	203	#else
f6e0eba1	204	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 \| type, 0);
c81c6ca4 GOC	205	#endif
	206	}
	207
	208	static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
	209	{
69218e47	210	struct desc_struct *d = get_cpu_gdt_rw(cpu);
c81c6ca4 GOC	211	tss_desc tss;
c81c6ca4 GOC	212
f6e0eba1	213	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
4f53ab14	214	__KERNEL_TSS_LIMIT);
c81c6ca4 GOC	215	write_gdt_entry(d, entry, &tss, DESC_TSS);
	216	}
	217
	218	#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
	219
54cd0eac GOC	220	static inline void native_set_ldt(const void *addr, unsigned int entries)
	221	{
	222	if (likely(entries == 0))
c1773a16	223	asm volatile("lldt %w0"::"q" (0));
54cd0eac GOC	224	else {
	225	unsigned cpu = smp_processor_id();
	226	ldt_desc ldt;
	227
5ac37f87 MK	228	set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
5ac37f87 MK	229	entries * LDT_ENTRY_SIZE - 1);
69218e47	230	write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
54cd0eac	231	&ldt, DESC_LDT);
c1773a16	232	asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
54cd0eac GOC	233	}
	234	}
	235
45fc8757 TG	236	static inline void native_load_gdt(const struct desc_ptr *dtr)
	237	{
	238	asm volatile("lgdt %0"::"m" (*dtr));
	239	}
	240
	241	static inline void native_load_idt(const struct desc_ptr *dtr)
	242	{
	243	asm volatile("lidt %0"::"m" (*dtr));
	244	}
	245
	246	static inline void native_store_gdt(struct desc_ptr *dtr)
	247	{
	248	asm volatile("sgdt %0":"=m" (*dtr));
	249	}
	250
	251	static inline void native_store_idt(struct desc_ptr *dtr)
	252	{
	253	asm volatile("sidt %0":"=m" (*dtr));
	254	}
	255
	256	/*
	257	* The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
	258	* a read-only remapping. To prevent a page fault, the GDT is switched to the
	259	* original writeable version when needed.
	260	*/
	261	#ifdef CONFIG_X86_64
54cd0eac GOC	262	static inline void native_load_tr_desc(void)
54cd0eac GOC	263	{
45fc8757 TG	264	struct desc_ptr gdt;
	265	int cpu = raw_smp_processor_id();
	266	bool restore = 0;
	267	struct desc_struct *fixmap_gdt;
	268
	269	native_store_gdt(&gdt);
	270	fixmap_gdt = get_cpu_gdt_ro(cpu);
	271
	272	/*
	273	* If the current GDT is the read-only fixmap, swap to the original
	274	* writeable version. Swap back at the end.
	275	*/
	276	if (gdt.address == (unsigned long)fixmap_gdt) {
	277	load_direct_gdt(cpu);
	278	restore = 1;
	279	}
54cd0eac	280	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
45fc8757 TG	281	if (restore)
	282	load_fixmap_gdt(cpu);
	283	}
	284	#else
	285	static inline void native_load_tr_desc(void)
	286	{
	287	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	288	}
	289	#endif
	290
	291	static inline unsigned long native_store_tr(void)
	292	{
	293	unsigned long tr;
	294
	295	asm volatile("str %0":"=r" (tr));
	296
	297	return tr;
	298	}
	299
	300	static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
	301	{
	302	struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
	303	unsigned int i;
	304
	305	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
	306	gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
54cd0eac GOC	307	}
54cd0eac GOC	308
b7ceaec1 AL	309	DECLARE_PER_CPU(bool, __tss_limit_invalid);
b7ceaec1 AL	310
b7ffc44d AL	311	static inline void force_reload_TR(void)
b7ffc44d AL	312	{
69218e47	313	struct desc_struct *d = get_current_gdt_rw();
b7ffc44d AL	314	tss_desc tss;
	315
	316	memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
	317
	318	/*
	319	* LTR requires an available TSS, and the TSS is currently
	320	* busy. Make it be available so that LTR will work.
	321	*/
	322	tss.type = DESC_TSS;
	323	write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
	324
	325	load_TR_desc();
b7ceaec1	326	this_cpu_write(__tss_limit_invalid, false);
b7ffc44d AL	327	}
b7ffc44d AL	328
b7ceaec1 AL	329	/*
	330	* Call this if you need the TSS limit to be correct, which should be the case
	331	* if and only if you have TIF_IO_BITMAP set or you're switching to a task
	332	* with TIF_IO_BITMAP set.
	333	*/
	334	static inline void refresh_tss_limit(void)
b7ffc44d AL	335	{
	336	DEBUG_LOCKS_WARN_ON(preemptible());
	337
b7ceaec1	338	if (unlikely(this_cpu_read(__tss_limit_invalid)))
b7ffc44d	339	force_reload_TR();
b7ffc44d AL	340	}
	341
	342	/*
	343	* If you do something evil that corrupts the cached TSS limit (I'm looking
	344	* at you, VMX exits), call this function.
	345	*
	346	* The optimization here is that the TSS limit only matters for Linux if the
	347	* IO bitmap is in use. If the TSS limit gets forced to its minimum value,
	348	* everything works except that IO bitmap will be ignored and all CPL 3 IO
	349	* instructions will #GP, which is exactly what we want for normal tasks.
	350	*/
	351	static inline void invalidate_tss_limit(void)
	352	{
	353	DEBUG_LOCKS_WARN_ON(preemptible());
	354
	355	if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
	356	force_reload_TR();
	357	else
b7ceaec1	358	this_cpu_write(__tss_limit_invalid, true);
b7ffc44d AL	359	}
b7ffc44d AL	360
e30ab185 AL	361	/* This intentionally ignores lm, since 32-bit apps don't have that field. */
e30ab185 AL	362	#define LDT_empty(info) \
c1773a16 JP	363	((info)->base_addr == 0 && \
	364	(info)->limit == 0 && \
	365	(info)->contents == 0 && \
	366	(info)->read_exec_only == 1 && \
	367	(info)->seg_32bit == 0 && \
	368	(info)->limit_in_pages == 0 && \
	369	(info)->seg_not_present == 1 && \
	370	(info)->useable == 0)
881c2975	371
3669ef9f AL	372	/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
	373	static inline bool LDT_zero(const struct user_desc *info)
	374	{
	375	return (info->base_addr == 0 &&
	376	info->limit == 0 &&
	377	info->contents == 0 &&
	378	info->read_exec_only == 0 &&
	379	info->seg_32bit == 0 &&
	380	info->limit_in_pages == 0 &&
	381	info->seg_not_present == 0 &&
	382	info->useable == 0);
	383	}
	384
881c2975 GOC	385	static inline void clear_LDT(void)
	386	{
	387	set_ldt(NULL, 0);
	388	}
	389
1bd5718c	390	static inline unsigned long get_desc_base(const struct desc_struct *desc)
cc697852	391	{
2c75910f	392	return (unsigned)(desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24));
cc697852	393	}
1bd5718c	394
57594742 AM	395	static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
	396	{
	397	desc->base0 = base & 0xffff;
	398	desc->base1 = (base >> 16) & 0xff;
	399	desc->base2 = (base >> 24) & 0xff;
	400	}
	401
1bd5718c RM	402	static inline unsigned long get_desc_limit(const struct desc_struct *desc)
	403	{
	404	return desc->limit0 \| (desc->limit << 16);
	405	}
	406
57594742 AM	407	static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
	408	{
	409	desc->limit0 = limit & 0xffff;
	410	desc->limit = (limit >> 16) & 0xf;
	411	}
	412
228bdaa9 SR	413	#ifdef CONFIG_X86_64
	414	static inline void set_nmi_gate(int gate, void *addr)
	415	{
	416	gate_desc s;
	417
	418	pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
629f4f9d	419	write_idt_entry(debug_idt_table, gate, &s);
228bdaa9 SR	420	}
	421	#endif
	422
cf910e83 SA	423	#ifdef CONFIG_TRACING
	424	extern struct desc_ptr trace_idt_descr;
	425	extern gate_desc trace_idt_table[];
	426	static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
	427	{
	428	write_idt_entry(trace_idt_table, entry, gate);
	429	}
25c74b10 SA	430
	431	static inline void _trace_set_gate(int gate, unsigned type, void *addr,
	432	unsigned dpl, unsigned ist, unsigned seg)
	433	{
	434	gate_desc s;
	435
	436	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	437	/*
	438	* does not need to be atomic because it is only done once at
	439	* setup time
	440	*/
	441	write_trace_idt_entry(gate, &s);
	442	}
cf910e83 SA	443	#else
	444	static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
	445	{
	446	}
25c74b10 SA	447
25c74b10 SA	448	#define _trace_set_gate(gate, type, addr, dpl, ist, seg)
cf910e83 SA	449	#endif
cf910e83 SA	450
507f90c9	451	static inline void _set_gate(int gate, unsigned type, void *addr,
c1773a16	452	unsigned dpl, unsigned ist, unsigned seg)
507f90c9 GOC	453	{
507f90c9 GOC	454	gate_desc s;
9a3865b1	455
507f90c9 GOC	456	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	457	/*
	458	* does not need to be atomic because it is only done once at
	459	* setup time
	460	*/
	461	write_idt_entry(idt_table, gate, &s);
cf910e83	462	write_trace_idt_entry(gate, &s);
507f90c9 GOC	463	}
	464
	465	/*
	466	* This needs to use 'idt_table' rather than 'idt', and
	467	* thus use the _nonmapped_ version of the IDT, as the
	468	* Pentium F0 0F bugfix can have resulted in the mapped
	469	* IDT being write-protected.
	470	*/
5eca7453	471	#define set_intr_gate_notrace(n, addr) \
25c74b10 SA	472	do { \
	473	BUG_ON((unsigned)n > 0xFF); \
	474	_set_gate(n, GATE_INTERRUPT, (void *)addr, 0, 0, \
	475	__KERNEL_CS); \
5eca7453 WN	476	} while (0)
	477
	478	#define set_intr_gate(n, addr) \
	479	do { \
	480	set_intr_gate_notrace(n, addr); \
25c74b10 SA	481	_trace_set_gate(n, GATE_INTERRUPT, (void *)trace_##addr,\
	482	0, 0, __KERNEL_CS); \
	483	} while (0)
507f90c9	484
305b92a2	485	extern int first_system_vector;
b77b881f YL	486	/* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
b77b881f YL	487	extern unsigned long used_vectors[];
305b92a2 AM	488
	489	static inline void alloc_system_vector(int vector)
	490	{
b77b881f YL	491	if (!test_bit(vector, used_vectors)) {
b77b881f YL	492	set_bit(vector, used_vectors);
305b92a2 AM	493	if (first_system_vector > vector)
305b92a2 AM	494	first_system_vector = vector;
9a3865b1	495	} else {
305b92a2	496	BUG();
9a3865b1	497	}
305b92a2 AM	498	}
305b92a2 AM	499
cf910e83 SA	500	#define alloc_intr_gate(n, addr) \
	501	do { \
	502	alloc_system_vector(n); \
959c071f	503	set_intr_gate(n, addr); \
cf910e83 SA	504	} while (0)
cf910e83 SA	505
507f90c9 GOC	506	/*
	507	* This routine sets up an interrupt gate at directory privilege level 3.
	508	*/
	509	static inline void set_system_intr_gate(unsigned int n, void *addr)
	510	{
	511	BUG_ON((unsigned)n > 0xFF);
	512	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
	513	}
	514
699d2937	515	static inline void set_system_trap_gate(unsigned int n, void *addr)
507f90c9 GOC	516	{
507f90c9 GOC	517	BUG_ON((unsigned)n > 0xFF);
699d2937	518	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
507f90c9 GOC	519	}
507f90c9 GOC	520
699d2937	521	static inline void set_trap_gate(unsigned int n, void *addr)
507f90c9 GOC	522	{
507f90c9 GOC	523	BUG_ON((unsigned)n > 0xFF);
699d2937	524	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
507f90c9 GOC	525	}
	526
	527	static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
	528	{
	529	BUG_ON((unsigned)n > 0xFF);
	530	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
	531	}
	532
	533	static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
	534	{
	535	BUG_ON((unsigned)n > 0xFF);
	536	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
	537	}
	538
699d2937	539	static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
507f90c9 GOC	540	{
	541	BUG_ON((unsigned)n > 0xFF);
	542	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
	543	}
cc697852	544
629f4f9d SA	545	#ifdef CONFIG_X86_64
	546	DECLARE_PER_CPU(u32, debug_idt_ctr);
	547	static inline bool is_debug_idt_enabled(void)
	548	{
	549	if (this_cpu_read(debug_idt_ctr))
	550	return true;
	551
	552	return false;
	553	}
	554
	555	static inline void load_debug_idt(void)
	556	{
	557	load_idt((const struct desc_ptr *)&debug_idt_descr);
	558	}
	559	#else
	560	static inline bool is_debug_idt_enabled(void)
	561	{
	562	return false;
	563	}
	564
	565	static inline void load_debug_idt(void)
	566	{
	567	}
	568	#endif
	569
cf910e83 SA	570	#ifdef CONFIG_TRACING
	571	extern atomic_t trace_idt_ctr;
	572	static inline bool is_trace_idt_enabled(void)
	573	{
	574	if (atomic_read(&trace_idt_ctr))
	575	return true;
	576
	577	return false;
	578	}
	579
	580	static inline void load_trace_idt(void)
	581	{
	582	load_idt((const struct desc_ptr *)&trace_idt_descr);
	583	}
	584	#else
	585	static inline bool is_trace_idt_enabled(void)
	586	{
	587	return false;
	588	}
	589
	590	static inline void load_trace_idt(void)
	591	{
	592	}
	593	#endif
	594
629f4f9d	595	/*
2b4bc789	596	* The load_current_idt() must be called with interrupts disabled
629f4f9d	597	* to avoid races. That way the IDT will always be set back to the expected
2b4bc789 SRRH	598	* descriptor. It's also called when a CPU is being initialized, and
	599	* that doesn't need to disable interrupts, as nothing should be
	600	* bothering the CPU then.
629f4f9d SA	601	*/
	602	static inline void load_current_idt(void)
	603	{
629f4f9d SA	604	if (is_debug_idt_enabled())
629f4f9d SA	605	load_debug_idt();
cf910e83 SA	606	else if (is_trace_idt_enabled())
cf910e83 SA	607	load_trace_idt();
629f4f9d SA	608	else
629f4f9d SA	609	load_idt((const struct desc_ptr *)&idt_descr);
629f4f9d	610	}
1965aae3	611	#endif /* _ASM_X86_DESC_H */