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381aa07a DH |
1 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
2 | #define _ASM_X86_DISABLED_FEATURES_H | |
3 | ||
4 | /* These features, although they might be available in a CPU | |
5 | * will not be used because the compile options to support | |
6 | * them are not present. | |
7 | * | |
8 | * This code allows them to be checked and disabled at | |
9 | * compile time without an explicit #ifdef. Use | |
10 | * cpu_feature_enabled(). | |
11 | */ | |
12 | ||
95290cf1 DH |
13 | #ifdef CONFIG_X86_INTEL_MPX |
14 | # define DISABLE_MPX 0 | |
15 | #else | |
16 | # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) | |
17 | #endif | |
18 | ||
3522c2a6 RN |
19 | #ifdef CONFIG_X86_INTEL_UMIP |
20 | # define DISABLE_UMIP 0 | |
21 | #else | |
22 | # define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) | |
23 | #endif | |
24 | ||
9298b815 DH |
25 | #ifdef CONFIG_X86_64 |
26 | # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) | |
27 | # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) | |
28 | # define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31)) | |
29 | # define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31)) | |
cba4671a | 30 | # define DISABLE_PCID 0 |
9298b815 DH |
31 | #else |
32 | # define DISABLE_VME 0 | |
33 | # define DISABLE_K6_MTRR 0 | |
34 | # define DISABLE_CYRIX_ARR 0 | |
35 | # define DISABLE_CENTAUR_MCR 0 | |
cba4671a | 36 | # define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31)) |
9298b815 DH |
37 | #endif /* CONFIG_X86_64 */ |
38 | ||
dfb4a70f | 39 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS |
dfb4a70f DH |
40 | # define DISABLE_PKU 0 |
41 | # define DISABLE_OSPKE 0 | |
e8df1a95 DH |
42 | #else |
43 | # define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31)) | |
44 | # define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) | |
dfb4a70f DH |
45 | #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ |
46 | ||
3677d4c6 KS |
47 | #ifdef CONFIG_X86_5LEVEL |
48 | # define DISABLE_LA57 0 | |
49 | #else | |
50 | # define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31)) | |
51 | #endif | |
52 | ||
a89f040f TG |
53 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
54 | # define DISABLE_PTI 0 | |
55 | #else | |
56 | # define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) | |
57 | #endif | |
58 | ||
381aa07a DH |
59 | /* |
60 | * Make sure to add features to the correct mask | |
61 | */ | |
9298b815 | 62 | #define DISABLED_MASK0 (DISABLE_VME) |
381aa07a DH |
63 | #define DISABLED_MASK1 0 |
64 | #define DISABLED_MASK2 0 | |
9298b815 | 65 | #define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_MTRR) |
cba4671a | 66 | #define DISABLED_MASK4 (DISABLE_PCID) |
381aa07a DH |
67 | #define DISABLED_MASK5 0 |
68 | #define DISABLED_MASK6 0 | |
a89f040f | 69 | #define DISABLED_MASK7 (DISABLE_PTI) |
381aa07a | 70 | #define DISABLED_MASK8 0 |
95290cf1 | 71 | #define DISABLED_MASK9 (DISABLE_MPX) |
dfb4a70f DH |
72 | #define DISABLED_MASK10 0 |
73 | #define DISABLED_MASK11 0 | |
74 | #define DISABLED_MASK12 0 | |
75 | #define DISABLED_MASK13 0 | |
76 | #define DISABLED_MASK14 0 | |
77 | #define DISABLED_MASK15 0 | |
3522c2a6 | 78 | #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) |
6e17cb9c | 79 | #define DISABLED_MASK17 0 |
38635304 DW |
80 | #define DISABLED_MASK18 0 |
81 | #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) | |
381aa07a DH |
82 | |
83 | #endif /* _ASM_X86_DISABLED_FEATURES_H */ |