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1965aae3 PA |
1 | #ifndef _ASM_X86_DMA_MAPPING_H |
2 | #define _ASM_X86_DMA_MAPPING_H | |
6f536635 GC |
3 | |
4 | /* | |
395cf969 | 5 | * IOMMU interface. See Documentation/DMA-API-HOWTO.txt and |
5872fb94 | 6 | * Documentation/DMA-API.txt for documentation. |
6f536635 GC |
7 | */ |
8 | ||
d7002857 | 9 | #include <linux/kmemcheck.h> |
6f536635 | 10 | #include <linux/scatterlist.h> |
2118d0c5 | 11 | #include <linux/dma-debug.h> |
abe6602b | 12 | #include <linux/dma-attrs.h> |
6f536635 GC |
13 | #include <asm/io.h> |
14 | #include <asm/swiotlb.h> | |
6c505ce3 | 15 | #include <asm-generic/dma-coherent.h> |
6f536635 | 16 | |
eb647138 JB |
17 | #ifdef CONFIG_ISA |
18 | # define ISA_DMA_BIT_MASK DMA_BIT_MASK(24) | |
19 | #else | |
20 | # define ISA_DMA_BIT_MASK DMA_BIT_MASK(32) | |
21 | #endif | |
22 | ||
8fd524b3 FT |
23 | #define DMA_ERROR_CODE 0 |
24 | ||
b7107a3d | 25 | extern int iommu_merge; |
6c505ce3 | 26 | extern struct device x86_dma_fallback_dev; |
b7107a3d | 27 | extern int panic_on_overflow; |
7c183416 | 28 | |
160c1d8e FT |
29 | extern struct dma_map_ops *dma_ops; |
30 | ||
31 | static inline struct dma_map_ops *get_dma_ops(struct device *dev) | |
c786df08 | 32 | { |
8d8bb39b FT |
33 | #ifdef CONFIG_X86_32 |
34 | return dma_ops; | |
35 | #else | |
36 | if (unlikely(!dev) || !dev->archdata.dma_ops) | |
37 | return dma_ops; | |
38 | else | |
39 | return dev->archdata.dma_ops; | |
cfb80c9e | 40 | #endif |
8d8bb39b FT |
41 | } |
42 | ||
7c095e46 FT |
43 | #include <asm-generic/dma-mapping-common.h> |
44 | ||
8d8bb39b FT |
45 | /* Make sure we keep the same behaviour */ |
46 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | |
47 | { | |
160c1d8e | 48 | struct dma_map_ops *ops = get_dma_ops(dev); |
8d8bb39b FT |
49 | if (ops->mapping_error) |
50 | return ops->mapping_error(dev, dma_addr); | |
c786df08 | 51 | |
8fd524b3 | 52 | return (dma_addr == DMA_ERROR_CODE); |
c786df08 GC |
53 | } |
54 | ||
8d396ded GC |
55 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) |
56 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | |
8d396ded | 57 | |
802c1f66 GC |
58 | extern int dma_supported(struct device *hwdev, u64 mask); |
59 | extern int dma_set_mask(struct device *dev, u64 mask); | |
60 | ||
9f6ac577 | 61 | extern void *dma_generic_alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
62 | dma_addr_t *dma_addr, gfp_t flag, |
63 | struct dma_attrs *attrs); | |
9f6ac577 | 64 | |
99becaca FT |
65 | static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) |
66 | { | |
67 | if (!dev->dma_mask) | |
68 | return 0; | |
69 | ||
ac2b3e67 | 70 | return addr + size - 1 <= *dev->dma_mask; |
99becaca FT |
71 | } |
72 | ||
8d4f5339 FT |
73 | static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) |
74 | { | |
75 | return paddr; | |
76 | } | |
77 | ||
78 | static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) | |
79 | { | |
80 | return daddr; | |
81 | } | |
82 | ||
3cb6a917 GC |
83 | static inline void |
84 | dma_cache_sync(struct device *dev, void *vaddr, size_t size, | |
85 | enum dma_data_direction dir) | |
86 | { | |
87 | flush_write_buffers(); | |
88 | } | |
ae17a63b | 89 | |
823e7e8c FT |
90 | static inline unsigned long dma_alloc_coherent_mask(struct device *dev, |
91 | gfp_t gfp) | |
92 | { | |
93 | unsigned long dma_mask = 0; | |
b7107a3d | 94 | |
823e7e8c FT |
95 | dma_mask = dev->coherent_dma_mask; |
96 | if (!dma_mask) | |
2f4f27d4 | 97 | dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32); |
823e7e8c FT |
98 | |
99 | return dma_mask; | |
100 | } | |
101 | ||
102 | static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp) | |
103 | { | |
104 | unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp); | |
105 | ||
2f4f27d4 | 106 | if (dma_mask <= DMA_BIT_MASK(24)) |
75bebb7f FT |
107 | gfp |= GFP_DMA; |
108 | #ifdef CONFIG_X86_64 | |
284901a9 | 109 | if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA)) |
823e7e8c FT |
110 | gfp |= GFP_DMA32; |
111 | #endif | |
112 | return gfp; | |
113 | } | |
114 | ||
baa676fc AP |
115 | #define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) |
116 | ||
6c505ce3 | 117 | static inline void * |
baa676fc AP |
118 | dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, |
119 | gfp_t gfp, struct dma_attrs *attrs) | |
6c505ce3 | 120 | { |
160c1d8e | 121 | struct dma_map_ops *ops = get_dma_ops(dev); |
6c505ce3 JR |
122 | void *memory; |
123 | ||
8a53ad67 FT |
124 | gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); |
125 | ||
6c505ce3 JR |
126 | if (dma_alloc_from_coherent(dev, size, dma_handle, &memory)) |
127 | return memory; | |
128 | ||
eb647138 | 129 | if (!dev) |
6c505ce3 | 130 | dev = &x86_dma_fallback_dev; |
6c505ce3 | 131 | |
98216260 | 132 | if (!is_device_dma_capable(dev)) |
de9f521f FT |
133 | return NULL; |
134 | ||
baa676fc | 135 | if (!ops->alloc) |
823e7e8c FT |
136 | return NULL; |
137 | ||
baa676fc AP |
138 | memory = ops->alloc(dev, size, dma_handle, |
139 | dma_alloc_coherent_gfp_flags(dev, gfp), attrs); | |
2118d0c5 JR |
140 | debug_dma_alloc_coherent(dev, size, *dma_handle, memory); |
141 | ||
142 | return memory; | |
6c505ce3 JR |
143 | } |
144 | ||
baa676fc AP |
145 | #define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) |
146 | ||
147 | static inline void dma_free_attrs(struct device *dev, size_t size, | |
148 | void *vaddr, dma_addr_t bus, | |
149 | struct dma_attrs *attrs) | |
6c505ce3 | 150 | { |
160c1d8e | 151 | struct dma_map_ops *ops = get_dma_ops(dev); |
6c505ce3 JR |
152 | |
153 | WARN_ON(irqs_disabled()); /* for portability */ | |
154 | ||
155 | if (dma_release_from_coherent(dev, get_order(size), vaddr)) | |
156 | return; | |
157 | ||
2118d0c5 | 158 | debug_dma_free_coherent(dev, size, vaddr, bus); |
baa676fc AP |
159 | if (ops->free) |
160 | ops->free(dev, size, vaddr, bus, attrs); | |
6c505ce3 | 161 | } |
b7107a3d | 162 | |
6f536635 | 163 | #endif |