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1965aae3 PA |
1 | #ifndef _ASM_X86_DMA_MAPPING_H |
2 | #define _ASM_X86_DMA_MAPPING_H | |
6f536635 GC |
3 | |
4 | /* | |
5872fb94 RD |
5 | * IOMMU interface. See Documentation/PCI/PCI-DMA-mapping.txt and |
6 | * Documentation/DMA-API.txt for documentation. | |
6f536635 GC |
7 | */ |
8 | ||
d7002857 | 9 | #include <linux/kmemcheck.h> |
6f536635 | 10 | #include <linux/scatterlist.h> |
2118d0c5 | 11 | #include <linux/dma-debug.h> |
abe6602b | 12 | #include <linux/dma-attrs.h> |
6f536635 GC |
13 | #include <asm/io.h> |
14 | #include <asm/swiotlb.h> | |
6c505ce3 | 15 | #include <asm-generic/dma-coherent.h> |
6f536635 | 16 | |
eb647138 JB |
17 | #ifdef CONFIG_ISA |
18 | # define ISA_DMA_BIT_MASK DMA_BIT_MASK(24) | |
19 | #else | |
20 | # define ISA_DMA_BIT_MASK DMA_BIT_MASK(32) | |
21 | #endif | |
22 | ||
8fd524b3 FT |
23 | #define DMA_ERROR_CODE 0 |
24 | ||
b7107a3d | 25 | extern int iommu_merge; |
6c505ce3 | 26 | extern struct device x86_dma_fallback_dev; |
b7107a3d | 27 | extern int panic_on_overflow; |
7c183416 | 28 | |
160c1d8e FT |
29 | extern struct dma_map_ops *dma_ops; |
30 | ||
31 | static inline struct dma_map_ops *get_dma_ops(struct device *dev) | |
c786df08 | 32 | { |
8d8bb39b FT |
33 | #ifdef CONFIG_X86_32 |
34 | return dma_ops; | |
35 | #else | |
36 | if (unlikely(!dev) || !dev->archdata.dma_ops) | |
37 | return dma_ops; | |
38 | else | |
39 | return dev->archdata.dma_ops; | |
cfb80c9e | 40 | #endif |
8d8bb39b FT |
41 | } |
42 | ||
7c095e46 FT |
43 | #include <asm-generic/dma-mapping-common.h> |
44 | ||
8d8bb39b FT |
45 | /* Make sure we keep the same behaviour */ |
46 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) | |
47 | { | |
160c1d8e | 48 | struct dma_map_ops *ops = get_dma_ops(dev); |
8d8bb39b FT |
49 | if (ops->mapping_error) |
50 | return ops->mapping_error(dev, dma_addr); | |
c786df08 | 51 | |
8fd524b3 | 52 | return (dma_addr == DMA_ERROR_CODE); |
c786df08 GC |
53 | } |
54 | ||
8d396ded GC |
55 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) |
56 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | |
8d396ded | 57 | |
802c1f66 GC |
58 | extern int dma_supported(struct device *hwdev, u64 mask); |
59 | extern int dma_set_mask(struct device *dev, u64 mask); | |
60 | ||
9f6ac577 FT |
61 | extern void *dma_generic_alloc_coherent(struct device *dev, size_t size, |
62 | dma_addr_t *dma_addr, gfp_t flag); | |
63 | ||
99becaca FT |
64 | static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) |
65 | { | |
66 | if (!dev->dma_mask) | |
67 | return 0; | |
68 | ||
ac2b3e67 | 69 | return addr + size - 1 <= *dev->dma_mask; |
99becaca FT |
70 | } |
71 | ||
8d4f5339 FT |
72 | static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) |
73 | { | |
74 | return paddr; | |
75 | } | |
76 | ||
77 | static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) | |
78 | { | |
79 | return daddr; | |
80 | } | |
81 | ||
3cb6a917 GC |
82 | static inline void |
83 | dma_cache_sync(struct device *dev, void *vaddr, size_t size, | |
84 | enum dma_data_direction dir) | |
85 | { | |
86 | flush_write_buffers(); | |
87 | } | |
ae17a63b | 88 | |
823e7e8c FT |
89 | static inline unsigned long dma_alloc_coherent_mask(struct device *dev, |
90 | gfp_t gfp) | |
91 | { | |
92 | unsigned long dma_mask = 0; | |
b7107a3d | 93 | |
823e7e8c FT |
94 | dma_mask = dev->coherent_dma_mask; |
95 | if (!dma_mask) | |
2f4f27d4 | 96 | dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32); |
823e7e8c FT |
97 | |
98 | return dma_mask; | |
99 | } | |
100 | ||
101 | static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp) | |
102 | { | |
103 | unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp); | |
104 | ||
2f4f27d4 | 105 | if (dma_mask <= DMA_BIT_MASK(24)) |
75bebb7f FT |
106 | gfp |= GFP_DMA; |
107 | #ifdef CONFIG_X86_64 | |
284901a9 | 108 | if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA)) |
823e7e8c FT |
109 | gfp |= GFP_DMA32; |
110 | #endif | |
111 | return gfp; | |
112 | } | |
113 | ||
6c505ce3 JR |
114 | static inline void * |
115 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, | |
116 | gfp_t gfp) | |
117 | { | |
160c1d8e | 118 | struct dma_map_ops *ops = get_dma_ops(dev); |
6c505ce3 JR |
119 | void *memory; |
120 | ||
8a53ad67 FT |
121 | gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); |
122 | ||
6c505ce3 JR |
123 | if (dma_alloc_from_coherent(dev, size, dma_handle, &memory)) |
124 | return memory; | |
125 | ||
eb647138 | 126 | if (!dev) |
6c505ce3 | 127 | dev = &x86_dma_fallback_dev; |
6c505ce3 | 128 | |
98216260 | 129 | if (!is_device_dma_capable(dev)) |
de9f521f FT |
130 | return NULL; |
131 | ||
823e7e8c FT |
132 | if (!ops->alloc_coherent) |
133 | return NULL; | |
134 | ||
2118d0c5 JR |
135 | memory = ops->alloc_coherent(dev, size, dma_handle, |
136 | dma_alloc_coherent_gfp_flags(dev, gfp)); | |
137 | debug_dma_alloc_coherent(dev, size, *dma_handle, memory); | |
138 | ||
139 | return memory; | |
6c505ce3 JR |
140 | } |
141 | ||
142 | static inline void dma_free_coherent(struct device *dev, size_t size, | |
143 | void *vaddr, dma_addr_t bus) | |
144 | { | |
160c1d8e | 145 | struct dma_map_ops *ops = get_dma_ops(dev); |
6c505ce3 JR |
146 | |
147 | WARN_ON(irqs_disabled()); /* for portability */ | |
148 | ||
149 | if (dma_release_from_coherent(dev, get_order(size), vaddr)) | |
150 | return; | |
151 | ||
2118d0c5 | 152 | debug_dma_free_coherent(dev, size, vaddr, bus); |
6c505ce3 JR |
153 | if (ops->free_coherent) |
154 | ops->free_coherent(dev, size, vaddr, bus); | |
155 | } | |
b7107a3d | 156 | |
6f536635 | 157 | #endif |