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Commit | Line | Data |
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1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
78f7f1e5 IM |
10 | #ifndef _ASM_X86_FPU_INTERNAL_H |
11 | #define _ASM_X86_FPU_INTERNAL_H | |
1361b83a | 12 | |
050902c0 | 13 | #include <linux/compat.h> |
952f07ec | 14 | #include <linux/sched.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
df6b35f4 | 18 | #include <asm/fpu/api.h> |
669ebabb | 19 | #include <asm/fpu/xstate.h> |
1361b83a | 20 | |
df639752 IM |
21 | #define MXCSR_DEFAULT 0x1f80 |
22 | ||
72a671ce | 23 | extern unsigned int mxcsr_feature_mask; |
1361b83a | 24 | |
6f575023 IM |
25 | extern union thread_xstate init_fpstate; |
26 | ||
04c8e01d | 27 | extern void fpu__init_cpu(void); |
55cc4678 IM |
28 | extern void fpu__init_system_xstate(void); |
29 | extern void fpu__init_cpu_xstate(void); | |
dd863880 | 30 | extern void fpu__init_system(struct cpuinfo_x86 *c); |
55cc4678 | 31 | |
c4d72e2d | 32 | extern void fpu__activate_curr(struct fpu *fpu); |
0aba6978 | 33 | |
bf935b0b | 34 | extern void fpstate_init(union thread_xstate *state); |
0aba6978 IM |
35 | #ifdef CONFIG_MATH_EMULATION |
36 | extern void fpstate_init_soft(struct i387_soft_struct *soft); | |
37 | #else | |
38 | static inline void fpstate_init_soft(struct i387_soft_struct *soft) {} | |
39 | #endif | |
40 | static inline void fpstate_init_fxstate(struct i387_fxsave_struct *fx) | |
41 | { | |
42 | fx->cwd = 0x37f; | |
43 | fx->mxcsr = MXCSR_DEFAULT; | |
44 | } | |
952f07ec | 45 | |
e1cebad4 IM |
46 | extern int dump_fpu(struct pt_regs *, struct user_i387_struct *); |
47 | extern int fpu__exception_code(struct fpu *fpu, int trap_nr); | |
6ffc152e IM |
48 | |
49 | /* | |
50 | * High level FPU state handling functions: | |
51 | */ | |
52 | extern void fpu__save(struct fpu *fpu); | |
952f07ec | 53 | extern void fpu__restore(void); |
82c0e45e | 54 | extern int fpu__restore_sig(void __user *buf, int ia32_frame); |
6ffc152e IM |
55 | extern void fpu__drop(struct fpu *fpu); |
56 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); | |
04c8e01d | 57 | extern void fpu__clear(struct fpu *fpu); |
6ffc152e | 58 | |
952f07ec IM |
59 | extern void fpu__init_check_bugs(void); |
60 | extern void fpu__resume_cpu(void); | |
61 | ||
36b544dc | 62 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); |
1361b83a | 63 | |
1c927eea | 64 | /* |
36b544dc | 65 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, |
1c927eea RR |
66 | * on this CPU. |
67 | * | |
68 | * This will disable any lazy FPU state restore of the current FPU state, | |
69 | * but if the current thread owns the FPU, it will still be saved by. | |
70 | */ | |
71 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
72 | { | |
36b544dc | 73 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
1c927eea RR |
74 | } |
75 | ||
66ddc2cb | 76 | static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu) |
1c927eea | 77 | { |
66ddc2cb | 78 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; |
1c927eea RR |
79 | } |
80 | ||
1361b83a LT |
81 | #define X87_FSW_ES (1 << 7) /* Exception Summary */ |
82 | ||
5d2bd700 SS |
83 | static __always_inline __pure bool use_eager_fpu(void) |
84 | { | |
c6b40691 | 85 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
86 | } |
87 | ||
1361b83a LT |
88 | static __always_inline __pure bool use_xsaveopt(void) |
89 | { | |
c6b40691 | 90 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
91 | } |
92 | ||
93 | static __always_inline __pure bool use_xsave(void) | |
94 | { | |
c6b40691 | 95 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
96 | } |
97 | ||
98 | static __always_inline __pure bool use_fxsr(void) | |
99 | { | |
c6b40691 | 100 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
101 | } |
102 | ||
36e49e7f | 103 | extern void fpstate_sanitize_xstate(struct fpu *fpu); |
1361b83a | 104 | |
49b8c695 PA |
105 | #define user_insn(insn, output, input...) \ |
106 | ({ \ | |
107 | int err; \ | |
108 | asm volatile(ASM_STAC "\n" \ | |
109 | "1:" #insn "\n\t" \ | |
110 | "2: " ASM_CLAC "\n" \ | |
111 | ".section .fixup,\"ax\"\n" \ | |
112 | "3: movl $-1,%[err]\n" \ | |
113 | " jmp 2b\n" \ | |
114 | ".previous\n" \ | |
115 | _ASM_EXTABLE(1b, 3b) \ | |
116 | : [err] "=r" (err), output \ | |
117 | : "0"(0), input); \ | |
118 | err; \ | |
119 | }) | |
120 | ||
0ca5bd0d SS |
121 | #define check_insn(insn, output, input...) \ |
122 | ({ \ | |
123 | int err; \ | |
124 | asm volatile("1:" #insn "\n\t" \ | |
125 | "2:\n" \ | |
126 | ".section .fixup,\"ax\"\n" \ | |
127 | "3: movl $-1,%[err]\n" \ | |
128 | " jmp 2b\n" \ | |
129 | ".previous\n" \ | |
130 | _ASM_EXTABLE(1b, 3b) \ | |
131 | : [err] "=r" (err), output \ | |
132 | : "0"(0), input); \ | |
133 | err; \ | |
134 | }) | |
135 | ||
c6813144 | 136 | static inline int copy_fregs_to_user(struct i387_fsave_struct __user *fx) |
1361b83a | 137 | { |
49b8c695 | 138 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
139 | } |
140 | ||
c6813144 | 141 | static inline int copy_fxregs_to_user(struct i387_fxsave_struct __user *fx) |
1361b83a | 142 | { |
0ca5bd0d | 143 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 144 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 145 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 146 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 147 | |
c6813144 | 148 | /* See comment in copy_fxregs_to_kernel() below. */ |
49b8c695 | 149 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
150 | } |
151 | ||
c6813144 | 152 | static inline int copy_kernel_to_fxregs(struct i387_fxsave_struct *fx) |
1361b83a | 153 | { |
0ca5bd0d SS |
154 | if (config_enabled(CONFIG_X86_32)) |
155 | return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
156 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
157 | return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a | 158 | |
c6813144 | 159 | /* See comment in copy_fxregs_to_kernel() below. */ |
0ca5bd0d SS |
160 | return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
161 | "m" (*fx)); | |
1361b83a LT |
162 | } |
163 | ||
c6813144 | 164 | static inline int copy_user_to_fxregs(struct i387_fxsave_struct __user *fx) |
e139e955 PA |
165 | { |
166 | if (config_enabled(CONFIG_X86_32)) | |
167 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
168 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
169 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
170 | ||
c6813144 | 171 | /* See comment in copy_fxregs_to_kernel() below. */ |
e139e955 PA |
172 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
173 | "m" (*fx)); | |
174 | } | |
175 | ||
c6813144 | 176 | static inline int copy_kernel_to_fregs(struct i387_fsave_struct *fx) |
1361b83a | 177 | { |
0ca5bd0d | 178 | return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
179 | } |
180 | ||
c6813144 | 181 | static inline int copy_user_to_fregs(struct i387_fsave_struct __user *fx) |
e139e955 PA |
182 | { |
183 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
184 | } |
185 | ||
c6813144 | 186 | static inline void copy_fxregs_to_kernel(struct fpu *fpu) |
1361b83a | 187 | { |
0ca5bd0d | 188 | if (config_enabled(CONFIG_X86_32)) |
7366ed77 | 189 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d | 190 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
7366ed77 | 191 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
192 | else { |
193 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
194 | * operand uses any extended registers for addressing, a second | |
195 | * REX prefix will be generated (to the assembler, rex64 | |
196 | * followed by semicolon is a separate instruction), and hence | |
197 | * the 64-bitness is lost. | |
198 | * | |
199 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
200 | * supported starting with gas 2.16. | |
201 | * | |
202 | * Using, as a workaround, the properly prefixed form below | |
203 | * isn't accepted by any binutils version so far released, | |
204 | * complaining that the same type of prefix is used twice if | |
205 | * an extended register is needed for addressing (fix submitted | |
206 | * to mainline 2005-11-21). | |
207 | * | |
7366ed77 | 208 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
209 | * |
210 | * This, however, we can work around by forcing the compiler to | |
211 | * select an addressing mode that doesn't require extended | |
212 | * registers. | |
213 | */ | |
214 | asm volatile( "rex64/fxsave (%[fx])" | |
7366ed77 IM |
215 | : "=m" (fpu->state.fxsave) |
216 | : [fx] "R" (&fpu->state.fxsave)); | |
0ca5bd0d | 217 | } |
1361b83a LT |
218 | } |
219 | ||
1361b83a LT |
220 | /* |
221 | * These must be called with preempt disabled. Returns | |
4f836347 IM |
222 | * 'true' if the FPU state is still intact and we can |
223 | * keep registers active. | |
224 | * | |
225 | * The legacy FNSAVE instruction cleared all FPU state | |
226 | * unconditionally, so registers are essentially destroyed. | |
227 | * Modern FPU state can be kept in registers, if there are | |
1bc6b056 | 228 | * no pending FP exceptions. |
1361b83a | 229 | */ |
4f836347 | 230 | static inline int copy_fpregs_to_fpstate(struct fpu *fpu) |
1361b83a | 231 | { |
1bc6b056 | 232 | if (likely(use_xsave())) { |
c6813144 | 233 | copy_xregs_to_kernel(&fpu->state.xsave); |
1bc6b056 IM |
234 | return 1; |
235 | } | |
1361b83a | 236 | |
1bc6b056 | 237 | if (likely(use_fxsr())) { |
c6813144 | 238 | copy_fxregs_to_kernel(fpu); |
1bc6b056 | 239 | return 1; |
1361b83a LT |
240 | } |
241 | ||
242 | /* | |
1bc6b056 IM |
243 | * Legacy FPU register saving, FNSAVE always clears FPU registers, |
244 | * so we have to mark them inactive: | |
1361b83a | 245 | */ |
7366ed77 | 246 | asm volatile("fnsave %[fx]; fwait" : [fx] "=m" (fpu->state.fsave)); |
4f836347 | 247 | |
4f836347 | 248 | return 0; |
1361b83a LT |
249 | } |
250 | ||
0e75c54f | 251 | static inline int __copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a LT |
252 | { |
253 | if (use_xsave()) | |
c6813144 | 254 | return copy_kernel_to_xregs(&fpu->state.xsave, -1); |
0ca5bd0d | 255 | else if (use_fxsr()) |
c6813144 | 256 | return copy_kernel_to_fxregs(&fpu->state.fxsave); |
1361b83a | 257 | else |
c6813144 | 258 | return copy_kernel_to_fregs(&fpu->state.fsave); |
1361b83a LT |
259 | } |
260 | ||
0e75c54f | 261 | static inline int copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a | 262 | { |
6ca7a8a1 BP |
263 | /* |
264 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
265 | * pending. Clear the x87 state here by setting it to fixed values. | |
266 | * "m" is a random variable that should be in L1. | |
267 | */ | |
9b13a93d | 268 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
269 | asm volatile( |
270 | "fnclex\n\t" | |
271 | "emms\n\t" | |
272 | "fildl %P[addr]" /* set F?P to defined value */ | |
d5cea9b0 | 273 | : : [addr] "m" (fpu->fpregs_active)); |
26bef131 | 274 | } |
1361b83a | 275 | |
0e75c54f | 276 | return __copy_fpstate_to_fpregs(fpu); |
1361b83a LT |
277 | } |
278 | ||
32b49b3c IM |
279 | /* |
280 | * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation' | |
281 | * idiom, which is then paired with the sw-flag (fpregs_active) later on: | |
282 | */ | |
283 | ||
284 | static inline void __fpregs_activate_hw(void) | |
285 | { | |
286 | if (!use_eager_fpu()) | |
287 | clts(); | |
288 | } | |
289 | ||
290 | static inline void __fpregs_deactivate_hw(void) | |
291 | { | |
292 | if (!use_eager_fpu()) | |
293 | stts(); | |
294 | } | |
295 | ||
296 | /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */ | |
723c58e4 | 297 | static inline void __fpregs_deactivate(struct fpu *fpu) |
1361b83a | 298 | { |
d5cea9b0 | 299 | fpu->fpregs_active = 0; |
36b544dc | 300 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
301 | } |
302 | ||
32b49b3c | 303 | /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */ |
dfaea4e6 | 304 | static inline void __fpregs_activate(struct fpu *fpu) |
1361b83a | 305 | { |
d5cea9b0 | 306 | fpu->fpregs_active = 1; |
c0311f63 | 307 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); |
1361b83a LT |
308 | } |
309 | ||
952f07ec IM |
310 | /* |
311 | * The question "does this thread have fpu access?" | |
312 | * is slightly racy, since preemption could come in | |
313 | * and revoke it immediately after the test. | |
314 | * | |
315 | * However, even in that very unlikely scenario, | |
316 | * we can just assume we have FPU access - typically | |
317 | * to save the FP state - we'll just take a #NM | |
318 | * fault and get the FPU access back. | |
319 | */ | |
3c6dffa9 | 320 | static inline int fpregs_active(void) |
952f07ec IM |
321 | { |
322 | return current->thread.fpu.fpregs_active; | |
323 | } | |
324 | ||
1361b83a LT |
325 | /* |
326 | * Encapsulate the CR0.TS handling together with the | |
327 | * software flag. | |
328 | * | |
329 | * These generally need preemption protection to work, | |
330 | * do try to avoid using these on their own. | |
331 | */ | |
66af8e27 | 332 | static inline void fpregs_activate(struct fpu *fpu) |
1361b83a | 333 | { |
32b49b3c | 334 | __fpregs_activate_hw(); |
66af8e27 | 335 | __fpregs_activate(fpu); |
1361b83a LT |
336 | } |
337 | ||
66af8e27 | 338 | static inline void fpregs_deactivate(struct fpu *fpu) |
1361b83a | 339 | { |
66af8e27 | 340 | __fpregs_deactivate(fpu); |
32b49b3c | 341 | __fpregs_deactivate_hw(); |
1361b83a LT |
342 | } |
343 | ||
befc61ad IM |
344 | /* |
345 | * Definitions for the eXtended Control Register instructions | |
346 | */ | |
347 | ||
348 | #define XCR_XFEATURE_ENABLED_MASK 0x00000000 | |
349 | ||
350 | static inline u64 xgetbv(u32 index) | |
351 | { | |
352 | u32 eax, edx; | |
353 | ||
354 | asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ | |
355 | : "=a" (eax), "=d" (edx) | |
356 | : "c" (index)); | |
357 | return eax + ((u64)edx << 32); | |
358 | } | |
359 | ||
360 | static inline void xsetbv(u32 index, u64 value) | |
361 | { | |
362 | u32 eax = value; | |
363 | u32 edx = value >> 32; | |
364 | ||
365 | asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ | |
366 | : : "a" (eax), "d" (edx), "c" (index)); | |
367 | } | |
368 | ||
1361b83a LT |
369 | /* |
370 | * FPU state switching for scheduling. | |
371 | * | |
372 | * This is a two-stage process: | |
373 | * | |
374 | * - switch_fpu_prepare() saves the old state and | |
375 | * sets the new state of the CR0.TS bit. This is | |
376 | * done within the context of the old process. | |
377 | * | |
378 | * - switch_fpu_finish() restores the new state as | |
379 | * necessary. | |
380 | */ | |
381 | typedef struct { int preload; } fpu_switch_t; | |
382 | ||
cb8818b6 IM |
383 | static inline fpu_switch_t |
384 | switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu) | |
1361b83a LT |
385 | { |
386 | fpu_switch_t fpu; | |
387 | ||
304bceda SS |
388 | /* |
389 | * If the task has used the math, pre-load the FPU on xsave processors | |
390 | * or if the past 5 consecutive context-switches used math. | |
391 | */ | |
c5bedc68 | 392 | fpu.preload = new_fpu->fpstate_active && |
cb8818b6 | 393 | (use_eager_fpu() || new_fpu->counter > 5); |
1361ef29 | 394 | |
d5cea9b0 | 395 | if (old_fpu->fpregs_active) { |
4f836347 | 396 | if (!copy_fpregs_to_fpstate(old_fpu)) |
cb8818b6 | 397 | old_fpu->last_cpu = -1; |
1361ef29 | 398 | else |
cb8818b6 | 399 | old_fpu->last_cpu = cpu; |
1361ef29 | 400 | |
36b544dc | 401 | /* But leave fpu_fpregs_owner_ctx! */ |
d5cea9b0 | 402 | old_fpu->fpregs_active = 0; |
1361b83a LT |
403 | |
404 | /* Don't change CR0.TS if we just switch! */ | |
405 | if (fpu.preload) { | |
cb8818b6 | 406 | new_fpu->counter++; |
dfaea4e6 | 407 | __fpregs_activate(new_fpu); |
7366ed77 | 408 | prefetch(&new_fpu->state); |
32b49b3c IM |
409 | } else { |
410 | __fpregs_deactivate_hw(); | |
411 | } | |
1361b83a | 412 | } else { |
cb8818b6 IM |
413 | old_fpu->counter = 0; |
414 | old_fpu->last_cpu = -1; | |
1361b83a | 415 | if (fpu.preload) { |
cb8818b6 | 416 | new_fpu->counter++; |
66ddc2cb | 417 | if (fpu_want_lazy_restore(new_fpu, cpu)) |
1361b83a LT |
418 | fpu.preload = 0; |
419 | else | |
7366ed77 | 420 | prefetch(&new_fpu->state); |
232f62cd | 421 | fpregs_activate(new_fpu); |
1361b83a LT |
422 | } |
423 | } | |
424 | return fpu; | |
425 | } | |
426 | ||
427 | /* | |
428 | * By the time this gets called, we've already cleared CR0.TS and | |
429 | * given the process the FPU if we are going to preload the FPU | |
430 | * state - all we need to do is to conditionally restore the register | |
431 | * state itself. | |
432 | */ | |
384a23f9 | 433 | static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch) |
1361b83a | 434 | { |
384a23f9 | 435 | if (fpu_switch.preload) { |
0e75c54f | 436 | if (unlikely(copy_fpstate_to_fpregs(new_fpu))) |
fbce7782 | 437 | fpu__clear(new_fpu); |
1361b83a LT |
438 | } |
439 | } | |
440 | ||
441 | /* | |
442 | * Signal frame handlers... | |
443 | */ | |
c8e14041 | 444 | extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fx, int size); |
1361b83a LT |
445 | |
446 | /* | |
fb14b4ea | 447 | * Needs to be preemption-safe. |
1361b83a | 448 | * |
377ffbcc | 449 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
450 | * the save state. It does not do any saving/restoring on its own. In |
451 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
452 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 453 | */ |
1361b83a LT |
454 | static inline void user_fpu_begin(void) |
455 | { | |
4540d3fa IM |
456 | struct fpu *fpu = ¤t->thread.fpu; |
457 | ||
1361b83a | 458 | preempt_disable(); |
3c6dffa9 | 459 | if (!fpregs_active()) |
232f62cd | 460 | fpregs_activate(fpu); |
1361b83a LT |
461 | preempt_enable(); |
462 | } | |
463 | ||
78f7f1e5 | 464 | #endif /* _ASM_X86_FPU_INTERNAL_H */ |