projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1eeaed76 RM |
1 | /* |
| 2 | * Copyright (C) 1994 Linus Torvalds | |
| 3 | * | |
| 4 | * Pentium III FXSR, SSE support | |
| 5 | * General FPU state handling cleanups | |
| 6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
| 7 | * x86-64 work by Andi Kleen 2002 | |
| 8 | */ | |
| 9 | ||
| 1965aae3 PA |
10 | #ifndef _ASM_X86_I387_H |
| 11 | #define _ASM_X86_I387_H | |
| 1eeaed76 | 12 | |
| 3b0d6596 HX |
13 | #ifndef __ASSEMBLY__ |
| 14 | ||
| 1eeaed76 | 15 | #include <linux/sched.h> |
| e4914012 | 16 | #include <linux/hardirq.h> |
| 1361b83a LT |
17 | |
| 18 | struct pt_regs; | |
| 19 | struct user_i387_struct; | |
| 1eeaed76 | 20 | |
| aa283f49 | 21 | extern int init_fpu(struct task_struct *child); |
| 304bceda | 22 | extern void fpu_finit(struct fpu *fpu); |
| 36454936 | 23 | extern int dump_fpu(struct pt_regs *, struct user_i387_struct *); |
| 1361b83a | 24 | extern void math_state_restore(void); |
| 1eeaed76 | 25 | |
| 8546c008 LT |
26 | extern bool irq_fpu_usable(void); |
| 27 | extern void kernel_fpu_begin(void); | |
| 28 | extern void kernel_fpu_end(void); | |
| 1eeaed76 | 29 | |
| e4914012 SS |
30 | /* |
| 31 | * Some instructions like VIA's padlock instructions generate a spurious | |
| 32 | * DNA fault but don't modify SSE registers. And these instructions | |
| 0b8c3d5a CE |
33 | * get used from interrupt context as well. To prevent these kernel instructions |
| 34 | * in interrupt context interacting wrongly with other user/kernel fpu usage, we | |
| e4914012 SS |
35 | * should use them only in the context of irq_ts_save/restore() |
| 36 | */ | |
| 37 | static inline int irq_ts_save(void) | |
| 38 | { | |
| 39 | /* | |
| 0b8c3d5a CE |
40 | * If in process context and not atomic, we can take a spurious DNA fault. |
| 41 | * Otherwise, doing clts() in process context requires disabling preemption | |
| 42 | * or some heavy lifting like kernel_fpu_begin() | |
| e4914012 | 43 | */ |
| 0b8c3d5a | 44 | if (!in_atomic()) |
| e4914012 SS |
45 | return 0; |
| 46 | ||
| 47 | if (read_cr0() & X86_CR0_TS) { | |
| 48 | clts(); | |
| 49 | return 1; | |
| 50 | } | |
| 51 | ||
| 52 | return 0; | |
| 53 | } | |
| 54 | ||
| 55 | static inline void irq_ts_restore(int TS_state) | |
| 56 | { | |
| 57 | if (TS_state) | |
| 58 | stts(); | |
| 59 | } | |
| 60 | ||
| 15d8791c LT |
61 | /* |
| 62 | * The question "does this thread have fpu access?" | |
| 63 | * is slightly racy, since preemption could come in | |
| 64 | * and revoke it immediately after the test. | |
| 65 | * | |
| 66 | * However, even in that very unlikely scenario, | |
| 67 | * we can just assume we have FPU access - typically | |
| 68 | * to save the FP state - we'll just take a #NM | |
| 69 | * fault and get the FPU access back. | |
| 15d8791c LT |
70 | */ |
| 71 | static inline int user_has_fpu(void) | |
| 72 | { | |
| 1361b83a | 73 | return current->thread.fpu.has_fpu; |
| 1eeaed76 RM |
74 | } |
| 75 | ||
| 8546c008 | 76 | extern void unlazy_fpu(struct task_struct *tsk); |
| 1eeaed76 | 77 | |
| 3b0d6596 HX |
78 | #endif /* __ASSEMBLY__ */ |
| 79 | ||
| 1965aae3 | 80 | #endif /* _ASM_X86_I387_H */ |