[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / include / asm / intel-family.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_INTEL_FAMILY_H
#define _ASM_X86_INTEL_FAMILY_H

/*
 * "Big Core" Processors (Branded as Core, Xeon, etc...)
 *
 * While adding a new CPUID for a new microarchitecture, add a new
 * group to keep logically sorted out in chronological order. Within
 * that group keep the CPUID for the variants sorted by model number.
 *
 * The defined symbol names have the following form:
 *	INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
 * where:
 * OPTFAMILY	Describes the family of CPUs that this belongs to. Default
 *		is assumed to be "_CORE" (and should be omitted). Other values
 *		currently in use are _ATOM and _XEON_PHI
 * MICROARCH	Is the code name for the micro-architecture for this core.
 *		N.B. Not the platform name.
 * OPTDIFF	If needed, a short string to differentiate by market segment.
 *
 *		Common OPTDIFFs:
 *
 *			- regular client parts
 *		_L	- regular mobile parts
 *		_G	- parts with extra graphics on
 *		_X	- regular server parts
 *		_D	- micro server parts
 *
 *		Historical OPTDIFFs:
 *
 *		_EP	- 2 socket server parts
 *		_EX	- 4+ socket server parts
 *
 * The #define line may optionally include a comment including platform names.
 */

#define INTEL_FAM6_CORE_YONAH		0x0E

#define INTEL_FAM6_CORE2_MEROM		0x0F
#define INTEL_FAM6_CORE2_MEROM_L	0x16
#define INTEL_FAM6_CORE2_PENRYN		0x17
#define INTEL_FAM6_CORE2_DUNNINGTON	0x1D

#define INTEL_FAM6_NEHALEM		0x1E
#define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */
#define INTEL_FAM6_NEHALEM_EP		0x1A
#define INTEL_FAM6_NEHALEM_EX		0x2E

#define INTEL_FAM6_WESTMERE		0x25
#define INTEL_FAM6_WESTMERE_EP		0x2C
#define INTEL_FAM6_WESTMERE_EX		0x2F

#define INTEL_FAM6_SANDYBRIDGE		0x2A
#define INTEL_FAM6_SANDYBRIDGE_X	0x2D
#define INTEL_FAM6_IVYBRIDGE		0x3A
#define INTEL_FAM6_IVYBRIDGE_X		0x3E

#define INTEL_FAM6_HASWELL		0x3C
#define INTEL_FAM6_HASWELL_X		0x3F
#define INTEL_FAM6_HASWELL_L		0x45
#define INTEL_FAM6_HASWELL_G		0x46

#define INTEL_FAM6_BROADWELL		0x3D
#define INTEL_FAM6_BROADWELL_G		0x47
#define INTEL_FAM6_BROADWELL_X		0x4F
#define INTEL_FAM6_BROADWELL_D		0x56

#define INTEL_FAM6_SKYLAKE_L		0x4E
#define INTEL_FAM6_SKYLAKE		0x5E
#define INTEL_FAM6_SKYLAKE_X		0x55
#define INTEL_FAM6_KABYLAKE_L		0x8E
#define INTEL_FAM6_KABYLAKE		0x9E

#define INTEL_FAM6_CANNONLAKE_L		0x66

#define INTEL_FAM6_ICELAKE_X		0x6A
#define INTEL_FAM6_ICELAKE_D		0x6C
#define INTEL_FAM6_ICELAKE		0x7D
#define INTEL_FAM6_ICELAKE_L		0x7E
#define INTEL_FAM6_ICELAKE_NNPI		0x9D

#define INTEL_FAM6_TIGERLAKE_L		0x8C
#define INTEL_FAM6_TIGERLAKE		0x8D

#define INTEL_FAM6_COMETLAKE		0xA5
#define INTEL_FAM6_COMETLAKE_L		0xA6

/* "Small Core" Processors (Atom) */

#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
#define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */

#define INTEL_FAM6_ATOM_SALTWELL	0x36 /* Cedarview */
#define INTEL_FAM6_ATOM_SALTWELL_MID	0x27 /* Penwell */
#define INTEL_FAM6_ATOM_SALTWELL_TABLET	0x35 /* Cloverview */

#define INTEL_FAM6_ATOM_SILVERMONT	0x37 /* Bay Trail, Valleyview */
#define INTEL_FAM6_ATOM_SILVERMONT_D	0x4D /* Avaton, Rangely */
#define INTEL_FAM6_ATOM_SILVERMONT_MID	0x4A /* Merriefield */

#define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
#define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
#define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */

#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
#define INTEL_FAM6_ATOM_GOLDMONT_D	0x5F /* Denverton */

/* Note: the micro-architecture is "Goldmont Plus" */
#define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A /* Gemini Lake */

#define INTEL_FAM6_ATOM_TREMONT_D	0x86 /* Jacobsville */
#define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */

/* Xeon Phi */

#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */
#define INTEL_FAM6_XEON_PHI_KNM		0x85 /* Knights Mill */

/* Useful macros */
#define INTEL_CPU_FAM_ANY(_family, _model, _driver_data)	\
{								\
	.vendor		= X86_VENDOR_INTEL,			\
	.family		= _family,				\
	.model		= _model,				\
	.feature	= X86_FEATURE_ANY,			\
	.driver_data	= (kernel_ulong_t)&_driver_data		\
}

#define INTEL_CPU_FAM6(_model, _driver_data)			\
	INTEL_CPU_FAM_ANY(6, INTEL_FAM6_##_model, _driver_data)

#endif /* _ASM_X86_INTEL_FAMILY_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
970442c5 DH	2	#ifndef _ASM_X86_INTEL_FAMILY_H
	3	#define _ASM_X86_INTEL_FAMILY_H
	4
	5	/*
	6	* "Big Core" Processors (Branded as Core, Xeon, etc...)
	7	*
850eb9fb RB	8	* While adding a new CPUID for a new microarchitecture, add a new
	9	* group to keep logically sorted out in chronological order. Within
	10	* that group keep the CPUID for the variants sorted by model number.
12ece2d5 TL	11	*
	12	* The defined symbol names have the following form:
	13	* INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
	14	* where:
	15	* OPTFAMILY Describes the family of CPUs that this belongs to. Default
	16	* is assumed to be "_CORE" (and should be omitted). Other values
	17	* currently in use are _ATOM and _XEON_PHI
	18	* MICROARCH Is the code name for the micro-architecture for this core.
	19	* N.B. Not the platform name.
	20	* OPTDIFF If needed, a short string to differentiate by market segment.
a3d8c0d1 PZ	21	*
	22	* Common OPTDIFFs:
	23	*
	24	* - regular client parts
	25	* _L - regular mobile parts
	26	* _G - parts with extra graphics on
	27	* _X - regular server parts
	28	* _D - micro server parts
	29	*
	30	* Historical OPTDIFFs:
	31	*
	32	* _EP - 2 socket server parts
	33	* _EX - 4+ socket server parts
12ece2d5 TL	34	*
12ece2d5 TL	35	* The #define line may optionally include a comment including platform names.
970442c5 DH	36	*/
	37
	38	#define INTEL_FAM6_CORE_YONAH 0x0E
c238f234	39
970442c5 DH	40	#define INTEL_FAM6_CORE2_MEROM 0x0F
	41	#define INTEL_FAM6_CORE2_MEROM_L 0x16
	42	#define INTEL_FAM6_CORE2_PENRYN 0x17
	43	#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
	44
	45	#define INTEL_FAM6_NEHALEM 0x1E
4b3b234f	46	#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
970442c5 DH	47	#define INTEL_FAM6_NEHALEM_EP 0x1A
970442c5 DH	48	#define INTEL_FAM6_NEHALEM_EX 0x2E
c238f234	49
970442c5	50	#define INTEL_FAM6_WESTMERE 0x25
970442c5 DH	51	#define INTEL_FAM6_WESTMERE_EP 0x2C
	52	#define INTEL_FAM6_WESTMERE_EX 0x2F
	53
	54	#define INTEL_FAM6_SANDYBRIDGE 0x2A
	55	#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
	56	#define INTEL_FAM6_IVYBRIDGE 0x3A
	57	#define INTEL_FAM6_IVYBRIDGE_X 0x3E
	58
c66f78a6	59	#define INTEL_FAM6_HASWELL 0x3C
970442c5	60	#define INTEL_FAM6_HASWELL_X 0x3F
af239c44	61	#define INTEL_FAM6_HASWELL_L 0x45
5e741407	62	#define INTEL_FAM6_HASWELL_G 0x46
970442c5	63
c66f78a6	64	#define INTEL_FAM6_BROADWELL 0x3D
5e741407	65	#define INTEL_FAM6_BROADWELL_G 0x47
970442c5	66	#define INTEL_FAM6_BROADWELL_X 0x4F
5ebb34ed	67	#define INTEL_FAM6_BROADWELL_D 0x56
970442c5	68
af239c44	69	#define INTEL_FAM6_SKYLAKE_L 0x4E
c66f78a6	70	#define INTEL_FAM6_SKYLAKE 0x5E
970442c5	71	#define INTEL_FAM6_SKYLAKE_X 0x55
af239c44	72	#define INTEL_FAM6_KABYLAKE_L 0x8E
c66f78a6	73	#define INTEL_FAM6_KABYLAKE 0x9E
970442c5	74
af239c44	75	#define INTEL_FAM6_CANNONLAKE_L 0x66
850eb9fb	76
e35faeb6	77	#define INTEL_FAM6_ICELAKE_X 0x6A
5ebb34ed	78	#define INTEL_FAM6_ICELAKE_D 0x6C
c66f78a6	79	#define INTEL_FAM6_ICELAKE 0x7D
af239c44	80	#define INTEL_FAM6_ICELAKE_L 0x7E
e32d045c	81	#define INTEL_FAM6_ICELAKE_NNPI 0x9D
8cd8f0ce	82
6e1c32c5 GK	83	#define INTEL_FAM6_TIGERLAKE_L 0x8C
	84	#define INTEL_FAM6_TIGERLAKE 0x8D
	85
8d7c6ac3 KL	86	#define INTEL_FAM6_COMETLAKE 0xA5
	87	#define INTEL_FAM6_COMETLAKE_L 0xA6
	88
970442c5 DH	89	/* "Small Core" Processors (Atom) */
970442c5 DH	90
f2c4db1b PZ	91	#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
	92	#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
	93
	94	#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
	95	#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
	96	#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
	97
	98	#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
5ebb34ed	99	#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
f2c4db1b PZ	100	#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
	101
	102	#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
	103	#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
855fa1f3	104	#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
f2c4db1b PZ	105
f2c4db1b PZ	106	#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
5ebb34ed	107	#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
a3d8c0d1 PZ	108
a3d8c0d1 PZ	109	/* Note: the micro-architecture is "Goldmont Plus" */
f2c4db1b	110	#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
0a05fa67	111
5ebb34ed	112	#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
0f65605a	113	#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
970442c5 DH	114
	115	/* Xeon Phi */
	116
	117	#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
0047f598	118	#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
970442c5	119
e2ce67b2 AS	120	/* Useful macros */
	121	#define INTEL_CPU_FAM_ANY(_family, _model, _driver_data) \
	122	{ \
	123	.vendor = X86_VENDOR_INTEL, \
	124	.family = _family, \
	125	.model = _model, \
	126	.feature = X86_FEATURE_ANY, \
	127	.driver_data = (kernel_ulong_t)&_driver_data \
	128	}
	129
	130	#define INTEL_CPU_FAM6(_model, _driver_data) \
	131	INTEL_CPU_FAM_ANY(6, INTEL_FAM6_##_model, _driver_data)
	132
970442c5	133	#endif /* _ASM_X86_INTEL_FAMILY_H */