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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
970442c5 DH |
2 | #ifndef _ASM_X86_INTEL_FAMILY_H |
3 | #define _ASM_X86_INTEL_FAMILY_H | |
4 | ||
5 | /* | |
6 | * "Big Core" Processors (Branded as Core, Xeon, etc...) | |
7 | * | |
8 | * The "_X" parts are generally the EP and EX Xeons, or the | |
00ae831d | 9 | * "Extreme" ones, like Broadwell-E, or Atom microserver. |
970442c5 | 10 | * |
850eb9fb RB |
11 | * While adding a new CPUID for a new microarchitecture, add a new |
12 | * group to keep logically sorted out in chronological order. Within | |
13 | * that group keep the CPUID for the variants sorted by model number. | |
12ece2d5 TL |
14 | * |
15 | * The defined symbol names have the following form: | |
16 | * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF} | |
17 | * where: | |
18 | * OPTFAMILY Describes the family of CPUs that this belongs to. Default | |
19 | * is assumed to be "_CORE" (and should be omitted). Other values | |
20 | * currently in use are _ATOM and _XEON_PHI | |
21 | * MICROARCH Is the code name for the micro-architecture for this core. | |
22 | * N.B. Not the platform name. | |
23 | * OPTDIFF If needed, a short string to differentiate by market segment. | |
24 | * Exact strings here will vary over time. _DESKTOP, _MOBILE, and | |
25 | * _X (short for Xeon server) should be used when they are | |
26 | * appropriate. | |
27 | * | |
28 | * The #define line may optionally include a comment including platform names. | |
970442c5 DH |
29 | */ |
30 | ||
31 | #define INTEL_FAM6_CORE_YONAH 0x0E | |
c238f234 | 32 | |
970442c5 DH |
33 | #define INTEL_FAM6_CORE2_MEROM 0x0F |
34 | #define INTEL_FAM6_CORE2_MEROM_L 0x16 | |
35 | #define INTEL_FAM6_CORE2_PENRYN 0x17 | |
36 | #define INTEL_FAM6_CORE2_DUNNINGTON 0x1D | |
37 | ||
38 | #define INTEL_FAM6_NEHALEM 0x1E | |
4b3b234f | 39 | #define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */ |
970442c5 DH |
40 | #define INTEL_FAM6_NEHALEM_EP 0x1A |
41 | #define INTEL_FAM6_NEHALEM_EX 0x2E | |
c238f234 | 42 | |
970442c5 | 43 | #define INTEL_FAM6_WESTMERE 0x25 |
970442c5 DH |
44 | #define INTEL_FAM6_WESTMERE_EP 0x2C |
45 | #define INTEL_FAM6_WESTMERE_EX 0x2F | |
46 | ||
47 | #define INTEL_FAM6_SANDYBRIDGE 0x2A | |
48 | #define INTEL_FAM6_SANDYBRIDGE_X 0x2D | |
49 | #define INTEL_FAM6_IVYBRIDGE 0x3A | |
50 | #define INTEL_FAM6_IVYBRIDGE_X 0x3E | |
51 | ||
52 | #define INTEL_FAM6_HASWELL_CORE 0x3C | |
53 | #define INTEL_FAM6_HASWELL_X 0x3F | |
54 | #define INTEL_FAM6_HASWELL_ULT 0x45 | |
55 | #define INTEL_FAM6_HASWELL_GT3E 0x46 | |
56 | ||
57 | #define INTEL_FAM6_BROADWELL_CORE 0x3D | |
970442c5 DH |
58 | #define INTEL_FAM6_BROADWELL_GT3E 0x47 |
59 | #define INTEL_FAM6_BROADWELL_X 0x4F | |
c238f234 | 60 | #define INTEL_FAM6_BROADWELL_XEON_D 0x56 |
970442c5 DH |
61 | |
62 | #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E | |
63 | #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E | |
64 | #define INTEL_FAM6_SKYLAKE_X 0x55 | |
65 | #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E | |
66 | #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E | |
67 | ||
850eb9fb RB |
68 | #define INTEL_FAM6_CANNONLAKE_MOBILE 0x66 |
69 | ||
e35faeb6 KL |
70 | #define INTEL_FAM6_ICELAKE_X 0x6A |
71 | #define INTEL_FAM6_ICELAKE_XEON_D 0x6C | |
72 | #define INTEL_FAM6_ICELAKE_DESKTOP 0x7D | |
8cd8f0ce | 73 | #define INTEL_FAM6_ICELAKE_MOBILE 0x7E |
e32d045c | 74 | #define INTEL_FAM6_ICELAKE_NNPI 0x9D |
8cd8f0ce | 75 | |
5c11a5df GK |
76 | #define INTEL_FAM6_TIGERLAKE_L 0x8C |
77 | #define INTEL_FAM6_TIGERLAKE 0x8D | |
78 | ||
b44b8949 KL |
79 | #define INTEL_FAM6_COMETLAKE 0xA5 |
80 | #define INTEL_FAM6_COMETLAKE_L 0xA6 | |
81 | ||
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82 | /* "Small Core" Processors (Atom) */ |
83 | ||
f2c4db1b PZ |
84 | #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ |
85 | #define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */ | |
86 | ||
87 | #define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */ | |
88 | #define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */ | |
89 | #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */ | |
90 | ||
91 | #define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */ | |
92 | #define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */ | |
93 | #define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */ | |
94 | ||
95 | #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ | |
96 | #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ | |
97 | ||
98 | #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ | |
99 | #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */ | |
100 | #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ | |
0a05fa67 | 101 | |
00ae831d | 102 | #define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */ |
970442c5 DH |
103 | |
104 | /* Xeon Phi */ | |
105 | ||
106 | #define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ | |
0047f598 | 107 | #define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */ |
970442c5 | 108 | |
e2ce67b2 AS |
109 | /* Useful macros */ |
110 | #define INTEL_CPU_FAM_ANY(_family, _model, _driver_data) \ | |
111 | { \ | |
112 | .vendor = X86_VENDOR_INTEL, \ | |
113 | .family = _family, \ | |
114 | .model = _model, \ | |
115 | .feature = X86_FEATURE_ANY, \ | |
116 | .driver_data = (kernel_ulong_t)&_driver_data \ | |
117 | } | |
118 | ||
119 | #define INTEL_CPU_FAM6(_model, _driver_data) \ | |
120 | INTEL_CPU_FAM_ANY(6, INTEL_FAM6_##_model, _driver_data) | |
121 | ||
970442c5 | 122 | #endif /* _ASM_X86_INTEL_FAMILY_H */ |