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af2730f6 | 1 | /* |
05454c26 | 2 | * intel-mid.h: Intel MID specific setup code |
af2730f6 JP |
3 | * |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; version 2 | |
9 | * of the License. | |
10 | */ | |
05454c26 KS |
11 | #ifndef _ASM_X86_INTEL_MID_H |
12 | #define _ASM_X86_INTEL_MID_H | |
c20b5c33 FT |
13 | |
14 | #include <linux/sfi.h> | |
5823d089 | 15 | #include <linux/pci.h> |
40a96d54 | 16 | #include <linux/platform_device.h> |
c20b5c33 | 17 | |
712b6aa8 | 18 | extern int intel_mid_pci_init(void); |
5823d089 AS |
19 | extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); |
20 | ||
21 | #define INTEL_MID_PWR_LSS_OFFSET 4 | |
22 | #define INTEL_MID_PWR_LSS_TYPE (1 << 7) | |
23 | ||
24 | extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); | |
25 | ||
40a96d54 DC |
26 | extern int get_gpio_by_name(const char *name); |
27 | extern void intel_scu_device_register(struct platform_device *pdev); | |
7309282c | 28 | extern int __init sfi_parse_mrtc(struct sfi_table_header *table); |
aeedb370 | 29 | extern int __init sfi_parse_mtmr(struct sfi_table_header *table); |
7309282c FT |
30 | extern int sfi_mrtc_num; |
31 | extern struct sfi_rtc_table_entry sfi_mrtc_array[]; | |
af2730f6 | 32 | |
49c72a0a KS |
33 | /* |
34 | * Here defines the array of devices platform data that IAFW would export | |
35 | * through SFI "DEVS" table, we use name and type to match the device and | |
36 | * its platform data. | |
37 | */ | |
38 | struct devs_id { | |
39 | char name[SFI_NAME_LEN + 1]; | |
40 | u8 type; | |
41 | u8 delay; | |
42 | void *(*get_platform_data)(void *info); | |
43 | /* Custom handler for devices */ | |
44 | void (*device_handler)(struct sfi_device_table_entry *pentry, | |
45 | struct devs_id *dev); | |
46 | }; | |
47 | ||
40a96d54 DC |
48 | #define sfi_device(i) \ |
49 | static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ | |
50 | __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i | |
51 | ||
a0c173bd JP |
52 | /* |
53 | * Medfield is the follow-up of Moorestown, it combines two chip solution into | |
54 | * one. Other than that it also added always-on and constant tsc and lapic | |
55 | * timers. Medfield is the platform name, and the chip name is called Penwell | |
56 | * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be | |
57 | * identified via MSRs. | |
58 | */ | |
712b6aa8 | 59 | enum intel_mid_cpu_type { |
1a8359e4 | 60 | /* 1 was Moorestown */ |
712b6aa8 | 61 | INTEL_MID_CPU_CHIP_PENWELL = 2, |
85611e3f | 62 | INTEL_MID_CPU_CHIP_CLOVERVIEW, |
bc20aa48 | 63 | INTEL_MID_CPU_CHIP_TANGIER, |
a0c173bd JP |
64 | }; |
65 | ||
712b6aa8 | 66 | extern enum intel_mid_cpu_type __intel_mid_cpu_chip; |
35d47699 | 67 | |
85611e3f KS |
68 | /** |
69 | * struct intel_mid_ops - Interface between intel-mid & sub archs | |
70 | * @arch_setup: arch_setup function to re-initialize platform | |
71 | * structures (x86_init, x86_platform_init) | |
72 | * | |
73 | * This structure can be extended if any new interface is required | |
74 | * between intel-mid & its sub arch files. | |
75 | */ | |
76 | struct intel_mid_ops { | |
77 | void (*arch_setup)(void); | |
78 | }; | |
79 | ||
80 | /* Helper API's for INTEL_MID_OPS_INIT */ | |
81 | #define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \ | |
82 | [cpuid] = get_##cpuname##_ops | |
83 | ||
84 | /* Maximum number of CPU ops */ | |
85 | #define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) | |
86 | ||
87 | /* | |
88 | * For every new cpu addition, a weak get_<cpuname>_ops() function needs be | |
89 | * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h. | |
90 | */ | |
91 | #define INTEL_MID_OPS_INIT {\ | |
92 | DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ | |
93 | DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ | |
bc20aa48 | 94 | DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \ |
85611e3f KS |
95 | }; |
96 | ||
35d47699 MN |
97 | #ifdef CONFIG_X86_INTEL_MID |
98 | ||
712b6aa8 | 99 | static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) |
a75af580 | 100 | { |
712b6aa8 | 101 | return __intel_mid_cpu_chip; |
a75af580 PA |
102 | } |
103 | ||
40a96d54 DC |
104 | static inline bool intel_mid_has_msic(void) |
105 | { | |
106 | return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); | |
107 | } | |
108 | ||
35d47699 MN |
109 | #else /* !CONFIG_X86_INTEL_MID */ |
110 | ||
712b6aa8 | 111 | #define intel_mid_identify_cpu() (0) |
40a96d54 | 112 | #define intel_mid_has_msic() (0) |
35d47699 MN |
113 | |
114 | #endif /* !CONFIG_X86_INTEL_MID */ | |
115 | ||
712b6aa8 KS |
116 | enum intel_mid_timer_options { |
117 | INTEL_MID_TIMER_DEFAULT, | |
118 | INTEL_MID_TIMER_APBT_ONLY, | |
119 | INTEL_MID_TIMER_LAPIC_APBT, | |
a0c173bd JP |
120 | }; |
121 | ||
712b6aa8 | 122 | extern enum intel_mid_timer_options intel_mid_timer_options; |
14671386 | 123 | |
0a915326 DB |
124 | /* |
125 | * Penwell uses spread spectrum clock, so the freq number is not exactly | |
126 | * the same as reported by MSR based on SDM. | |
127 | */ | |
85611e3f KS |
128 | #define FSB_FREQ_83SKU 83200 |
129 | #define FSB_FREQ_100SKU 99840 | |
130 | #define FSB_FREQ_133SKU 133000 | |
131 | ||
132 | #define FSB_FREQ_167SKU 167000 | |
133 | #define FSB_FREQ_200SKU 200000 | |
134 | #define FSB_FREQ_267SKU 267000 | |
135 | #define FSB_FREQ_333SKU 333000 | |
136 | #define FSB_FREQ_400SKU 400000 | |
137 | ||
138 | /* Bus Select SoC Fuse value */ | |
139 | #define BSEL_SOC_FUSE_MASK 0x7 | |
140 | #define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ | |
141 | #define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ | |
142 | #define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ | |
0a915326 | 143 | |
16ab5395 | 144 | #define SFI_MTMR_MAX_NUM 8 |
cf089455 | 145 | #define SFI_MRTC_MAX 8 |
16ab5395 | 146 | |
1da4b1c6 FT |
147 | extern void intel_scu_devices_create(void); |
148 | extern void intel_scu_devices_destroy(void); | |
149 | ||
7309282c FT |
150 | /* VRTC timer */ |
151 | #define MRST_VRTC_MAP_SZ (1024) | |
152 | /*#define MRST_VRTC_PGOFFSET (0xc00) */ | |
153 | ||
712b6aa8 | 154 | extern void intel_mid_rtc_init(void); |
7309282c | 155 | |
40a96d54 DC |
156 | /* the offset for the mapping of global gpio pin to irq */ |
157 | #define INTEL_MID_IRQ_OFFSET 0x100 | |
158 | ||
05454c26 | 159 | #endif /* _ASM_X86_INTEL_MID_H */ |