[mirror_ubuntu-focal-kernel.git] / arch / x86 / include / asm / intel_rdt.h

#ifndef _ASM_X86_INTEL_RDT_H
#define _ASM_X86_INTEL_RDT_H

#define IA32_L3_CBM_BASE	0xc90
#define IA32_L2_CBM_BASE	0xd10

/**
 * struct rdt_resource - attributes of an RDT resource
 * @enabled:			Is this feature enabled on this machine
 * @capable:			Is this feature available on this machine
 * @name:			Name to use in "schemata" file
 * @num_closid:			Number of CLOSIDs available
 * @max_cbm:			Largest Cache Bit Mask allowed
 * @min_cbm_bits:		Minimum number of consecutive bits to be set
 *				in a cache bit mask
 * @domains:			All domains for this resource
 * @num_domains:		Number of domains active
 * @msr_base:			Base MSR address for CBMs
 * @tmp_cbms:			Scratch space when updating schemata
 * @cache_level:		Which cache level defines scope of this domain
 * @cbm_idx_multi:		Multiplier of CBM index
 * @cbm_idx_offset:		Offset of CBM index. CBM index is computed by:
 *				closid * cbm_idx_multi + cbm_idx_offset
 */
struct rdt_resource {
	bool			enabled;
	bool			capable;
	char			*name;
	int			num_closid;
	int			cbm_len;
	int			min_cbm_bits;
	u32			max_cbm;
	struct list_head	domains;
	int			num_domains;
	int			msr_base;
	u32			*tmp_cbms;
	int			cache_level;
	int			cbm_idx_multi;
	int			cbm_idx_offset;
};

/**
 * struct rdt_domain - group of cpus sharing an RDT resource
 * @list:	all instances of this resource
 * @id:		unique id for this instance
 * @cpu_mask:	which cpus share this resource
 * @cbm:	array of cache bit masks (indexed by CLOSID)
 */
struct rdt_domain {
	struct list_head	list;
	int			id;
	struct cpumask		cpu_mask;
	u32			*cbm;
};

/**
 * struct msr_param - set a range of MSRs from a domain
 * @res:       The resource to use
 * @low:       Beginning index from base MSR
 * @high:      End index
 */
struct msr_param {
	struct rdt_resource	*res;
	int			low;
	int			high;
};

extern struct mutex rdtgroup_mutex;

extern struct rdt_resource rdt_resources_all[];

enum {
	RDT_RESOURCE_L3,
	RDT_RESOURCE_L3DATA,
	RDT_RESOURCE_L3CODE,
	RDT_RESOURCE_L2,

	/* Must be the last */
	RDT_NUM_RESOURCES,
};

#define for_each_capable_rdt_resource(r)				      \
	for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
	     r++) 							      \
		if (r->capable)

#define for_each_enabled_rdt_resource(r)				      \
	for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
	     r++)							      \
		if (r->enabled)

/* CPUID.(EAX=10H, ECX=ResID=1).EAX */
union cpuid_0x10_1_eax {
	struct {
		unsigned int cbm_len:5;
	} split;
	unsigned int full;
};

/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
union cpuid_0x10_1_edx {
	struct {
		unsigned int cos_max:16;
	} split;
	unsigned int full;
};

void rdt_cbm_update(void *arg);
#endif /* _ASM_X86_INTEL_RDT_H */
Commit	Line	Data
113c6097 FY	1	#ifndef _ASM_X86_INTEL_RDT_H
	2	#define _ASM_X86_INTEL_RDT_H
	3
	4	#define IA32_L3_CBM_BASE 0xc90
c1c7c3f9	5	#define IA32_L2_CBM_BASE 0xd10
113c6097	6
c1c7c3f9 FY	7	/**
	8	* struct rdt_resource - attributes of an RDT resource
	9	* @enabled: Is this feature enabled on this machine
	10	* @capable: Is this feature available on this machine
	11	* @name: Name to use in "schemata" file
	12	* @num_closid: Number of CLOSIDs available
	13	* @max_cbm: Largest Cache Bit Mask allowed
	14	* @min_cbm_bits: Minimum number of consecutive bits to be set
	15	* in a cache bit mask
	16	* @domains: All domains for this resource
	17	* @num_domains: Number of domains active
	18	* @msr_base: Base MSR address for CBMs
	19	* @tmp_cbms: Scratch space when updating schemata
	20	* @cache_level: Which cache level defines scope of this domain
	21	* @cbm_idx_multi: Multiplier of CBM index
	22	* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
	23	* closid * cbm_idx_multi + cbm_idx_offset
	24	*/
	25	struct rdt_resource {
	26	bool enabled;
	27	bool capable;
	28	char *name;
	29	int num_closid;
	30	int cbm_len;
	31	int min_cbm_bits;
	32	u32 max_cbm;
	33	struct list_head domains;
	34	int num_domains;
	35	int msr_base;
	36	u32 *tmp_cbms;
	37	int cache_level;
	38	int cbm_idx_multi;
	39	int cbm_idx_offset;
	40	};
	41
2264d9c7 TL	42	/**
	43	* struct rdt_domain - group of cpus sharing an RDT resource
	44	* @list: all instances of this resource
	45	* @id: unique id for this instance
	46	* @cpu_mask: which cpus share this resource
	47	* @cbm: array of cache bit masks (indexed by CLOSID)
	48	*/
	49	struct rdt_domain {
	50	struct list_head list;
	51	int id;
	52	struct cpumask cpu_mask;
	53	u32 *cbm;
	54	};
	55
	56	/**
	57	* struct msr_param - set a range of MSRs from a domain
	58	* @res: The resource to use
	59	* @low: Beginning index from base MSR
	60	* @high: End index
	61	*/
	62	struct msr_param {
	63	struct rdt_resource *res;
	64	int low;
	65	int high;
	66	};
	67
	68	extern struct mutex rdtgroup_mutex;
	69
c1c7c3f9 FY	70	extern struct rdt_resource rdt_resources_all[];
	71
	72	enum {
	73	RDT_RESOURCE_L3,
	74	RDT_RESOURCE_L3DATA,
	75	RDT_RESOURCE_L3CODE,
	76	RDT_RESOURCE_L2,
	77
	78	/* Must be the last */
	79	RDT_NUM_RESOURCES,
	80	};
	81
	82	#define for_each_capable_rdt_resource(r) \
	83	for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
	84	r++) \
	85	if (r->capable)
	86
2264d9c7 TL	87	#define for_each_enabled_rdt_resource(r) \
	88	for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
	89	r++) \
	90	if (r->enabled)
	91
c1c7c3f9 FY	92	/* CPUID.(EAX=10H, ECX=ResID=1).EAX */
	93	union cpuid_0x10_1_eax {
	94	struct {
	95	unsigned int cbm_len:5;
	96	} split;
	97	unsigned int full;
	98	};
	99
	100	/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
	101	union cpuid_0x10_1_edx {
	102	struct {
	103	unsigned int cos_max:16;
	104	} split;
	105	unsigned int full;
	106	};
2264d9c7 TL	107
2264d9c7 TL	108	void rdt_cbm_update(void *arg);
113c6097	109	#endif /* _ASM_X86_INTEL_RDT_H */