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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1965aae3 PA |
2 | #ifndef _ASM_X86_IO_APIC_H |
3 | #define _ASM_X86_IO_APIC_H | |
e1d91978 | 4 | |
a1a33fa3 | 5 | #include <linux/types.h> |
e1d91978 TG |
6 | #include <asm/mpspec.h> |
7 | #include <asm/apicdef.h> | |
9d6a4d08 | 8 | #include <asm/irq_vectors.h> |
4a8e2a31 | 9 | #include <asm/x86_init.h> |
e1d91978 TG |
10 | /* |
11 | * Intel IO-APIC support for SMP and UP systems. | |
12 | * | |
13 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar | |
14 | */ | |
15 | ||
d3f020d2 CG |
16 | /* I/O Unit Redirection Table */ |
17 | #define IO_APIC_REDIR_VECTOR_MASK 0x000FF | |
18 | #define IO_APIC_REDIR_DEST_LOGICAL 0x00800 | |
19 | #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 | |
20 | #define IO_APIC_REDIR_SEND_PENDING (1 << 12) | |
21 | #define IO_APIC_REDIR_REMOTE_IRR (1 << 14) | |
22 | #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) | |
23 | #define IO_APIC_REDIR_MASKED (1 << 16) | |
24 | ||
e1d91978 TG |
25 | /* |
26 | * The structure of the IO-APIC: | |
27 | */ | |
28 | union IO_APIC_reg_00 { | |
29 | u32 raw; | |
30 | struct { | |
31 | u32 __reserved_2 : 14, | |
32 | LTS : 1, | |
33 | delivery_type : 1, | |
34 | __reserved_1 : 8, | |
35 | ID : 8; | |
36 | } __attribute__ ((packed)) bits; | |
37 | }; | |
38 | ||
39 | union IO_APIC_reg_01 { | |
40 | u32 raw; | |
41 | struct { | |
42 | u32 version : 8, | |
43 | __reserved_2 : 7, | |
44 | PRQ : 1, | |
45 | entries : 8, | |
46 | __reserved_1 : 8; | |
47 | } __attribute__ ((packed)) bits; | |
48 | }; | |
49 | ||
50 | union IO_APIC_reg_02 { | |
51 | u32 raw; | |
52 | struct { | |
53 | u32 __reserved_2 : 24, | |
54 | arbitration : 4, | |
55 | __reserved_1 : 4; | |
56 | } __attribute__ ((packed)) bits; | |
57 | }; | |
58 | ||
59 | union IO_APIC_reg_03 { | |
60 | u32 raw; | |
61 | struct { | |
62 | u32 boot_DT : 1, | |
63 | __reserved_1 : 31; | |
64 | } __attribute__ ((packed)) bits; | |
65 | }; | |
66 | ||
e1d91978 TG |
67 | struct IO_APIC_route_entry { |
68 | __u32 vector : 8, | |
69 | delivery_mode : 3, /* 000: FIXED | |
70 | * 001: lowest prio | |
71 | * 111: ExtINT | |
72 | */ | |
73 | dest_mode : 1, /* 0: physical, 1: logical */ | |
74 | delivery_status : 1, | |
75 | polarity : 1, | |
76 | irr : 1, | |
77 | trigger : 1, /* 0: edge, 1: level */ | |
78 | mask : 1, /* 0: enabled, 1: disabled */ | |
79 | __reserved_2 : 15; | |
80 | ||
e1d91978 TG |
81 | __u32 __reserved_3 : 24, |
82 | dest : 8; | |
e1d91978 | 83 | } __attribute__ ((packed)); |
e1d91978 | 84 | |
89027d35 SS |
85 | struct IR_IO_APIC_route_entry { |
86 | __u64 vector : 8, | |
87 | zero : 3, | |
88 | index2 : 1, | |
89 | delivery_status : 1, | |
90 | polarity : 1, | |
91 | irr : 1, | |
92 | trigger : 1, | |
93 | mask : 1, | |
94 | reserved : 31, | |
95 | format : 1, | |
96 | index : 15; | |
e1d91978 TG |
97 | } __attribute__ ((packed)); |
98 | ||
c4d05a2c | 99 | struct irq_alloc_info; |
f7a0c786 | 100 | struct ioapic_domain_cfg; |
c4d05a2c | 101 | |
335efdf5 TG |
102 | #define IOAPIC_AUTO -1 |
103 | #define IOAPIC_EDGE 0 | |
104 | #define IOAPIC_LEVEL 1 | |
105 | ||
106 | #define IOAPIC_MASKED 1 | |
107 | #define IOAPIC_UNMASKED 0 | |
108 | ||
109 | #define IOAPIC_POL_HIGH 0 | |
110 | #define IOAPIC_POL_LOW 1 | |
111 | ||
112 | #define IOAPIC_DEST_MODE_PHYSICAL 0 | |
113 | #define IOAPIC_DEST_MODE_LOGICAL 1 | |
114 | ||
d7f3d478 JL |
115 | #define IOAPIC_MAP_ALLOC 0x1 |
116 | #define IOAPIC_MAP_CHECK 0x2 | |
abb00522 | 117 | |
e1d91978 TG |
118 | #ifdef CONFIG_X86_IO_APIC |
119 | ||
120 | /* | |
121 | * # of IO-APICs and # of IRQ routing registers | |
122 | */ | |
123 | extern int nr_ioapics; | |
e1d91978 | 124 | |
d5371430 SS |
125 | extern int mpc_ioapic_id(int ioapic); |
126 | extern unsigned int mpc_ioapic_addr(int ioapic); | |
e1d91978 TG |
127 | |
128 | /* # of MP IRQ source entries */ | |
129 | extern int mp_irq_entries; | |
130 | ||
131 | /* MP IRQ source entries */ | |
c2c21745 | 132 | extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
e1d91978 | 133 | |
e1d91978 TG |
134 | /* 1 if "noapic" boot option passed */ |
135 | extern int skip_ioapic_setup; | |
136 | ||
a9322f64 SA |
137 | /* 1 if "noapic" boot option passed */ |
138 | extern int noioapicquirk; | |
139 | ||
9197979b SA |
140 | /* -1 if "noapic" boot option passed */ |
141 | extern int noioapicreroute; | |
142 | ||
154d9e50 JL |
143 | extern u32 gsi_top; |
144 | ||
8643e28d JL |
145 | extern unsigned long io_apic_irqs; |
146 | ||
147 | #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs)) | |
148 | ||
e1d91978 TG |
149 | /* |
150 | * If we use the IO-APIC for IRQ routing, disable automatic | |
151 | * assignment of PCI IRQ's. | |
152 | */ | |
153 | #define io_apic_assign_pci_irqs \ | |
154 | (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) | |
155 | ||
9b1b0e42 | 156 | struct irq_cfg; |
857fdc53 | 157 | extern void ioapic_insert_resources(void); |
11d686e9 | 158 | extern int arch_early_ioapic_init(void); |
e1d91978 | 159 | |
31dce14a SS |
160 | extern int save_ioapic_entries(void); |
161 | extern void mask_ioapic_entries(void); | |
162 | extern int restore_ioapic_entries(void); | |
4dc2f96c | 163 | |
de934103 | 164 | extern void setup_ioapic_ids_from_mpc(void); |
a38c5380 | 165 | extern void setup_ioapic_ids_from_mpc_nocheck(void); |
2a4ab640 | 166 | |
3eb2be5f JL |
167 | extern int mp_find_ioapic(u32 gsi); |
168 | extern int mp_find_ioapic_pin(int ioapic, u32 gsi); | |
c4d05a2c JL |
169 | extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
170 | struct irq_alloc_info *info); | |
df334bea | 171 | extern void mp_unmap_irq(int irq); |
35ef9c94 JL |
172 | extern int mp_register_ioapic(int id, u32 address, u32 gsi_base, |
173 | struct ioapic_domain_cfg *cfg); | |
15516a3b | 174 | extern int mp_unregister_ioapic(u32 gsi_base); |
e89900c9 | 175 | extern int mp_ioapic_registered(u32 gsi_base); |
f7a0c786 | 176 | |
c4d05a2c JL |
177 | extern void ioapic_set_alloc_attr(struct irq_alloc_info *info, |
178 | int node, int trigger, int polarity); | |
2a4ab640 | 179 | |
2d8009ba FT |
180 | extern void mp_save_irq(struct mpc_intsrc *m); |
181 | ||
7167d08e HK |
182 | extern void disable_ioapic_support(void); |
183 | ||
ca1b8862 | 184 | extern void __init io_apic_init_mappings(void); |
4a8e2a31 | 185 | extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg); |
1c4248ca | 186 | extern void native_disable_io_apic(void); |
4a8e2a31 KRW |
187 | |
188 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
189 | { | |
190 | return x86_io_apic_ops.read(apic, reg); | |
191 | } | |
192 | ||
8643e28d JL |
193 | extern void setup_IO_APIC(void); |
194 | extern void enable_IO_APIC(void); | |
195 | extern void disable_IO_APIC(void); | |
196 | extern void setup_ioapic_dest(void); | |
197 | extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin); | |
198 | extern void print_IO_APICs(void); | |
e1d91978 | 199 | #else /* !CONFIG_X86_IO_APIC */ |
78f28b7c | 200 | |
8643e28d | 201 | #define IO_APIC_IRQ(x) 0 |
e1d91978 | 202 | #define io_apic_assign_pci_irqs 0 |
de934103 | 203 | #define setup_ioapic_ids_from_mpc x86_init_noop |
857fdc53 | 204 | static inline void ioapic_insert_resources(void) { } |
11d686e9 | 205 | static inline int arch_early_ioapic_init(void) { return 0; } |
8643e28d | 206 | static inline void print_IO_APICs(void) {} |
a4384df3 | 207 | #define gsi_top (NR_IRQS_LEGACY) |
eddb0c55 | 208 | static inline int mp_find_ioapic(u32 gsi) { return 0; } |
c4d05a2c JL |
209 | static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
210 | struct irq_alloc_info *info) | |
211 | { | |
212 | return gsi; | |
213 | } | |
214 | ||
df334bea | 215 | static inline void mp_unmap_irq(int irq) { } |
78f28b7c | 216 | |
31dce14a | 217 | static inline int save_ioapic_entries(void) |
7d0f1926 HK |
218 | { |
219 | return -ENOMEM; | |
220 | } | |
221 | ||
31dce14a SS |
222 | static inline void mask_ioapic_entries(void) { } |
223 | static inline int restore_ioapic_entries(void) | |
7d0f1926 HK |
224 | { |
225 | return -ENOMEM; | |
226 | } | |
227 | ||
ca1b8862 | 228 | static inline void mp_save_irq(struct mpc_intsrc *m) { } |
7167d08e | 229 | static inline void disable_ioapic_support(void) { } |
ca1b8862 | 230 | static inline void io_apic_init_mappings(void) { } |
4a8e2a31 | 231 | #define native_io_apic_read NULL |
1c4248ca | 232 | #define native_disable_io_apic NULL |
86866083 TG |
233 | |
234 | static inline void setup_IO_APIC(void) { } | |
235 | static inline void enable_IO_APIC(void) { } | |
236 | static inline void setup_ioapic_dest(void) { } | |
237 | ||
96a388de | 238 | #endif |
e1d91978 | 239 | |
1965aae3 | 240 | #endif /* _ASM_X86_IO_APIC_H */ |